Ignore:
Timestamp:
Apr 1, 2015, 3:42:03 PM (10 years ago)
Author:
alain
Message:

Introducing a new IOC driver supporting the VciMultiAhci? disk controller (in polling mode only).
Extending the MMC driver to support the SYNC command requested by the AHCI protocol on the tsar_generic_iob platform.

Location:
trunk/softs/tsar_boot/drivers
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/softs/tsar_boot/drivers/reset_bdv.c

    r758 r962  
    4343};
    4444
     45////////////////////
    4546int reset_bdv_init()
    4647{
    … …  
    4849}
    4950
    50 int reset_bdv_read( unsigned int lba, void* buffer, unsigned int count )
     51////////////////////////////////////
     52int reset_bdv_read( unsigned int lba,
     53                    void* buffer,
     54                    unsigned int count )
    5155{
    52     /*
    53      * block_device configuration
    54      */
     56    // block_device configuration
    5557    iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], (unsigned int) buffer );
    5658    iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], count );
    … …  
    5860    iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE], 0 );
    5961
    60     /*
    61      * block_device trigger transfer
    62      */
     62    //  trigger transfer
    6363    iowrite32( &ioc_address[BLOCK_DEVICE_OP], ( unsigned int )
    6464               BLOCK_DEVICE_READ );
     65
     66#if (RESET_HARD_CC == 0) || USE_IOB
     67    // inval buffer in L1 cache
     68    reset_L1_inval( buffer , count * 512 );
     69#endif
     70
     71#if USE_IOB
     72    // inval buffer in L2 cache
     73    reset_L2_inval( buffer , count * 512 );
     74#endif
    6575
    6676    unsigned int status = 0;
    … …  
    7282            break;
    7383        }
    74         if ( status == BLOCK_DEVICE_READ_ERROR   ) {
     84        if ( status == BLOCK_DEVICE_READ_ERROR   )
     85        {
    7586            reset_puts("ERROR during read on the BLK device\n");
    7687            return 1;
    … …  
    7889    }
    7990
    80 #if (RESET_HARD_CC == 0) || USE_IOB
    81     reset_buf_invalidate(buffer, count * 512, USE_IOB);
    82 #endif
    8391    return 0;
    8492}

  • trunk/softs/tsar_boot/drivers/reset_inval.c

    r911 r962  
    22 * \file   reset_inval.c
    33 * \date   December 14, 2014
    4  * \author Cesar Fuguet
     4 * \author Cesar Fuguet / Alain Greiner
    55 */
    66
    … …  
    1313#endif
    1414
    15 static int* const mcc_address = (int* const)SEG_MMC_BASE;
     15static int* const mmc_address = (int* const)SEG_MMC_BASE;
    1616
    1717enum memc_registers
    … …  
    3131
    3232/**
    33  * \brief Invalidate all data cache lines corresponding to a memory buffer
    34  *        (identified by an address and a size) in L1 cache and L2 cache.
     33 * \brief Invalidate all L1 cache lines corresponding to a memory buffer
     34 *        (identified by an address and a size).
    3535 */
    36 void reset_buf_invalidate (void* const buffer, size_t size, int inval_memc)
     36void reset_L1_inval( void* const buffer, size_t size )
    3737{
    3838    unsigned int i;
    … …  
    4545            : /* no outputs */
    4646            : "i" (0x11), "R" (*((char*)buffer + i))
    47             : "memory"
    48             );
     47            : "memory" );
    4948    }
     49}
    5050
    51     if (inval_memc)
    52     {
    53         // this preloader uses only the cluster 0
    54         // It does not use the ADDR_HI bits, and does not take
    55         // any lock for exclusive access to MCC
    56         iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer);
    57         iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0);
    58         iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size);
    59         iowrite32(&mcc_address[MCC_CMD]    , (unsigned int) MCC_CMD_INVAL);
    60     }
     51/**
     52 * \brief Invalidate all L2 cache lines corresponding to a memory buffer
     53 *        (identified by an address and a size).
     54 */
     55void reset_L2_inval( void* const buffer, size_t size )
     56{
     57    iowrite32( &mmc_address[MCC_ADDR_LO], (unsigned int)buffer );
     58    iowrite32( &mmc_address[MCC_ADDR_HI], 0 );
     59    iowrite32( &mmc_address[MCC_LENGTH] , size );
     60    iowrite32( &mmc_address[MCC_CMD]    , MCC_CMD_INVAL);
     61}
     62
     63/**
     64 * \brief Update external RAM for all L2 cache lines corresponding to
     65 *        a memory buffer (identified by an address and a size).
     66 */
     67void reset_L2_sync ( void* const buffer, size_t size )
     68{
     69    iowrite32( &mmc_address[MCC_ADDR_LO], (unsigned int)buffer );
     70    iowrite32( &mmc_address[MCC_ADDR_HI], 0 );
     71    iowrite32( &mmc_address[MCC_LENGTH] , size );
     72    iowrite32( &mmc_address[MCC_CMD]    , MCC_CMD_SYNC );
    6173}
    6274

  • trunk/softs/tsar_boot/drivers/reset_inval.h

    r758 r962  
    1010#include <inttypes.h>
    1111
    12 void reset_mcc_invalidate (void* const buffer, size_t size);
     12void reset_L1_inval (void* const buffer, size_t size);
    1313
    14 void reset_buf_invalidate (void* const buffer, size_t size, int inval_memc);
     14void reset_L2_inval (void* const buffer, size_t size);
     15
     16void reset_L2_sync (void* const buffer, size_t size);
    1517
    1618#endif
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