Timeline
Sep 24, 2010:
- 6:38 PM Changeset [97] by
- Draft of new platform with VciSyntheticInitiator? and VDSPIN
Sep 21, 2010:
- 8:01 PM Changeset [96] by
- Redo ins TLB access bit update when it miss in dcache
Sep 18, 2010:
- 5:04 PM Changeset [95] by
- Platform with DMA and FB
Sep 14, 2010:
- 3:30 PM Changeset [94] by
- Deleting work directory
- 2:42 PM Changeset [93] by
- Platform with DMA
- 2:30 PM Changeset [92] by
- Platform with DMA VHDL
Sep 13, 2010:
- 6:15 PM Changeset [91] by
- polishing
- 5:17 PM Changeset [90] by
- Introducing a print_trace() method for debug.
Sep 11, 2010:
- 9:27 PM Changeset [89] by
- fixing bug vci_ring_initiator : fifo_wok
Sep 7, 2010:
Sep 6, 2010:
- 1:57 PM Changeset [88] by
- Correction of itlb access bit set and dtlb dirty bit set
Sep 5, 2010:
- 4:21 PM Changeset [87] by
- platform for new vdspin_router/vci_local_ring_fast
- 10:36 AM Changeset [86] by
- simple_ring_fast platform
Sep 3, 2010:
- 3:57 PM Changeset [85] by
- removing duplicate ring_signals_2
- 12:17 PM Changeset [84] by
- ICACHE_SW_FLUSH/ICACHE_CACHE_FLUSH: when walking the tlb/cache looking …
Sep 2, 2010:
- 2:27 PM Changeset [83] by
- Fix the masking of RERROR field
- 2:22 PM Changeset [82] by
- Add broadcast limitation compatibility, indicate the type of response …
- 10:45 AM InterconnexionNetworks edited by
- (diff)
Aug 31, 2010:
- 2:18 PM Changeset [81] by
- vci_synthetic_initiator draft
- 12:15 PM InterconnexionNetworks edited by
- (diff)
Aug 30, 2010:
Aug 29, 2010:
- 6:21 PM InterconnexionNetworks edited by
- (diff)
- 6:00 PM InterconnexionNetworks edited by
- (diff)
- 5:44 PM InterconnexionNetworks edited by
- (diff)
- 4:45 PM InterconnexionNetworks edited by
- (diff)
Aug 28, 2010:
- 7:10 PM Changeset [80] by
- Modified the coherence check for TLB entry updating
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