Timeline
Apr 17, 2013:
- 5:26 PM Changeset [370] by
- In tsarv5_generic_mmu : * top.cpp : go look for hard_config.h in …
- 4:53 PM Changeset [369] by
- Bugfix in vci_cc_vcache_wrapper v5 : forgot to copy the nline when …
Apr 16, 2013:
- 5:33 PM Changeset [368] by
- Modification in tsar/trunk/softs/tsar_boot Writing the carriage …
Apr 15, 2013:
- 7:59 PM InterconnexionNetworks edited by
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- 7:56 PM InterconnexionNetworks edited by
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- 7:54 PM InterconnexionNetworks edited by
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- 7:27 PM InterconnexionNetworks edited by
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- 11:59 AM InterconnexionNetworks edited by
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- 11:56 AM InterconnexionNetworks edited by
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- 11:55 AM Changeset [367] by
- Modification in v5/vci_mem_cache Aligning to left the SRCID into the …
- 11:49 AM InterconnexionNetworks edited by
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- 11:32 AM InterconnexionNetworks edited by
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Apr 12, 2013:
- 9:41 PM Changeset [366] by
- In vci_cc_vcache_wrapper v5, * now using the new generic_cache_tsar …
- 9:33 PM Changeset [365] by
- In generic_cache_tsar, added a new write_dir function that does not …
- 3:14 PM Changeset [364] by
- Bug fix in dcache fsm, in dcache_xtn_dc_inval_go state, set the slot …
Apr 10, 2013:
- 6:36 PM Changeset [363] by
- In tsarv5_generic_mmu platform, in tsar cluster, added l_width to …
- 12:58 PM Changeset [362] by
- Bugfix in vci_mem_cache: In function "copy()" of the xram_transaction …
- 12:54 PM Changeset [361] by
- Bugfix in vci_mem_cache_v4: In function "copy()" of the …
- 11:54 AM Changeset [360] by
- In tsarv5_generic_mmu platform (tsarcluster): * connected vci to dspin …
Apr 9, 2013:
- 5:10 PM Changeset [359] by
- bugfix : correctly updating the r_preempt register
- 12:34 PM Changeset [358] by
- bugfix : preempt in case of broadcast, palloc in case of single flit
Apr 8, 2013:
- 6:13 PM Changeset [357] by
- fixbug : test on eop in case of single_flit coherence request
- 1:46 PM Changeset [356] by
- Modifying comments in the dspin_dhccp_param to comply the type …
Apr 5, 2013:
- 7:21 PM Changeset [355] by
- In vci_cc_vcache_wrapper v5 - added check for p_dspin_in.write in …
- 4:28 PM Changeset [354] by
- Bugfix in branches/v5/vci_mem_cache Adding missing condition in …
- 4:17 PM Changeset [353] by
- Bugfix in branches/v5/vci_mem_cache Adding missing fifo get in case of …
Apr 4, 2013:
- 3:45 PM Changeset [352] by
- Bugfix in vci_cc_vcache_wrapper_v4: In case of SC or CAS command, the …
- 2:36 PM Changeset [351] by
- Got rid of intermediate v5 version. _dspin_coherence versions changed …
Apr 3, 2013:
- 10:41 PM Changeset [350] by
- Introducing Platform tsarv5_dspin_array, that can be used for TSAR …
Apr 2, 2013:
- 5:53 PM Changeset [349] by
- Rearranging addresses in the function pointer table to keep backward …
- 5:47 PM InterconnexionNetworks edited by
- fix error in dspin multi-ack packet descrption (diff)
- 2:23 PM Changeset [348] by
- Adding the boot_putc and the boot_getc in the functions pointer table …
Apr 1, 2013:
- 8:57 PM Changeset [347] by
- Introducing dcache line invalidation mechanism in the boot_ioc_read …
Mar 29, 2013:
- 6:56 PM Changeset [346] by
- New contructors for vci_mem_cache & vci_cc_vcache, as we don't need …
- 6:15 PM Changeset [345] by
- Introducing the cluster component in tsarv5_generic_mmu platform.
- 6:07 PM Changeset [344] by
- Introducing the tsarv5_generic_mmu platform.
- 10:00 AM Changeset [343] by
- Using the Xicu SOFT IRQs (IPIs). Adding them on the Xicu constructor
Mar 28, 2013:
- 7:30 PM Changeset [342] by
- Introducing tsar_generic_mmu_dspin_coherence platform (ring dspin for …
- 7:08 PM Changeset [341] by
- In vci_cc_vcache_wrapper_dspin_coherence, DCACHE_TLB_PTE1_MISS and …
- 6:25 PM Changeset [340] by
- Erasing always false condition in the if statement of the …
- 6:23 PM Changeset [339] by
- Erasing always false condition in the if statement of the …
- 2:12 PM Changeset [338] by
- * In vci_cc_vcache_wrapper_dspin_coherence, modified both states …
- 1:50 PM Changeset [337] by
- In generic_cache_tsar, added new read function that returns 2 32bits …
Mar 27, 2013:
- 2:25 PM Changeset [336] by
- Bug fix in the vci_cc_vcache_wrapper and vci_mem_cache components (and …
Mar 26, 2013:
- 11:15 AM Changeset [335] by
- Added llsc table initialization in both vci_mem_cache and …
- 11:12 AM Changeset [334] by
- Separated stat counters resets from internal registers resets
Mar 23, 2013:
Mar 22, 2013:
- 5:40 PM Changeset [333] by
- - In vci_cc_vcache_wrapper_dspin_coherence : initializing …
Mar 21, 2013:
- 4:21 PM Changeset [332] by
- Updated top.cpp in tsar_mono_mmu_dspin_coherence to respect new file …
- 4:06 PM Changeset [331] by
- Renaming all files form vci_cc_vcache_wrapper_dspin_coherence and …
Mar 20, 2013:
- 10:55 AM Changeset [330] by
- * Commented debug in dspin_local_ring_fast_c * Added test on plen …
Mar 19, 2013:
- 2:18 PM InterconnexionNetworks edited by
- updated table for types encoding from L2 to L1 (diff)
- 2:06 PM InterconnexionNetworks edited by
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- 2:04 PM InterconnexionNetworks edited by
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- 1:27 PM InterconnexionNetworks edited by
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- 1:11 PM InterconnexionNetworks edited by
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- 1:06 PM InterconnexionNetworks edited by
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- 1:01 PM InterconnexionNetworks edited by
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- 12:57 PM InterconnexionNetworks edited by
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- 12:55 PM InterconnexionNetworks edited by
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- 12:53 PM InterconnexionNetworks edited by
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- 10:56 AM WikiStart edited by
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- 10:51 AM InterconnexionNetworks edited by
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Mar 18, 2013:
- 4:48 PM InterconnexionNetworks edited by
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- 4:33 PM InterconnexionNetworks edited by
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- 4:15 PM InterconnexionNetworks edited by
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- 3:54 PM Changeset [329] by
- Added test on INST/DATA for the CLACK in the …
- 3:51 PM InterconnexionNetworks edited by
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- 3:45 PM Changeset [328] by
- Including TYPE_CLEANUP_ACK_INST and TYPE_CLEANUP_ACK_DATA in the …
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