[237] | 1 | Embedded systems (SoC and MPSoC) became an inevitable evolution in the microelectronic industry. |
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[97] | 2 | Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) |
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[99] | 3 | is not an option for SMEs (Small and Medium Enterprises). |
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| 4 | Fortunately, the new FPGA (Field Programmable Gate Array) components, |
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| 5 | such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete |
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| 6 | multi-processor architecture on a single device. |
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| 7 | But the design of embedded system is a long and complex task that requires expertise in software, |
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| 8 | software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling. |
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| 9 | Only very few SMEs have these multiple expertises and are present on the embedded system market. |
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[297] | 10 | Furthermore, even small design services in the big companies are facing the same issue. |
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[99] | 11 | \begin{center}\begin{minipage}{.8\linewidth}\textit{ |
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[297] | 12 | The major objective of COACH is to provide to system designers, an affordable |
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| 13 | open-source framework to design embedded systems on FPGA devices. |
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[99] | 14 | }\end{minipage}\end{center} |
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[97] | 15 | %Current design methodologies provide quite low-level abstraction capabilities, and |
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| 16 | %there is an urgent need to leverage system level exploration through the use of a high-level |
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| 17 | %specification of the application and design space exploration tools. |
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| 18 | %The first system oriented approaches are appearing, among which those |
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| 19 | %based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs. |
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[99] | 20 | %%% |
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| 21 | \parlf |
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[297] | 22 | The COACH project will propose a new design flow based on a small number of architectural templates. |
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[237] | 23 | An architectural template is a generic, parameterized architecture, relying on a predefined library |
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[97] | 24 | of IP cores. |
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| 25 | Besides using a specific collection of general purpose IP cores (such as processors cores, |
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| 26 | embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural |
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| 27 | template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools. |
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| 28 | During this project, the COACH partners will develop three different architectural templates: |
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| 29 | \begin{enumerate} |
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[172] | 30 | \item An \altera architectural template based on the \altera IP core library, the AVALON system bus and the NIOS processor. |
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| 31 | \item A \xilinx architectural template based on the \xilinx IP core library, the PLB system bus and the Microblaze processor. |
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[99] | 32 | \item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP |
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| 33 | communication infrastructure. |
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[97] | 34 | \end{enumerate} |
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| 35 | The proposed design flow starts from a high level description of the application, specified as a set of |
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| 36 | parallel tasks written in C, without any assumption on the hardware or software implementation |
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[172] | 37 | of these tasks. It lets the system |
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[99] | 38 | designer in charge of expressing the coarse grain parallelism of the application, gives the designer |
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[97] | 39 | the possibility to explore various mapping of the application on the selected template architecture, |
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| 40 | and offers a high predictability of results with respect to cost and performance objectives. |
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[99] | 41 | \\ |
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[97] | 42 | When this interactive, system level, design space exploration is completed (converging to |
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| 43 | a specific mapping on a specific version of the selected architectural template), the rest of the flow |
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[297] | 44 | is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary |
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| 45 | code for the software running on the embedded processors, and the bit-stream to program the target FPGA |
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[97] | 46 | will be automatically generated by the COACH tools. |
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[99] | 47 | % |
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| 48 | \parlf |
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[97] | 49 | The strength of the COACH approach is the strong integration of the high-level synthesis tools |
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[170] | 50 | in a platform based design flow supporting virtual prototyping and design space exploration. |
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[97] | 51 | Most building blocks already exist (resulting from previous projects): the GAUT |
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[297] | 52 | or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology, |
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| 53 | the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool, |
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| 54 | as well as the SoCLib library of SystemC simulation models. |
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| 55 | They must now be enhanced and integrated in a consistent design flow: this will |
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| 56 | be done in Magillem framework thanks to the IP-XACT standard. |
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[97] | 57 | %The five academic laboratories worked very closely during more than one year (one monthly meeting |
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| 58 | %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating |
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| 59 | %those various technologies, and to define the detailed architecture of the proposed design flow. |
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[99] | 60 | %%% |
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| 61 | \parlf |
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[297] | 62 | In HPC (High Performance Computing), the targeted application is an existing one |
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[99] | 63 | running on a PC. |
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| 64 | The COACH framework helps designer to accelerate it by migrating critical parts into a |
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| 65 | SoC embedded into an FPGA device plugged to the PC PCI/X bus. |
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| 66 | \begin{center}\begin{minipage}{.8\linewidth}\textit{ |
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[297] | 67 | The second objective of COACH is to extend the framework for HPC applications. |
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[99] | 68 | }\end{minipage}\end{center} |
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| 69 | This will allow SMEs to enter HPC market for the applications that are |
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| 70 | unadapted to the current GPU based solutions. |
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| 71 | %%% |
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