[12] | 1 | % les objectifs scientifiques/techniques du projet. |
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[269] | 2 | The design steps are presented figure~\ref{coach-flow}. |
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[12] | 3 | \begin{figure}[hbtp]\leavevmode\center |
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| 4 | \includegraphics[width=.8\linewidth]{flow} |
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[182] | 5 | \caption{\label{coach-flow} COACH design flow} |
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[12] | 6 | \end{figure} |
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| 7 | \begin{description} |
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[104] | 8 | \item[HPC setup:] During this step, the user splits the application into 2 parts: the host application |
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[269] | 9 | which remains on the PC and the SoC application which is mapped on the FPGA. |
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| 10 | COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC) |
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| 11 | which will allow performance evaluation. |
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[104] | 12 | \item[SoC design:] In this phase, |
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[269] | 13 | COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels. |
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| 14 | The user input will consist of a process network describing the coarse grain parallelism |
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| 15 | of the application, an instance of a generic hardware platform |
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| 16 | and a mapping of processes on the platform components. |
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| 17 | COACH will offer different targets to map the processes: |
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| 18 | software (the process runs as a software task on a SoC processor), |
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| 19 | ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), |
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| 20 | and hardware (the process is implemented as a synthesized hardware coprocessor). |
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| 21 | \item[Application compilation:] Once the SoC architecture is validated through performances |
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| 22 | analysis, COACH will generate automatically an executable containing the host application and |
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| 23 | the FPGA bitstream. This bitstream contains |
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| 24 | both the hardware architecture and the SoC application software. |
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| 25 | The user will be able to launch the application by |
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[33] | 26 | loading the bitstream on an FPGA and running the executable on PC. |
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[12] | 27 | \end{description} |
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| 28 | |
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| 29 | % l'avancee scientifique attendue. Preciser l'originalite et le caractere |
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| 30 | % ambitieux du projet. |
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[104] | 31 | %FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire} |
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[12] | 32 | |
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[182] | 33 | %The main scientific contribution of the project is to unify various synthesis techniques |
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| 34 | %(same input and output formats) allowing the user to swap without engineering effort |
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| 35 | %from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis. |
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| 36 | %Another advantage of this framework is to provide different abstraction levels from |
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| 37 | %a single description. |
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| 38 | %Finally, this description is device family independent and its hardware implementation |
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| 39 | %is automatically generated. |
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| 40 | |
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[12] | 41 | % Detailler les verrous scientifiques et techniques a lever par la realisation du projet. |
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[269] | 42 | Hardware/Software co-design is a very complex task. To simplify it, COACH will address the |
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| 43 | following scientific and technological barriers: |
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| 44 | \begin{description} |
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| 45 | \item[\textit{Design Space Exploration by Virtual Prototyping}]: |
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| 46 | The COACH environment will allow to easily map a parallel application described as a process |
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[235] | 47 | network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will |
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[238] | 48 | permit to explore the design space by allowing system designer to select and |
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[235] | 49 | parameterize the target architecture, and to define the best hardware/software |
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| 50 | partitioning of the application. |
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[269] | 51 | \item[\textit{High-Level Synthesis}]: |
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[238] | 52 | COACH will allow the automatic generation of hardware accelerators when required |
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[269] | 53 | by using High-Level Synthesis (HLS) tools. These HLS tools will be |
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| 54 | fully integrated into a complete system-level design environment. |
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| 55 | Moreover, COACH will support both data and control dominated applications, |
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| 56 | and the HLS tools of COACH will support a common language and coding style |
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[238] | 57 | to avoid re-engineering by the designer. |
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| 58 | COACH will provide a tool which will automatically explore the micro-architectural |
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| 59 | design space of coprocessor. |
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[269] | 60 | \item[\textit{High-level code transformation}]: |
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[238] | 61 | COACH will allow to optimize the memory usage, to enhance the parallelism through |
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| 62 | loop transformations and parallelization. The challenge is to identify the coarse |
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| 63 | grained parallelism and to generate, |
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| 64 | from a sequential algorithm, application containing multiple communicating |
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| 65 | tasks. To this aim, one may adapt techniques which were developed in the 1990 for |
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| 66 | the construction of distributed programs. However, in the context of HLS, there are |
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| 67 | still several original problems to be solved, mainly to do with the construction of |
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| 68 | FIFO communication channels and with memory optimization. |
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| 69 | Additionnal preprocessing, source-level transformations, are thus |
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| 70 | required to improve the process. |
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| 71 | Particularly, this includes parallelism exposure and efficient memory mapping. |
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| 72 | COACH will support code transformation by providing a source to source C2C tool. |
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[269] | 73 | \item[\textit{Hardware/Software communication middleware}]: |
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[235] | 74 | COACH will implement an homogeneous HW/SW communication infrastructure and |
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| 75 | communication APIs (Application Programming Interface), that will be used for |
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| 76 | communications between software tasks running on embedded processors and |
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[238] | 77 | dedicated hardware coprocessors. This will allow explore the design space by |
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[249] | 78 | mapping the tasks of the application (described as a process network) on a |
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[238] | 79 | shared-memory, MPSoC architecture. |
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[269] | 80 | \item[\textit{Processor customization}]: |
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[238] | 81 | ASIP design will be addressed by the COACH project. COACH will allow system designers to explore |
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| 82 | the various level of interactions between the original CPU micro-architecture and its |
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| 83 | extension. It will also allow to retarget the compiler instruction-selection pass. Finally, |
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| 84 | COACH will integrate ASIP design in a complete System-level design framework. |
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[269] | 85 | \end{description} |
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[235] | 86 | |
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[12] | 87 | %Presenter les resultats escomptes en proposant si possible des criteres de reussite |
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| 88 | %et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en |
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| 89 | %fin de projet. |
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| 90 | The main result is the framework. It is composed concretely of: |
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[99] | 91 | a communication middleware for HPC, |
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| 92 | 5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, |
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[12] | 93 | Memory optimisation HLS and ASIP), |
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[99] | 94 | 3 architectural templates that are synthesizable and that can be prototyped, |
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[12] | 95 | one design space exploration tool, |
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[235] | 96 | 2 operating systems (DNA/OS and MUTEKH). |
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[12] | 97 | \\ |
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[99] | 98 | The framework fonctionality will be demonstrated with the demonstrators |
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| 99 | (see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 |
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[235] | 100 | page~\ref{subtask-tutorial}). |
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