source: anr/section-4.1.tex @ 225

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[12]1\begin{figure}\leavevmode\center
2\includegraphics[width=.8\linewidth]{architecture-csg}
[105]3\caption{\label{archi-csg} Software architecture for digital system generation}
[12]4%\end{figure}\begin{figure}\leavevmode\center
5\mbox{}\vspace*{1ex}\\
[21]6\includegraphics[width=1.0\linewidth]{architecture-hls}
[105]7\caption{\label{archi-hls} Software architecture of hardware accellerator synthesis}
[12]8%\end{figure}\begin{figure}\leavevmode\center
9\mbox{}\vspace*{1ex}\\
10\includegraphics[width=.8\linewidth]{architecture-hpc}
[105]11\caption{\label{archi-hpc} Software architecture of HPC}
[12]12\end{figure}
[56]13%FIXME: la figure ne montre que l'aspect simulation. Intégrer la partie génération (PC API, PCIX, FPGA-IP, bridge vers VCI, SoC API) serait un plus, non ?
[12]14%
[33]15Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc}
[65]16summarize the software architecture of the COACH framework we will develop.
[12]17In figures, the dotted boxes are the softwares or formats that COACH
[65]18has to provide and to support.
[99]19\parlf
[56]20For the system generation presented in figure~\ref{archi-csg}, the conductor
[21]21is the tool \verb!CSG! (COACH System Generator). Its inputs are a process
[119]22network describing the target application and the synthesis parameters.
[21]23The main parameters are the target hardware architectural template
[119]24with its instantiation parameters, the hardware/software mapping of the
[21]25tasks, the FPGA device and design constraints.
[119]26\verb+CSG+ thus requires an architectural template library, an operating system
[21]27library, two system hardware component (CPU, memories, BUS...) libraries
28(one for synthesis, one for simulation).
29For generating the coprocessor of a task mapped as hardware, \verb+CSG+
30controls the HAS tools described below.
31From these inputs \verb!CSG! can generate the entire system (both software \&
[183]32hardware) either as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
[21]33design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
[134]34launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the
[56]35FPGA device\footnote{Additional partial bitstreams are generated in case of
36 dynamic partial reconfiguration}.
[99]37\parlf
[21]38The software architecture for HAS is presented in figure~\ref{archi-hls}.
39The input is a single task of the process network. The HAS tools do not work
[12]40directly on the C++ task description but on an internal format called
[38]41\xcoach generated by a plugin into the GNU C compiler (GCC).
[183]42This will allow on the one hand to insure that all the tools will
[132]43accept the same C++ description and on the other hand make possible
[21]44their chaining. The front-end tools read a \xcoach description and generate
45a new \xcoach description that exibits more parallelism or implement
[132]46specific instructions for ASIP. The back-end tools read an \xcoach
47description and generate an \xcoachplus description. This is an \xcoach
48description annotated with hardware information (scheduling, binding) required by
[21]49the VHDL and systemC drivers.
50Furthermore, the back-end tools uses a macro-cell library (functional and memory
51unit).
[99]52\parlf
[21]53In addition to digital system design, HPC requires a supplementary
54partitioning step presented in figure~\ref{archi-hpc}. The designer
55splits the initial application (tag 1) in two parts: one still on the PC and the
56other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data
57through communication primitives (tag 2) implemented in a library.
[65]58To evaluate the relevance of the partitioning, the designer can build a
[21]59simulator. Once the partitioning is validated, the design of the FPGA part
60is done through \verb!CSG! (figure~\ref{archi-csg}).
[99]61\parlf
62The project is split into 8 tasks numbered from 1 to 8. There are described
[132]63below and detailled in section \ref{task-description}.
[99]64\begin{description}
65\item[Task-1: \textit{Project management}]
[132]66    This task relates to the monitoring of the COACH project.
[99]67\item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the
[21]68        project such as the defintion of the COACH inputs and outputs,
69    the internal formats (e.g. \xcoach), the architectural templates and
70    the design flow.
[183]71\item[Task-3: \textit{System generation}] This task addresses the prototyping and
72    the generation of digital system. Apart from HAS that belongs to task 3
[21]73    and 4, its components are those presented figure~\ref{archi-csg}
74    (e.g.  \verb!CSG!, operating systems).
[99]75\item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities:
[21]76    optimization of the memory usage, parallelism enhancement through loop
77    transformations, coarse grain parallelization and ASIP generation.
[99]78\item[Task-5: \textit{HAS back-end}] This task groups two functionalities:
[21]79    High-Level Synthesis of data dominated description and HLS of control
80    dominated description.
81    This task contains also the development of a frequency adaptator
82    that will allow the coprocessors to respect the processor \& the bus
83    frequency.
[99]84\item[Task-6: \textit{PC/FPGA communication middleware}]
[132]85    This task pools the features dedicated to HPC. These are mainly the
[183]86    validation of the partitioning (see figure~\ref{archi-hpc}), the sytem drivers for
[56]87    both PC and FPGA-SoC sides, the hardware communication components and
[183]88        the support for dynamic partial reconfiguration.
[99]89\item[Task-7: \textit{Industrial demonstrators}]
[33]90    This task groups the demonstrators of the COACH project.
[132]91    Most of them are industrial applications that will be developped within
92    the COACH framework.
93    Others consist in integrating the COACH framework as a driver of
94    industrial proprietary design tools.
[183]95\item[Task 8: \textit{Dissemination}]
[132]96    This task concerns the diffusion of the project results.
[99]97    It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!,
[183]98    \verb!T0+24! and \verb!T0+36!), the publication of a tutorial and user manuals on a WEB site, the publication
99        of research papers in international journals and conferences and the organization of workshops and tutorials in
100        international conferences.
[99]101\end{description}
[21]102%
[12]103\begin{figure}\leavevmode\center
[21]104%\includegraphics[width=.4\linewidth]{dependence-task}
105\includegraphics[width=0.70\linewidth]{dependence-task-h}
106\caption{\label{dependence-task}Task dependencies}
[12]107\end{figure}
[65]108Figure~\ref{dependence-task} presents the tasks dependencies.
[99]109"$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$.
[132]110The more bold the arrow, the more important is the impact.
[21]111The graph shows:
112\begin{itemize}
[132]113\item Notwithstanding that $T4$ and $T5$ functionalities are complementary,
114their developments are independent (thanks to the \xcoach internal format).
[99]115\item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may works
[132]116without $T4$ and $T5$ if we limit ourselves to digital systems without hardware
117accelerators.
118\item $T3$ strongly impacts $T6$ but $T3$ does not depend at all on
119$T6$. Hence demonstrators ($T7$) of embedded system would not be impacted if
[99]120$T6$ would fail. 
[132]121\item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) and is at the heart of
[65]122the COACH project.
[132]123\item The demonstrators developped in $T7$, of course strongly depends on the achievements
[105]124of the previous tasks ($T2$, $T3$, $T4$, $T5$, $T6$).
[99]125\item $T8$ and $T1$ respectively depends on and impacts all the other tasks.
[21]126\end{itemize}
[33]127This organisation offers enough robustness to insure the success of the
[99]128project except for the specification task $T2$.
129The only critical task in this chart is $T2$. \label{xcoach-problem}
[33]130However, the partners met
13110 times (a one day meeting per month) during the last year to prepare the
132specification and the project proposal. This gives us a degree of confidence
[99]133that $T2$ will be completed in time.
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