[45] | 1 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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[121] | 2 | \subsubsection{\inria (CAIRN \& COMPSYS teams)} |
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[45] | 3 | |
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[120] | 4 | Inria, the French national institute for research in computer science |
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| 5 | and control, operating under the dual authority of the Ministry of |
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| 6 | Research and the Ministry of Industry, is dedicated to fundamental and |
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| 7 | applied research in information and communication science and |
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| 8 | technology (ICST). The Institute also plays a major role in technology |
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| 9 | transfer by fostering training through research, diffusion of |
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| 10 | scientific and technical information, development, as well as |
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| 11 | providing expert advice and participating in international programs. |
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[96] | 12 | |
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[120] | 13 | By playing a leading role in the scientific community in the field and |
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| 14 | being in close contact with industry, INRIA is a major participant in |
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| 15 | the development of ICST in France. Throughout its eight research |
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| 16 | centres in Rocquencourt, Rennes, Sophia Antipolis, Grenoble, Nancy, |
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| 17 | Bordeaux, Lille and Saclay, INRIA has a workforce of 3 800, 2 800 of |
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| 18 | whom are scientists from INRIA and INRIA's partner organizations such |
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| 19 | as CNRS (the French National Center for Scientific Research), |
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| 20 | universities and leading engineering schools. They work in 168 joint |
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| 21 | research project-teams. Many INRIA researchers are also professors and |
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| 22 | approximately 1 000 doctoral students work on theses as part of INRIA |
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| 23 | research project-teams. |
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| 24 | |
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| 25 | INRIA develops many partnerships with industry and fosters technology |
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| 26 | transfer and company foundation in the field of ICST - some ninety |
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| 27 | companies have been founded with the support of INRIA-Transfert, a |
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| 28 | subsidiary of INRIA, specialized in guiding, evaluating, qualifying, |
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| 29 | and financing innovative high-tech IT start-up companies. INRIA is |
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| 30 | involved in standardization committees such as the IETF, ISO and the |
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| 31 | W3C of which INRIA was the European host from 1995 to 2002. |
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| 32 | |
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| 33 | INRIA maintains important international relations and exchanges. In |
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| 34 | Europe, INRIA is a member of ERCIM which brings together research |
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| 35 | institutes from 19 European countries. INRIA is a partner in about 120 |
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| 36 | FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also |
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| 37 | collaborates with numerous scientific and academic institutions abroad |
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| 38 | (joint laboratories such as LIAMA, associated research teams, training |
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| 39 | and internship programs).\\ |
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| 40 | |
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| 41 | Two \inria project-teams participate to this project. |
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| 42 | \begin{itemize} |
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| 43 | \item CAIRN. The CAIRN group of INRIA Rennes -- Bretagne Atlantique study |
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| 44 | reconfigurable system-on-chip, i.e. hardware systems whose |
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| 45 | configuration may change before or even during execution. To this end, |
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| 46 | CAIRN has 13 permanent researchers and a variable number of PhD students, post-docs and engineers. |
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| 47 | CAIRN intends to approach reconfigurable architectures from three |
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| 48 | angles: the invention of new reconfigurable platforms, the development |
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| 49 | of associated transformation, compilation and synthesis tools, and the |
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| 50 | exploration of the interaction between algorithms and architectures. |
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| 51 | CAIRN is a joint team with CNRS, INSA of Rennes, University of Rennes 1 and ENS Cachan. |
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| 52 | |
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| 53 | \item COMPSYS. The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team |
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[61] | 54 | of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du |
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[92] | 55 | Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers |
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[61] | 56 | and a variable number of PhD students and post-docs. Its field of |
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| 57 | expertise is compilation for embedded system, optimizing compilers |
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| 58 | and automatic parallelization. It has authored or contributed to |
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| 59 | several well known libraries for linear programming, polyhedra manipulation |
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| 60 | and optimization in general. It has strong industrial cooperations, notably |
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[120] | 61 | with ST Microelectronics and Thales. |
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| 62 | \end{itemize} |
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[45] | 63 | |
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[61] | 64 | |
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[45] | 65 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 66 | \subsubsection{\tima} |
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[82] | 67 | The TIMA laboratory ("Techniques of Informatics and Microelectronics |
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| 68 | for integrated systems Architecture") is a public research laboratory |
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| 69 | sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159), |
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[96] | 70 | Grenoble Institute of Technology (Grenoble-INP) and Universitᅵ Joseph Fourier |
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[82] | 71 | (UJF). |
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| 72 | The research topics cover the specification, design, verification, test, |
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| 73 | CAD tools and design methods for integrated systems, from analog and |
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| 74 | digital components on one end of the spectrum, to multiprocessor |
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| 75 | Systems-on-Chip together with their basic operating system on the other end. |
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[45] | 76 | |
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[119] | 77 | Currently, the lab employs 124 persons among which 60 PhD candidates, and runs |
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[82] | 78 | 32 ongoing French/European funded projects. |
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[119] | 79 | Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions |
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[82] | 80 | and had 243 PhD thesis defended. |
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| 81 | |
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| 82 | The System Level Synthesis Group (25 people including PhDs) is |
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| 83 | involved in several FP6, FP7, CATRENE and ANR projects. |
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| 84 | Its field of expertise is in CAD and architecture for Multiprocessor |
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| 85 | SoC and Hardware/Software interface. |
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| 86 | |
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[45] | 87 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 88 | \subsubsection{\ubs} |
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| 89 | |
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[64] | 90 | The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, |
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| 91 | de la Communication, et de la Connaissance), is a French CNRS laboratory |
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[119] | 92 | (UMR 3192) that groups 4 research centers in the west and south |
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| 93 | Brittany: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de |
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[64] | 94 | Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). |
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| 95 | \\ |
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| 96 | The Lab-STICC is composed of three departments: Microwave and equipments (MOM), |
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| 97 | Digital communications, Architectures and circuits (CACS) and Knowledge, |
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| 98 | information and decision (CID). The Lab-STICC represents a staff of 279 |
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[119] | 99 | peoples, including 115 researchers and 113 PhD students. |
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[64] | 100 | The scientific production during the last 4 years represents 20 |
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| 101 | books, 200 journal publications, 500 conference publications, 22 |
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| 102 | patents, 69 PhDs diploma. |
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| 103 | \par |
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| 104 | The UBS/Lab-STICC laboratory is involved in several national research |
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| 105 | projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, |
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| 106 | A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), |
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| 107 | CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE |
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| 108 | ...). It is also involved in European Project (e.g. ITEA/SPICES, |
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| 109 | IST/AETHER ...). These projects are conducted through tight cooperation |
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| 110 | with national and international companies and organizations (e.g. France |
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[123] | 111 | Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS, |
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[64] | 112 | BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former |
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| 113 | projects are for example the high-level synthesis tool GAUT, the UHLS |
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| 114 | syntax and semantics-oriented editor, the DSP power estimation tool |
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| 115 | Soft-explorer or the co-design framework Design Trotter. |
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| 116 | \\ |
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| 117 | \par |
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| 118 | The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), |
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| 119 | located in Lorient, is involved in COACH. |
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| 120 | The UBS/Lab-STICC is working on the design of complex electronic systems |
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| 121 | and circuits, especially but not exclusively focussing on real-time |
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| 122 | embedded systems, power and energy consumption optimization, high-level |
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| 123 | synthesis and IP design, digital communications, hardware/software |
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| 124 | co-design and ESL methodologies. The application targeted by the |
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| 125 | UBS/Lab-STICC are mainly from telecommunication and multimedia domains |
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| 126 | which enclose signal, image, video, vision, and communication processing. |
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| 127 | |
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| 128 | |
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[45] | 129 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 130 | \subsubsection{\upmc} |
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[99] | 131 | |
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[62] | 132 | University Pierre et Marie Curie (UPMC) is the largest university in France (7400 employees,38000 students). |
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| 133 | The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of UPMC, hosting |
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| 134 | more than 400 researchers, under the umbrella of the CNRS (Centre National de la Recherche Scientifique). |
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[99] | 135 | The \og System on Chip \fg Department of LIP6 consists of 80 people, including 40 PHD students. |
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[62] | 136 | The research focus on CAD tools and methods for VLSI and System on Chip design. |
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[99] | 137 | \parlf |
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[62] | 138 | The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. |
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| 139 | The SoC department has been involved in several european projects :IDPS, EVEREST, OMI-HIC, OMI-MACRAME, |
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| 140 | OMI-ARCHES, EUROPRO, COSY, Medea SMT, Medea MESA, Medea+ BDREAMS, Medea+ TSAR. |
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[99] | 141 | \parlf |
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[62] | 142 | The public domain VLSI CAD system ALLIANCE, developped at UPMC is installed in more than 200 universities worldwide. |
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| 143 | The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting |
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[79] | 144 | the SoCLib WEB server. |
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[97] | 145 | In the SoCLin platform, the DSX tool is used for design space exploration. |
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| 146 | It helps the system designer to describe the coarse grain parallelism of the software application |
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| 147 | as a Task and Communication Graph, to configure the hardware architecture, and to map the |
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| 148 | multi-task software application on the multi-processors architecture. |
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| 149 | The DSX toll will be extended to support the FPGA target. |
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| 150 | Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis |
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| 151 | of control-dominated coprocessors. |
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| 152 | This tool will be modified to be integrated in the Coach design flow. |
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[99] | 153 | \parlf |
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[62] | 154 | Even if the preferred dissemination policy for the Coach design flow will be the free software policy, |
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| 155 | (following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies |
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[123] | 156 | (including \zied) have been created by former researchers from the SoC department of LIP6 between 1997 and 2002. |
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[45] | 157 | |
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| 158 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 159 | \subsubsection{\xilinx} |
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| 160 | |
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[99] | 161 | \xilinx is the world leader in the domain of programmable logic circuits (FPGA). |
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[119] | 162 | \xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex |
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[99] | 163 | families) and in the other hand a software solution allowing exploiting the |
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| 164 | characteristics of these FPGA. |
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| 165 | \parlf |
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[119] | 166 | The tools proposed allow the designer to describe his architecture from a modeling |
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[99] | 167 | language (VHDL/Verilog) to an optimized architecture implemented to the selected |
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| 168 | technology. |
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| 169 | The team located at Grenoble is responsible of the logic synthesis tool development (XST) |
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| 170 | of the software solution, which aggregates all the steps allowing proceeding from a HDL |
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| 171 | model to a technological netlist: |
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| 172 | \begin{itemize} |
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| 173 | \item Compilation of HDL code and model generation at Register Transfer Level (RTL). |
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| 174 | \item RTL model optimizations. |
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| 175 | \item Inference and generation of optimized macro blocks (Finite states machine, counter). |
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[119] | 176 | \item Boolean equations generation for random logic. |
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[99] | 177 | \item Logical, mapping and timing optimizations. |
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| 178 | \end{itemize} |
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| 179 | \parlf |
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| 180 | The architectures developed by \xilinx offer a collection of technological primitives |
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| 181 | (variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory |
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[119] | 182 | and even configurable processor cores (Pico and MicroBlaze families). |
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| 183 | This kind of architecture allows, therefore, the designer to validate different |
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[99] | 184 | hardware/software possibilities in a High Level Synthesis (HLS) framework. |
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| 185 | \parlf |
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| 186 | The classical optimization techniques focus, mainly, on the frequency aspects and on |
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| 187 | available resources use. |
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| 188 | The optimizations, taking into account the consumption criteria, become critical due to |
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| 189 | the fact of the increase of the architecture complexity and due to the use of FPGA |
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| 190 | component for low power applications. |
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| 191 | |
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[45] | 192 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 193 | \subsubsection{\bull} |
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| 194 | |
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[99] | 195 | \bull designs and develops servers and software for an open environment, integrating the |
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| 196 | most advanced technologies. It brings to its customers its expertise and know-how to help |
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| 197 | them in the transformation of their information systems and to optimize their IT |
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| 198 | infrastructure and their applications. |
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| 199 | \parlf |
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| 200 | \bull is particularly present in the public sector, banking, finance, telecommunication |
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| 201 | and industry sectors. Capitalizing on its wide experience, the Group has a thorough |
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| 202 | understanding of the business and specific processes of these sectors, thus enabling it to |
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| 203 | efficiently advise and to accompany its customers. Its distribution network spreads to |
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| 204 | over 100 countries worldwide. |
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| 205 | \parlf |
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| 206 | The team participating to the COACH project is from the Server Development Department |
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| 207 | based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing |
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| 208 | hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range |
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| 209 | from architecture specification, ASIC design/verification/prototyping to board design and |
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| 210 | include also specific EDA development to complement standard tools. |
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| 211 | |
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[45] | 212 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 213 | \subsubsection{\thales} |
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| 214 | |
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[123] | 215 | \thales is a world leader for mission critical information systems, with activities in 3 |
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| 216 | core businesses: aerospace (with all major aircraft manufacturers as customers), defence, |
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| 217 | and security (including ground transportation solutions). It employs 68000 people |
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| 218 | worldwide, and is present in 50 countries. \thales develops its strategic capabilities in |
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| 219 | component, software and system engineering and architectures through its R \& T organization. |
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| 220 | Its six Divisions manage their strategy and technical co-ordination per domain with |
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| 221 | hundreds of Units in these Divisions developing their technical activities in close |
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| 222 | relationship with their market. In this environment, \thales Research \& Technology |
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| 223 | operates at the corporate level as the technical community network architect, in charge of |
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| 224 | developing upstream and \thales-wide R \& T activities, with vision and visibility. |
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| 225 | In support of \thales applications, TRT's mission is also to anticipate and speed up |
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| 226 | technology transfer from research to development in Divisions by developing collaborations |
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| 227 | in R\&T. |
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| 228 | |
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| 229 | Thales is international, but Europe-centered. Research \& Development activities are |
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| 230 | disseminated, and corporate Research and Technology is concentrated in Centres in France, |
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| 231 | the United Kingdom and the Netherlands. |
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| 232 | The R\&T in Thales emphasizes more particularly on critical information systems, |
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| 233 | processing, control and cognitive systems, and autonomous systems. |
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| 234 | |
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| 235 | A key mission of our R\&T centres is to have a bi-directional transfer, or âimpedance |
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| 236 | matchingâ function between the scientific research network and the corresponding |
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| 237 | businesses. Benefiting from its presence and visibility on the international scene in |
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| 238 | advanced sciences, technology and software, \thales Research \& Technology is perceived as |
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| 239 | a valuable partner of the best research centres (academic or industrial) through |
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| 240 | recognized scientists and research engineer participation in collaborative projects. |
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| 241 | The TRTâs Information Science and Technology Group is able to develop innovative solutions |
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| 242 | along the information chain exploiting sensors data, through expertise in: computational |
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| 243 | architectures in embedded systems, typically suitable for autonomous system environments, |
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| 244 | mathematics and technologies for decision involving information fusion and cognitive |
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| 245 | processing, and cooperative technologies including man system interaction. |
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| 246 | The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the |
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| 247 | Information Science and Technology Group. |
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| 248 | |
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| 249 | Like other labs of TRT, ESL is in charge of making the link between the needs from Thales |
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| 250 | business units and the emerging technologies, in particular through assessment and |
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| 251 | de-risking studies. |
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| 252 | It has a long experience on parallel architectures design, in particular on SIMD |
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| 253 | architectures used for image processing and signal processing applications and on |
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| 254 | reconfigurable architectures. |
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| 255 | ESL is also strongly involved in studies on programming tools for these types of |
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| 256 | architectures and has developed the SpearDE tool used in this project. |
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| 257 | The laboratory had coordinated the FP6 IST MORPHEUS project on reconfigurable technology, |
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| 258 | being highly involved in the associated programming toolset. |
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| 259 | |
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| 260 | The team is also involved in |
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| 261 | the FP6 IST FET AETHER project on self-adaptability technologies and coordinates national |
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| 262 | projects on MPSoC architecture and tools like the \verb+Ter@ops+ project (P\^{o}le de |
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| 263 | Comp\'{e}titivit\'{e} \verb+System@tic+) dedicated to the design of a MPSoC for intensive |
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| 264 | computing embedded systems. |
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| 265 | |
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[45] | 266 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 267 | \subsubsection{\zied} |
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| 268 | |
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[123] | 269 | \zied is an innovative start-up specialized in the conception of configurable circuits |
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| 270 | and the development of CAD tools. \zied provides a complete front-to-back-end generator |
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| 271 | of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs. |
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| 272 | \zied solution is based on a patented FPGA architecture delivering an unprecedented |
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| 273 | level of logic density. This high capacity is accessible using a traditional RTL flow from |
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| 274 | Verilog/VHDL synthesis all the way to bitstream generation. |
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| 275 | |
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| 276 | \zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the |
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| 277 | French National Competition for Business Startup and Innovative Technology in 2007 and |
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| 278 | 2009 in âemergenceâ and âcreationâ categories respectively. |
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| 279 | |
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[45] | 280 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% |
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| 281 | \subsubsection{\navtel} |
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| 282 | |
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[99] | 283 | \navtel was created in 1994 to develop flexible systems based on FPGAs and currently |
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| 284 | focuses on intelligent signal mining for knowlege based signal processing systems. |
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| 285 | The company main activity covers the following domains: satellite communication, |
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| 286 | aeronautics, imaging and security. |
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| 287 | \navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical |
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| 288 | and imaging systems and 30\% to its own research programmes in collaboration with French |
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| 289 | and international partners. |
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| 290 | \parlf |
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| 291 | The multi disciplinary technical team comprises 6 engineers for signal processing and |
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| 292 | hardware development and one technician. |
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| 293 | \parlf |
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| 294 | \navtel has its own Ph.D program which includes in the past (classification technology |
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| 295 | and MIMO for FPGA implementation) and currently the preparation of a project for remote |
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| 296 | sensing with signal intelligence for satellite application. The company participates in |
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| 297 | national and European level projects contributing to a strategic alliance between academic |
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| 298 | and industrial partners.\\ |
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| 299 | The current research covers particle filter applications for communication and RADAR, |
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| 300 | Cognitive Radio, Satellite communication, embedded super computing and focuses on low |
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| 301 | power algorithms for implementation in FPGA and soft computing. |
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| 302 | \parlf |
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| 303 | For manufacturing and industrialization, \navtel works with ISO certified partners. |
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| 304 | The company clients include the CNES, ThalÚs Alenia Space, ThalÚs Communication, EADS, |
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| 305 | Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase through to the |
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| 306 | system delivery. |
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| 307 | |
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| 308 | \begin{description} |
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| 309 | \item[Recognitions:]\mbox{} |
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| 310 | \begin{itemize} |
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| 311 | \item EC Challenge+ programme for innovative projects (promotion 9) |
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| 312 | \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg |
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| 313 | \item Recognition by the French Senate for company creation during the |
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| 314 | \og Semaine de l'entrepreneur \fg 2005. |
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| 315 | \end{itemize} |
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| 316 | \end{description} |
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