[26] | 1 | \begin{taskinfo} |
---|
| 2 | \let\UBS\leader |
---|
| 3 | \let\UPMC\enable |
---|
| 4 | \let\TIMA\enable |
---|
[113] | 5 | \let\XILINX\enable |
---|
[26] | 6 | \end{taskinfo} |
---|
| 7 | % |
---|
| 8 | \begin{objectif} |
---|
[56] | 9 | The objectives of this task are to provide the two HAS back-ends of the COACH project and |
---|
[188] | 10 | a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required |
---|
[278] | 11 | by the processors and the system bus. |
---|
[26] | 12 | \\ |
---|
[110] | 13 | The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach description and provides an |
---|
| 14 | \xcoachplus description, i.e. an \xcoach description annotated with hardware information such as |
---|
| 15 | variables binding to registers, operations bindings to cells/fonctional units, operation scheduling... |
---|
| 16 | The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable and the \xcoachplus being treated by |
---|
| 17 | the \novers{\specXcoachToSystemC} and the \novers{\specXcoachToVhdl} deliverables, |
---|
| 18 | this task strongly depends on task~1. |
---|
[26] | 19 | \par |
---|
| 20 | For the two HAS front-end, this task is based on the already existing HLS tools GAUT and |
---|
[40] | 21 | UGH. These tools are complementary and not in competition because they cover respectively |
---|
| 22 | data and control dominated designs. |
---|
[26] | 23 | \end{objectif} |
---|
[218] | 24 | |
---|
[52] | 25 | \begin{workpackage} |
---|
[278] | 26 | \subtask{Making HAS back-end to read \xcoach format} |
---|
| 27 | The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. |
---|
| 28 | by implementing the mechanism to read \xcoach format. |
---|
[26] | 29 | \begin{livrable} |
---|
[220] | 30 | \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0} |
---|
[110] | 31 | Release of the UGH software that reads \xcoach format. |
---|
[278] | 32 | \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0} |
---|
| 33 | Release of the GAUT software that is able to read \xcoach format. |
---|
[26] | 34 | \end{livrable} |
---|
[278] | 35 | % |
---|
| 36 | \subtask{Making HAS back-end to write \xcoachplus format} |
---|
| 37 | The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. |
---|
| 38 | by implementing the mechanism to write \xcoachplus format. |
---|
[26] | 39 | \begin{livrable} |
---|
[278] | 40 | \itemL{12}{18}{x}{\Supmc}{UGH integration}{0:2:4.0} |
---|
| 41 | Release of the UGH software that writes \xcoachplus format. |
---|
[223] | 42 | \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0} |
---|
[110] | 43 | Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format. |
---|
[26] | 44 | \end{livrable} |
---|
[278] | 45 | |
---|
| 46 | \subtask{Coprocessor frequency adaptation} |
---|
| 47 | In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors |
---|
[26] | 48 | generated by HLS synthesis must respect this frequency. However, the HLS tools can not |
---|
[40] | 49 | guarantee that the micro-architectures they generate accurately respect this |
---|
[26] | 50 | frequency. This is especially the case when the target is a FPGA device, because the |
---|
| 51 | delays are really known only after the RTL synthesis and that estimated delays used |
---|
[111] | 52 | by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts |
---|
[26] | 53 | the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL |
---|
| 54 | synthesis. |
---|
| 55 | \begin{livrable} |
---|
[218] | 56 | \itemV{0}{12}{d}{\Supmc}{Frequency calibration} |
---|
[278] | 57 | A document describing the set up of the coprocessor frequency calibration. |
---|
[218] | 58 | \itemV{12}{24}{x}{\Supmc}{Frequency calibration} |
---|
[222] | 59 | \setMacroInAuxFile{freqCalibrationVhdl} |
---|
[52] | 60 | A VHDL description of hardware added to the coprocessor to enable the calibration. |
---|
[218] | 61 | \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{2:.5:3.5} |
---|
[52] | 62 | The frequency calibration software consists of a driver in the FPGA-SoC operating |
---|
[126] | 63 | system and of a control software. |
---|
[26] | 64 | \end{livrable} |
---|
| 65 | \end{workpackage} |
---|