source: anr/task-4.tex @ 287

Last change on this file since 287 was 287, checked in by coach, 14 years ago

MAJ après réunion de travail Ivan, Magillem
Liste des livrables

File size: 3.8 KB
RevLine 
[26]1\begin{taskinfo}
2\let\UBS\leader
3\let\UPMC\enable
4\let\TIMA\enable
[113]5\let\XILINX\enable
[26]6\end{taskinfo}
7%
8\begin{objectif}
[56]9The objectives of this task are to provide the two HAS back-ends of the COACH project and
[188]10a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required
[278]11by the processors and the system bus.
[26]12\\
[110]13The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach description and provides an
14\xcoachplus description, i.e. an \xcoach description  annotated with hardware information such as
15variables binding to registers, operations bindings to cells/fonctional units, operation scheduling...
16The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable and the \xcoachplus being treated by
17the \novers{\specXcoachToSystemC} and the \novers{\specXcoachToVhdl} deliverables,
18this task strongly depends on task~1.
[26]19\par
20For the two HAS front-end, this task is based on the already existing HLS tools GAUT and
[40]21UGH. These tools are complementary and not in competition because they cover respectively
22data and control dominated designs.
[26]23\end{objectif}
[218]24
[52]25\begin{workpackage}
[278]26\subtask{Making HAS back-end to read \xcoach format}
27    The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework.
28    by implementing the mechanism to read \xcoach format.
[26]29    \begin{livrable}
[220]30    \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0}
[110]31        Release of the UGH software that reads \xcoach format.
[278]32    \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0}
33        Release of the GAUT software that is able to read \xcoach format.
[26]34    \end{livrable}
[278]35%
36\subtask{Making HAS back-end to write \xcoachplus format}
37    The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework.
38    by implementing the mechanism to write \xcoachplus format.
[26]39    \begin{livrable}
[278]40    \itemL{12}{18}{x}{\Supmc}{UGH integration}{0:2:4.0}
41        Release of the UGH software that writes \xcoachplus format.
[223]42    \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0}
[110]43        Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format.
[26]44    \end{livrable}
[287]45%
46\subtask{Adapting HAS tools to the COACH communication schemes}
47    \begin{livrable}
48    \itemL{12}{18}{x}{\Supmc}{UGH update for COACH communications}{0:2:4.0}
49        Release of the UGH software that interprets the API of task communication.
50    \itemL{12}{18}{x}{\Subs}{GAUT update for COACH communications}{0:2:4.0}
51        Release of the GAUT software that interprets the API of task communication.
52    \end{livrable}
[278]53
54\subtask{Coprocessor frequency adaptation}
55    In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
[26]56    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
[40]57    guarantee that the micro-architectures they generate accurately respect this
[26]58    frequency. This is especially the case when the target is a FPGA device, because the
59    delays are really known only after the RTL synthesis and that estimated delays used
[111]60    by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts
[26]61    the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
62    synthesis.
63    \begin{livrable}
[218]64    \itemV{0}{12}{d}{\Supmc}{Frequency calibration}
[278]65        A document describing the set up of the coprocessor frequency calibration.
[218]66    \itemV{12}{24}{x}{\Supmc}{Frequency calibration}
[222]67        \setMacroInAuxFile{freqCalibrationVhdl}
[52]68        A VHDL description of hardware added to the coprocessor to enable the calibration.
[218]69    \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{2:.5:3.5}
[52]70        The frequency calibration software consists of a driver in the FPGA-SoC operating
[126]71        system and of a control software.
[26]72    \end{livrable}
73\end{workpackage}
Note: See TracBrowser for help on using the repository browser.