Changeset 112 for anr

Timestamp:

Feb 8, 2010, 4:09:44 PM (15 years ago)

Author:

coach

Message:

pc

Location:

anr

Files:

• section-3.1.tex (modified) (1 diff)
• task-1.tex (modified) (3 diffs)
• task-2.tex (modified) (4 diffs)
• task-3.tex (modified) (2 diffs)
• task-4.tex (modified) (3 diffs)
• task-5.tex (modified) (3 diffs)

anr/section-3.1.tex

@@ -113 +113 @@
 Regarding these limitations, it is necessary to create a new tool generation reducing the gap 
 between the specification of an heterogeneous system and its hardware implementation.
-%FIXME == {Ajouter ref livre + D&T}
+\mustbecompleted {FIXME :: Ajouter ref livre + D&T}
 
 \subsubsection{Application Specific Instruction Processors}

anr/task-1.tex

@@ -27 +27 @@
         descriptions.
     \itemL{6}{12}{d}{\Supmc}{COACH specification}{1:0:0} \setMacroInAuxFile{specGenManual}
-        The final version of the {\specGenManualI} delivrable updated with the %FIXME == {first}
+        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
         feed-backs of the demonstrator \STs.
     \itemV{0}{6}{d}{\Stima}{CSG specification} \setMacroInAuxFile{specCsgManualI}
@@ -38 +38 @@
         synthesis.
     \itemL{6}{12}{d}{\Stima}{CSG specification}{1:0:0} \setMacroInAuxFile{specCsgManual}
-        The final version of the {\specGenManualI} delivrable updated with the %FIXME == {first}
+        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
         feed-backs
         of the demonstrator \STs.
@@ -47 +47 @@
         coprocessor synthesis.
     \itemL{6}{12}{d}{\Subs}{HAS specification}{1:0:0} \setMacroInAuxFile{specHasManual}
-        The final version of the {\specGenManualI} delivrable updated with the %FIXME == {first}
+        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
         feed-backs of
         the demonstrator \STs.

anr/task-2.tex

@@ -14 +14 @@
 \item the development of all the missing components (SytemC models and/or synthesizable VHDL models 
 of the IP-cores),
-\item the configuration and the development of drivers %FIXME == {driver de quoi ???}
+\item the configuration and the development of drivers \mustbecompleted{FIXME:: driver de quoi ???}
 of the operating systems,
 \item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description 
-of the FPGA-SoC system (i.e. its bitstream), %FIXME == {VHDL ou bitstream ???}
+of the FPGA-SoC system (i.e. its bitstream), \mustbecompleted{FIXME:: VHDL ou bitstream ???}
 \item the specification of enhanced communication schemes and their sofware and hardware implementations.
 \end{itemize}
@@ -37 +37 @@
         In this milestone only the SystemC prototyping will be supported for the XILINX
         and ALTERA architectural template.
-        HAS is available. %FIXME = {ca veut dire ???}
+        HAS is available. \mustbecompleted{FIXME:: ca veut dire ???}
     \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
         This milestone extends CSG (\csgPrototypingOnly) to
@@ -47 +47 @@
     \\
     For the COACH architectural template, it consists of the devlopment of the VHDL
-    synthesizable description of the missing components. %FIXME == {pas clair missing components} 
+    synthesizable description of the missing components. \mustbecompleted{FIXME :: pas clair missing components} 
     Notice that the SystemC models
     comes from the SocLib ANR project, the processor with its cache comes from the TSAR
@@ -92 +92 @@
     \begin{livrable}
     \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
-        The drivers %FIXME = {???}
+        The drivers \mustbecompleted{FIXME :: ???}
         required for the first CSG milestone (delivrable \csgCoachArch).
     \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}

anr/task-3.tex

@@ -15 +15 @@
 as possible, identify communication channels, and output an \xcoach
 description.
-%FIXME == {Impossible d'utiliser les transformations de boucles pour amélierer la partie SW ??? }
+\mustbecompleted {FIXME :: Impossible d'utiliser les transformations de boucles pour amélierer la partie SW ??? }
 \end{objectif}
 %
@@ -65 +65 @@
       Description of the process network construction method for programs with 
       polyhedral loops. User manual. 
-      %FIXME == {User manual ou Specification. Si user manual alors le mettre en dissemination}
+      \mustbecompleted{ FIXME :: User manual ou Specification. Si user manual alors le mettre en dissemination}
     \itemL{30}{36}{d}{\Slip}{Process generation method}{0:0:0}
       Final assessment of the method and improved version of the user manual.
-      %FIXME == {User manual ou Specification. Si user manual alors le mettre en dissemination}
+      \mustbecompleted {FIXME :: User manual ou Specification. Si user manual alors le mettre en dissemination}
     \itemV{6}{12}{x}{\Slip}{Process construction}
       Preliminary implementation in the Syntol framework. 

anr/task-4.tex

@@ -7 +7 @@
 \begin{objectif}
 The objectives of this task are to provide the two HAS back-ends of the COACH project and
-a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required %FIXME == {or defined}
+a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required \mustbecompleted {FIXME :: or defined}
 by the processors and the system BUS.
 %pourquoi en majuscule?
@@ -25 +25 @@
 with a few control for GAUT and control dominated application with a few data processing
 for UGH. This will enlarge the domain the HLS can cover which is a strong limitation of the 
-tools currently avilable. %FIXME == [ajouter ref LIVRE, D&T, CATRENE Roadmap]
+tools currently avilable. \mustbecompleted {FIXME :: ajouter ref LIVRE, Design and Test, CATRENE Roadmap}
 \end{objectif}
 %
@@ -93 +93 @@
     \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5}
         The frequency calibration software consists of a driver in the FPGA-SoC operating
-        system and of a control software on a PC. %FIXME == {Pas clair pour le HPC. Comprends pas}
+        system and of a control software on a PC. \mustbecompleted {FIXME :: Pas clair pour le HPC. Comprends pas}
     \end{livrable}
 \end{workpackage}

anr/task-5.tex

@@ -15 +15 @@
     (figure~\ref{archi-hpc}).
 \item Providing communication schemes between the software part running on the PC and the
-FPGA-SoC. %FIXME = {Quelle difference avec l'item qui suit ???}
+FPGA-SoC. \mustbecompleted{ FIXME :: Quelle difference avec l'item qui suit ???}
 \item Implementing the communication scheme at all levels: partition help, software
 implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
@@ -25 +25 @@
 transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
 their FPGA and that GPU HPC softwares use also it.
-%FIXME == {ai supprime (mis en commentaire) la phrse qui suivait}
+\mustbecompleted { FIXME :: ai supprime (mis en commentaire) la phrse qui suivait}
 %This will allow us at least to be inspired by GPU communication schemes and may be to reuse
 %parts of the GPU softwares.
@@ -31 +31 @@
 \end{objectif}
 %
-%FIXME == {Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???}
+\mustbecompleted { FIXME :: Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???}
 \begin{workpackage}
 \item This \ST is the definition of the communication schemes as a software API