Changeset 112 for anr/task-2.tex
- Timestamp:
- Feb 8, 2010, 4:09:44 PM (15 years ago)
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anr/task-2.tex
r108 r112 14 14 \item the development of all the missing components (SytemC models and/or synthesizable VHDL models 15 15 of the IP-cores), 16 \item the configuration and the development of drivers %FIXME == {driver de quoi ???}16 \item the configuration and the development of drivers \mustbecompleted{FIXME:: driver de quoi ???} 17 17 of the operating systems, 18 18 \item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description 19 of the FPGA-SoC system (i.e. its bitstream), %FIXME == {VHDL ou bitstream ???}19 of the FPGA-SoC system (i.e. its bitstream), \mustbecompleted{FIXME:: VHDL ou bitstream ???} 20 20 \item the specification of enhanced communication schemes and their sofware and hardware implementations. 21 21 \end{itemize} … … 37 37 In this milestone only the SystemC prototyping will be supported for the XILINX 38 38 and ALTERA architectural template. 39 HAS is available. %FIXME = {ca veut dire ???}39 HAS is available. \mustbecompleted{FIXME:: ca veut dire ???} 40 40 \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} 41 41 This milestone extends CSG (\csgPrototypingOnly) to … … 47 47 \\ 48 48 For the COACH architectural template, it consists of the devlopment of the VHDL 49 synthesizable description of the missing components. %FIXME == {pas clair missing components}49 synthesizable description of the missing components. \mustbecompleted{FIXME :: pas clair missing components} 50 50 Notice that the SystemC models 51 51 comes from the SocLib ANR project, the processor with its cache comes from the TSAR … … 92 92 \begin{livrable} 93 93 \itemV{6}{8}{x}{\Supmc}{MUTEK OS} 94 The drivers %FIXME = {???}94 The drivers \mustbecompleted{FIXME :: ???} 95 95 required for the first CSG milestone (delivrable \csgCoachArch). 96 96 \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
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