Changeset 113


Ignore:
Timestamp:
Feb 8, 2010, 11:40:38 PM (15 years ago)
Author:
coach
Message:

IA: updated pour XILINX

Location:
anr
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • anr/anr.sty

    r75 r113  
    1111\let\specHasManual\relax
    1212\let\specCsgManual\relax
     13\let\specXilinxOptimization\relax
    1314
    1415\def\setMacroInAuxFile#1{%
    … …  
    1819\def\eoa{end-of-args}
    1920\def\@novers#1-#2\eoa{#1}
    20 \def\novers#1{\expandafter\@novers#1\eoa}
     21\def\novers#1{\ifx\relax#1\def\next{{\color{red}FIXME}}\else\def\next{\expandafter\@novers#1\eoa}\fi\next}
    2122
    2223%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

  • anr/gantt.l

    r75 r113  
    768768int main()
    769769{
    770     int tnplus[10] = { 1, 7, 8, -1 };
    771     int tnmoins[10] = { 1, 7, 8, -1 };
     770    int tnplus[10] = { 1, 2, 3, 4, -1 };
     771    int tnmoins[10] = { 1, 2, 3, 4, -1 };
    772772
    773773    yylex();
    … …  
    784784    do_partner_table_full(4); do_partner_table_short(4);
    785785    do_partner_table_full(5); do_partner_table_short(5);
     786    do_partner_table_full(7); do_partner_table_short(7);
     787    do_partner_table_full(8); do_partner_table_short(8);
     788    do_partner_table_full(9); do_partner_table_short(9);
     789    do_partner_table_full(10); do_partner_table_short(10);
    786790
    787791    return 0;

  • anr/section-4.4.tex

    r56 r113  
    1717\hspace*{-.6cm}\vspace{-1.5cm}
    1818\input{gantt1.tex}
    19 \caption{\label{gantt1}Gantt diagram of delivrables (task-1 \& task-8)}
     19\caption{\label{gantt1}Gantt diagram of delivrables (task-1 to task-4)}
    2020\end{figure}
    2121
    … …  
    2323\hspace*{-.6cm}\vspace{-1.5cm}
    2424\input{gantt2.tex}
    25 \caption{\label{gantt2}Gantt diagram of delivrables (task-2 to task-7)}
     25\caption{\label{gantt2}Gantt diagram of delivrables (task-5 to task-8)}
    2626\end{figure}
    2727

  • anr/task-1.tex

    r112 r113  
    2828    \itemL{6}{12}{d}{\Supmc}{COACH specification}{1:0:0} \setMacroInAuxFile{specGenManual}
    2929        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
    30         feed-backs of the demonstrator \STs.
     30            feed-backs of the demonstrator \STs.
    3131    \itemV{0}{6}{d}{\Stima}{CSG specification} \setMacroInAuxFile{specCsgManualI}
    3232        The first version of the CSG (COACH System Generator) specification.
    … …  
    3939    \itemL{6}{12}{d}{\Stima}{CSG specification}{1:0:0} \setMacroInAuxFile{specCsgManual}
    4040        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
    41         feed-backs
    42         of the demonstrator \STs.
     41            feed-backs of the demonstrator \STs.
    4342    \itemV{0}{6}{d}{\Subs}{HAS specification} \setMacroInAuxFile{specHasManualI}
    4443        The first version of the HAS (Hardware Accelerator Synthesis) specification.
    … …  
    4847    \itemL{6}{12}{d}{\Subs}{HAS specification}{1:0:0} \setMacroInAuxFile{specHasManual}
    4948        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
    50         feed-backs of
    51         the demonstrator \STs.
     49            feed-backs of the demonstrator \STs.
    5250    \end{livrable}
    5351\item This \ST specifies the software COACH structure. The deliverable is a
    … …  
    8280        in the {\specXcoachDoc} deliverable and HAS input defined in the {\specHasManual}
    8381        deliverable.
    84     \itemV{7}{12}{x}{\Subs}{C/C++ to/from \xcoach format (2)}
     82    \itemV{7}{12}{x}{\Subs}{C/C++ $\leftrightarrow$ \xcoach format (2)}
    8583        \setMacroInAuxFile{specXcoachToCBI}
    8684        This second tool X2C regenerates a C description from a \xcoach
    8785        description.
    88     \itemL{12}{18}{x}{\Subs}{C++ to/from \xcoach format (2)}{0:0:0}
     86    \itemL{12}{18}{x}{\Subs}{C++ $\leftrightarrow$ \xcoach format (2)}{0:0:0}
    8987        \setMacroInAuxFile{specXcoachToCB}
    9088        The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined
    … …  
    104102    \itemL{18}{24}{x}{\Subs}{\xcoachplus format to VHDL}{0:0:0}
    105103        \setMacroInAuxFile{specXcoachToVhdl}
    106         Maintenance work of the former software (\specXcoachToVhdlI).
     104        Maintenance work of the former software (\specXcoachToVhdlI) and integration
     105        of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
     106    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0}
     107        \setMacroInAuxFile{specXilinxOptimization}
     108        This deliverable consists in optimizing the VHDL generated from \xcoachplus format
     109        (deliverable \novers{\specXcoachToVhdl}) to the \xilinx RTL synthesis tools.
     110        \ubs will provide several examples of VHDL source files generated from \xcoachplus,
     111        with explanations about generation process of main data structures used in VHDL sources,
     112        \xilinx will provide back a documentation listing that proposes VHDL generation enhancements.
    107113    \end{livrable}
    108114   

  • anr/task-2.tex

    r112 r113  
    33\let\IRISA\enable
    44\let\TIMA\enable
     5\let\XILINX\enable
    56\end{taskinfo}
    67%
    … …  
    5758    \begin{livrable}
    5859    \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
     60        \setMacroInAuxFile{csgCoachArchTempl}
    5961        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
     62    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
     63       This deliverable consists in optimizing the VHDL descriptions of the components of
     64       the COACH architectural template (deliverable \novers{\csgCoachArchTempl}) to the
     65       \xilinx RTL synthesis tools.
     66       \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
     67       listing that proposes VHDL generation enhancements.
    6068    \itemV{6}{18}{x}{\Stima}{XILINX architecture}
    6169        \setMacroInAuxFile{csgXilinxSystemC}
    … …  
    6674        The synthesizable VHDL description of the MWMR component corresponding to the
    6775        SystemC module of the former delivrable (\csgXilinxSystemC).
     76    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:2}
     77       This deliverable consists in optimizing the MWMR VHDL description (deliverable
     78       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
     79       \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
     80       listing that proposes VHDL generation enhancements.
    6881    \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture}
    6982        \setMacroInAuxFile{csgAlteraSystemC}
    … …  
    8497       Final release of the tool that generates the VHDL description of the optimized communication adapter
    8598       and its corresponding SystemC module (\gautCOMMoptimization).
     99    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:2}
     100       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
     101       \novers{\gautCOMMoptimization}).
     102       \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation
     103       listing that proposes VHDL generation enhancements.
    86104    \end{livrable}
    87105\item This \ST consists of the configuration of the SocLib MUTEK and DNA operating

  • anr/task-4.tex

    r112 r113  
    33\let\UPMC\enable
    44\let\TIMA\enable
     5\let\XILINX\enable
    56\end{taskinfo}
    67%
    … …  
    9091        A document describing the set up of the coprocessor frequency calibration.
    9192    \itemV{12}{24}{x}{\Supmc}{frequency calibration}
     93        \setMacroInAuxFile{freqCalibrationVhdl}
    9294        A VHDL description of hardware added to the coprocessor to enable the calibration.
    9395    \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5}
    9496        The frequency calibration software consists of a driver in the FPGA-SoC operating
    9597        system and of a control software on a PC. \mustbecompleted {FIXME :: Pas clair pour le HPC. Comprends pas}
     98    \itemL{24}{27}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (5)}{0:0:1}
     99       This deliverable consists in optimizing the VHDL description provided in
     100       \novers{\freqCalibrationVhdl}.
     101       \upmc will provide the VHDL description, \xilinx will provide back a documentation
     102       listing that proposes VHDL generation enhancements.
    96103    \end{livrable}
    97104\end{workpackage}

  • anr/task-5.tex

    r112 r113  
    55\let\UPMC\leader
    66\let\TIMA\enable
    7 \let\ALTERA\enable
     7\let\XILINX\enable
    88\end{taskinfo}
    99%
    … …  
    7171        \setMacroInAuxFile{hpcPlbBridge}
    7272        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
    73     \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0}
     73    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
    7474        \setMacroInAuxFile{hpcAvalonBridge}
    7575        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
    … …  
    8282It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
    8383    \begin{livrable}
    84     \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
     84    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
    8585        Modification of CSG software to support statically reconfigurable task.
    8686    \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:6:12}
    … …  
    9999        reconfiguration dedicated features (reconfiguration time of regions, variable
    100100        number of coprocessors).
     101    \itemL{24}{36}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx dynamic reconfiguration}{0:0:1}
     102        \xilinx will work with \tima in order to better take into account during
     103        partitioning decisions specific constraints due to partial reconfiguration process.
     104        The delivrable is a document describing the \xilinx specific constraints.
    101105    \end{livrable}
    102 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
    103     with its PCI/X IP. These boards are dedicated to the COACH HPC development.
    104     They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
    105     \begin{livrable}
    106     \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
    107     \end{livrable}
     106%\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
     107%   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
     108%   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
     109%   \begin{livrable}
     110%   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
     111%   \end{livrable}
    108112\end{workpackage}

  • anr/task-7.tex

    r111 r113  
    11\begin{taskinfo}
    22\let\UPMC\leader
    3 \let\ALL\enable
     3\let\XILINX\enable
    44\end{taskinfo}
    55%
    … …  
    6565    \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1}
    6666        The final release of the tutorial.
     67    \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:1}
     68        \xilinx will check that developped tutorial works well with \xilinx tools,
     69        and will propose corrections or enhancements if needed into a document.
    6770    \end{livrable}
    6871\end{workpackage}
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