Changeset 113
- Timestamp:
- Feb 8, 2010, 11:40:38 PM (15 years ago)
- Location:
- anr
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
anr/anr.sty
r75 r113 11 11 \let\specHasManual\relax 12 12 \let\specCsgManual\relax 13 \let\specXilinxOptimization\relax 13 14 14 15 \def\setMacroInAuxFile#1{% … … 18 19 \def\eoa{end-of-args} 19 20 \def\@novers#1-#2\eoa{#1} 20 \def\novers#1{\ expandafter\@novers#1\eoa}21 \def\novers#1{\ifx\relax#1\def\next{{\color{red}FIXME}}\else\def\next{\expandafter\@novers#1\eoa}\fi\next} 21 22 22 23 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -
anr/gantt.l
r75 r113 768 768 int main() 769 769 { 770 int tnplus[10] = { 1, 7, 8, -1 };771 int tnmoins[10] = { 1, 7, 8, -1 };770 int tnplus[10] = { 1, 2, 3, 4, -1 }; 771 int tnmoins[10] = { 1, 2, 3, 4, -1 }; 772 772 773 773 yylex(); … … 784 784 do_partner_table_full(4); do_partner_table_short(4); 785 785 do_partner_table_full(5); do_partner_table_short(5); 786 do_partner_table_full(7); do_partner_table_short(7); 787 do_partner_table_full(8); do_partner_table_short(8); 788 do_partner_table_full(9); do_partner_table_short(9); 789 do_partner_table_full(10); do_partner_table_short(10); 786 790 787 791 return 0; -
anr/section-4.4.tex
r56 r113 17 17 \hspace*{-.6cm}\vspace{-1.5cm} 18 18 \input{gantt1.tex} 19 \caption{\label{gantt1}Gantt diagram of delivrables (task-1 \& task-8)}19 \caption{\label{gantt1}Gantt diagram of delivrables (task-1 to task-4)} 20 20 \end{figure} 21 21 … … 23 23 \hspace*{-.6cm}\vspace{-1.5cm} 24 24 \input{gantt2.tex} 25 \caption{\label{gantt2}Gantt diagram of delivrables (task- 2 to task-7)}25 \caption{\label{gantt2}Gantt diagram of delivrables (task-5 to task-8)} 26 26 \end{figure} 27 27 -
anr/task-1.tex
r112 r113 28 28 \itemL{6}{12}{d}{\Supmc}{COACH specification}{1:0:0} \setMacroInAuxFile{specGenManual} 29 29 The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?} 30 feed-backs of the demonstrator \STs.30 feed-backs of the demonstrator \STs. 31 31 \itemV{0}{6}{d}{\Stima}{CSG specification} \setMacroInAuxFile{specCsgManualI} 32 32 The first version of the CSG (COACH System Generator) specification. … … 39 39 \itemL{6}{12}{d}{\Stima}{CSG specification}{1:0:0} \setMacroInAuxFile{specCsgManual} 40 40 The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?} 41 feed-backs 42 of the demonstrator \STs. 41 feed-backs of the demonstrator \STs. 43 42 \itemV{0}{6}{d}{\Subs}{HAS specification} \setMacroInAuxFile{specHasManualI} 44 43 The first version of the HAS (Hardware Accelerator Synthesis) specification. … … 48 47 \itemL{6}{12}{d}{\Subs}{HAS specification}{1:0:0} \setMacroInAuxFile{specHasManual} 49 48 The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?} 50 feed-backs of 51 the demonstrator \STs. 49 feed-backs of the demonstrator \STs. 52 50 \end{livrable} 53 51 \item This \ST specifies the software COACH structure. The deliverable is a … … 82 80 in the {\specXcoachDoc} deliverable and HAS input defined in the {\specHasManual} 83 81 deliverable. 84 \itemV{7}{12}{x}{\Subs}{C/C++ to/from\xcoach format (2)}82 \itemV{7}{12}{x}{\Subs}{C/C++ $\leftrightarrow$ \xcoach format (2)} 85 83 \setMacroInAuxFile{specXcoachToCBI} 86 84 This second tool X2C regenerates a C description from a \xcoach 87 85 description. 88 \itemL{12}{18}{x}{\Subs}{C++ to/from\xcoach format (2)}{0:0:0}86 \itemL{12}{18}{x}{\Subs}{C++ $\leftrightarrow$ \xcoach format (2)}{0:0:0} 89 87 \setMacroInAuxFile{specXcoachToCB} 90 88 The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined … … 104 102 \itemL{18}{24}{x}{\Subs}{\xcoachplus format to VHDL}{0:0:0} 105 103 \setMacroInAuxFile{specXcoachToVhdl} 106 Maintenance work of the former software (\specXcoachToVhdlI). 104 Maintenance work of the former software (\specXcoachToVhdlI) and integration 105 of enhancements proposed in \novers{\specXilinxOptimization} deliverable. 106 \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0} 107 \setMacroInAuxFile{specXilinxOptimization} 108 This deliverable consists in optimizing the VHDL generated from \xcoachplus format 109 (deliverable \novers{\specXcoachToVhdl}) to the \xilinx RTL synthesis tools. 110 \ubs will provide several examples of VHDL source files generated from \xcoachplus, 111 with explanations about generation process of main data structures used in VHDL sources, 112 \xilinx will provide back a documentation listing that proposes VHDL generation enhancements. 107 113 \end{livrable} 108 114 -
anr/task-2.tex
r112 r113 3 3 \let\IRISA\enable 4 4 \let\TIMA\enable 5 \let\XILINX\enable 5 6 \end{taskinfo} 6 7 % … … 57 58 \begin{livrable} 58 59 \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0} 60 \setMacroInAuxFile{csgCoachArchTempl} 59 61 The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. 62 \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0} 63 This deliverable consists in optimizing the VHDL descriptions of the components of 64 the COACH architectural template (deliverable \novers{\csgCoachArchTempl}) to the 65 \xilinx RTL synthesis tools. 66 \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation 67 listing that proposes VHDL generation enhancements. 60 68 \itemV{6}{18}{x}{\Stima}{XILINX architecture} 61 69 \setMacroInAuxFile{csgXilinxSystemC} … … 66 74 The synthesizable VHDL description of the MWMR component corresponding to the 67 75 SystemC module of the former delivrable (\csgXilinxSystemC). 76 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:2} 77 This deliverable consists in optimizing the MWMR VHDL description (deliverable 78 \novers{\csgXilinxSystemC}) of the \xilinx architectural template. 79 \tima will provide MWMR VHDL description, \xilinx will provide back a documentation 80 listing that proposes VHDL generation enhancements. 68 81 \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture} 69 82 \setMacroInAuxFile{csgAlteraSystemC} … … 84 97 Final release of the tool that generates the VHDL description of the optimized communication adapter 85 98 and its corresponding SystemC module (\gautCOMMoptimization). 99 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:2} 100 This deliverable consists in optimizing the communication adapter VHDL description (deliverable 101 \novers{\gautCOMMoptimization}). 102 \ubs will provide communication adapter VHDL description, \xilinx will provide back a documentation 103 listing that proposes VHDL generation enhancements. 86 104 \end{livrable} 87 105 \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating -
anr/task-4.tex
r112 r113 3 3 \let\UPMC\enable 4 4 \let\TIMA\enable 5 \let\XILINX\enable 5 6 \end{taskinfo} 6 7 % … … 90 91 A document describing the set up of the coprocessor frequency calibration. 91 92 \itemV{12}{24}{x}{\Supmc}{frequency calibration} 93 \setMacroInAuxFile{freqCalibrationVhdl} 92 94 A VHDL description of hardware added to the coprocessor to enable the calibration. 93 95 \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5} 94 96 The frequency calibration software consists of a driver in the FPGA-SoC operating 95 97 system and of a control software on a PC. \mustbecompleted {FIXME :: Pas clair pour le HPC. Comprends pas} 98 \itemL{24}{27}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (5)}{0:0:1} 99 This deliverable consists in optimizing the VHDL description provided in 100 \novers{\freqCalibrationVhdl}. 101 \upmc will provide the VHDL description, \xilinx will provide back a documentation 102 listing that proposes VHDL generation enhancements. 96 103 \end{livrable} 97 104 \end{workpackage} -
anr/task-5.tex
r112 r113 5 5 \let\UPMC\leader 6 6 \let\TIMA\enable 7 \let\ ALTERA\enable7 \let\XILINX\enable 8 8 \end{taskinfo} 9 9 % … … 71 71 \setMacroInAuxFile{hpcPlbBridge} 72 72 The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. 73 \itemL{9}{18}{h}{\S altera}{HPC hardware \altera}{0:0:0}73 \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} 74 74 \setMacroInAuxFile{hpcAvalonBridge} 75 75 The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. … … 82 82 It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. 83 83 \begin{livrable} 84 \itemL{ 18}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}84 \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2} 85 85 Modification of CSG software to support statically reconfigurable task. 86 86 \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:6:12} … … 99 99 reconfiguration dedicated features (reconfiguration time of regions, variable 100 100 number of coprocessors). 101 \itemL{24}{36}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx dynamic reconfiguration}{0:0:1} 102 \xilinx will work with \tima in order to better take into account during 103 partitioning decisions specific constraints due to partial reconfiguration process. 104 The delivrable is a document describing the \xilinx specific constraints. 101 105 \end{livrable} 102 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board103 104 105 106 107 106 %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board 107 % with its PCI/X IP. These boards are dedicated to the COACH HPC development. 108 % They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. 109 % \begin{livrable} 110 % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. 111 % \end{livrable} 108 112 \end{workpackage} -
anr/task-7.tex
r111 r113 1 1 \begin{taskinfo} 2 2 \let\UPMC\leader 3 \let\ ALL\enable3 \let\XILINX\enable 4 4 \end{taskinfo} 5 5 % … … 65 65 \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1} 66 66 The final release of the tutorial. 67 \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:1} 68 \xilinx will check that developped tutorial works well with \xilinx tools, 69 and will propose corrections or enhancements if needed into a document. 67 70 \end{livrable} 68 71 \end{workpackage}
Note: See TracChangeset
for help on using the changeset viewer.