Changeset 123 for anr/task-5.tex


Ignore:
Timestamp:
Feb 10, 2010, 1:59:01 AM (14 years ago)
Author:
coach
Message:

IA: 1) enter thales + zied 2) m.a.p

File:
1 edited

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  • anr/task-5.tex

    r113 r123  
    3333\mustbecompleted { FIXME :: Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???}
    3434\begin{workpackage}
    35 \item This \ST is the definition of the communication schemes as a software API
     35\subtask This \ST is the definition of the communication schemes as a software API
    3636    (Application Programing Interface) between the application part running on the PC and
    3737    the application part running on the FPGA-SoC.
     
    4141        Specification describing the API.
    4242    \end{livrable}
    43 \item This \ST consists in helping to partition applications.
     43\subtask This \ST consists in helping to partition applications.
    4444    It is a library implementing the communication API with features to profile
    4545    the partitioned application.
     
    5151        A library implementing the communication API defined in the {\hpcCommApi} delivrable.
    5252    \end{livrable}
    53 \item This \ST deals with the implementation of the communication API on the both sides (PC
     53\subtask This \ST deals with the implementation of the communication API on the both sides (PC
    5454    part and FPGA-SoC).
    5555    \begin{livrable}
     
    6565        Maintenance work of HPC API for both Linux PC and MUTEK OS.
    6666    \end{livrable}
    67 \item This \ST deals with the implementation of hardware and SystemC modules
     67\subtask This \ST deals with the implementation of hardware and SystemC modules
    6868    required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
    6969    \begin{livrable}
     
    7979    \end{livrable}
    8080
    81 \item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
     81\subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
    8282It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
    8383    \begin{livrable}
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