Changeset 114 for anr/task-3.tex

Timestamp:

Feb 9, 2010, 1:35:05 AM (14 years ago)

Author:

coach

Message:

IA: updated data from bull and navtel

File:

• anr/task-3.tex (modified) (4 diffs)

anr/task-3.tex

@@ -25 +25 @@
 
     \begin{livrable}
-      \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow}{0:0:0}
+      \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow}
         In this first version of the software, the computations patterns corresponding to
         custom instruction are specified by the user, and then automatically extracted (when
@@ -41 +41 @@
  of the architecture, along with its architectural extensions 
     \begin{livrable}
-      \itemV{0}{12}{X}{\Sirisa}{SystemC for extensible MIPS }{1:.5:.5} 
+      \itemV{0}{12}{X}{\Sirisa}{SystemC for extensible MIPS }
       { A SystemC simulation model for an simple extensible MIPS architectural template }
       \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{0:0:0}
@@ -49 +49 @@
           { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
           already available from Altera}
-      \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS}{1:.5:.5}
+      \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for an simple extensible MIPS architectural template}
       \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{0:0:0}
       {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemV{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:0}
+      \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:0}
       {A evaluation report with quantitative analysis of the performance/area trade-off induced by
       the different approaches}
@@ -78 +78 @@
       Extension of automatic parallelization and array contraction
       to non-polyhedral loops. Implementation in the Bee framework.
-    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction} {0:0:0}
+    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction}{0:0:0}
       Final release taking into account the feedbacks from the 
       demonstrator \STs.