Changeset 121 for anr/task-3.tex

Timestamp:

Feb 9, 2010, 5:08:49 PM (14 years ago)

Author:

coach

Message:

FC: mise à jour partie moyens INRIA/CAIRN

File:

• anr/task-3.tex (modified) (2 diffs)

anr/task-3.tex

@@ -27 +27 @@
       \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow}
         In this first version of the software, the computations patterns corresponding to
-        custom instruction are specified by the user, and then automatically extracted (when
+        custom instructions are specified by the user, and then automatically extracted (when
         beneficial) from the application intermediate representation. 
         %\mustbecompleted{FIXME .....}
-      \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{0:0:0}
+      \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{6:9:0}
         In this second version, the software will also be able to automatically identify 
         interesting pattern candidates in the application code, and use them as custom 
@@ -37 +37 @@
  
  \item In this sub-task, we provide micro-architectural template models for the two target
- processor architectures (NIOS-II and MIPS) supported within in the COACH-ASIP design flow. 
+ processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. 
  For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) 
  of the architecture, along with its architectural extensions 
     \begin{livrable}
       \itemV{0}{12}{X}{\Sirisa}{SystemC for extensible MIPS }
-      { A SystemC simulation model for an simple extensible MIPS architectural template }
-      \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{0:0:0}
-      {A SystemC simulation model for a extensible MIPS with a tight architectural integration of
+      { A SystemC simulation model for a simple extensible MIPS architectural template }
+      \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{2:3:0}
+      {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{0:0:0}
+      \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
           { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
           already available from Altera}
       \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS}
-      {A synthesizable VHDL model for an simple extensible MIPS architectural template}
-      \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{0:0:0}
-      {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of
+      {A synthesizable VHDL model for a simple extensible MIPS architectural template}
+      \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{9:12:0}
+      {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:0}
-      {A evaluation report with quantitative analysis of the performance/area trade-off induced by
+      \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:2}
+      {An evaluation report with quantitative analysis of the performance/area trade-off induced by
       the different approaches}
     \end{livrable}