Changeset 119


Ignore:
Timestamp:
Feb 9, 2010, 1:02:52 PM (15 years ago)
Author:
coach
Message:

Paul: Minor language modifications.

Location:
anr
Files:
5 edited

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  • anr/section-4.1.tex

    r105 r119  
    2020For the system generation presented in figure~\ref{archi-csg}, the conductor
    2121is the tool \verb!CSG! (COACH System Generator). Its inputs are a process
    22 network describing the application to design and the synthesis parameters.
     22network describing the target application and the synthesis parameters.
    2323The main parameters are the target hardware architectural template
    24 with its instanciation parameters, the hardware/software mapping of the
     24with its instantiation parameters, the hardware/software mapping of the
    2525tasks, the FPGA device and design constraints.
    26 \verb+CSG+ thus requires an architectural template library, a operating system
     26\verb+CSG+ thus requires an architectural template library, an operating system
    2727library, two system hardware component (CPU, memories, BUS...) libraries
    2828(one for synthesis, one for simulation).

  • anr/section-5.tex

    r80 r119  
    22
    33The Coach project will bring new scientific results in various fields, such as high level synthesis,
    4 hardware/software codesign, virtual prototyping, harware oriented compilation technics,
     4hardware/software codesign, virtual prototyping, harware oriented compilation techniques,
    55automatic parallelisation, etc. These results will be presented in the relevant International
    66Conferences, namely DATE, DAC, or ICCAD.
    … …  
    2929tools under the same GPL license as the SoCLib tools. 
    3030\item
    31 The SystemC simulation modelsafor the hardware components
     31The SystemC simulation models for the hardware components
    3232used by the SoCLib architectural template will be distributed as free software
    3333under a non-contaminant LGPL license.
    … …  
    5959
    6060A global consortium agreement will be defined during the first six monts of the project.
    61 As already stated, the Coach project has been prepared during one tear by a monthly meeting
     61As already stated, the Coach project has been prepared during one year by a monthly meeting
    6262involving the five academic partners. The general free software policy described in the
    6363previous section has been agreed by academic partners  and has been

  • anr/section-6.1.tex

    r99 r119  
    33
    44The CAIRN group is an INRIA - Bretagne Atlantique project and a part of IRISA, UMR
    5 6074. CAIRN members are affiliated from University of Rennes\~1 or Ecole Normale
    6 Supérieure de Cachan. the goal of CAIRN is to study reconfigurable system-on-chip,
     56074. CAIRN members are affiliated to University of Rennes\~1 or Ecole Normale
     6Supérieure de Cachan. The goal of CAIRN is to study reconfigurable system-on-chip,
    77i.e. hardware systems whose configuration may change before or even during execution.
    8 To this end, CAIRN intends to approach reconfigurable architectures from three angles:
     8To this end, CAIRN intends to approach reconfigurable architectures from three
     9directions: % angles:
    910the invention of new reconfigurable platforms, the development of associated
    1011transformation, compilation and synthesis tools, and the exploration of the interaction
    … …  
    3637Systems-on-Chip together with their basic operating system on the other end.
    3738
    38 Currently, the lab contains 124 persons among whom 60 PhD candidates, and runs
     39Currently, the lab employs 124 persons among which 60 PhD candidates, and runs
    394032 ongoing French/European funded projects.
    40 Since its creation in 1984, TIMA funded 7 start ups, patented 36 inventions
     41Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions
    4142and had 243 PhD thesis defended.
    4243
    … …  
    5152The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information,
    5253de la Communication, et de la Connaissance), is a French CNRS laboratory
    53 (UMR 3192) that gathers 4 research centers in the west and south
    54 Brittany; from the Universitï¿œ de Bretagne-Sud (UBS), the Universitï¿œ de
     54(UMR 3192) that groups 4 research centers in the west and south
     55Brittany: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de
    5556Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB).
    5657\\
    … …  
    5859Digital communications, Architectures and circuits (CACS) and Knowledge,
    5960information and decision (CID). The Lab-STICC represents a staff of 279
    60 people, including 115 researchers and 113 PhD students.
     61peoples, including 115 researchers and 113 PhD students.
    6162The scientific production during the last 4 years represents 20
    6263books, 200 journal publications, 500 conference publications, 22
    … …  
    121122
    122123\xilinx is the world leader in the domain of programmable logic circuits (FPGA).
    123 \xilinx develops in one hand several FPGA architectures (CoolRunner, Spartan and Virtex
     124\xilinx develops on one hand several FPGA architectures (CoolRunner, Spartan and Virtex
    124125families) and in the other hand a software solution allowing exploiting the
    125126characteristics of these FPGA.
    126127\parlf
    127 The tools proposed can allow the designer to describe his architecture from modeling
     128The tools proposed allow the designer to describe his architecture from a modeling
    128129language (VHDL/Verilog) to an optimized architecture implemented to the selected
    129130technology.
    … …  
    135136  \item RTL model optimizations.
    136137  \item Inference and generation of optimized macro blocks (Finite states machine, counter).
    137   \item Boolean equations generation for randomly logic.
     138  \item Boolean equations generation for random logic.
    138139  \item Logical, mapping and timing optimizations.
    139140\end{itemize}
    … …  
    141142The architectures developed by \xilinx offer a collection of technological primitives
    142143(variable complexity) from simple Boolean generators (LUT) to complex DSP blocks or memory
    143 and whether configurable processor cores (Pico and MicroBlaze families).
    144 This kind of architecture allows, thus, the designer to validate different
     144and even configurable processor cores (Pico and MicroBlaze families).
     145This kind of architecture allows, therefore, the designer to validate different
    145146hardware/software possibilities in a High Level Synthesis (HLS) framework.
    146147\parlf

  • anr/section-6.2.tex

    r62 r119  
    1 The Coach project will be coordinated by the Professor Alain Greiner from
     1The Coach project will be coordinated by professor Alain Greiner from
    22Université Pierre et Marie Curie.
    33Alain Greiner is the initiator and the main architect of the SoCLib project.
    … …  
    66(5 of them are involved in the Coach project).
    77The SoCLib project was managed by Thales, but the technical coordination has been done
    8 by Alain Greiner, that has a good experience in coordinating large technical projects
     8by Alain Greiner, who has a good experience in coordinating large technical projects
    99in both industrial and academic contexts:
    1010

  • anr/section-7.tex

    r114 r119  
    5656\item [Personnel costs]
    5757The permanent personnels involved in the project are professor and
    58 assistant processor (Fr\'ed\'eric P\'etrot and Olivier Muller).
     58assistant professors (Fr\'ed\'eric P\'etrot and Olivier Muller).
    5959All non permanent personnel are Phd students.
    6060Related costs are estimated in men per months.
    6161One phd student (Adrien Prost-Boucle), funded by french ministry of research,
    62 will work working on the project.
     62will be working on the project.
    6363One 100\% funded phd student will be hired in september 2010. A second phd student
    6464will be hired in september 2011, but with half-funding on the project.
    6565The first PhD student will mainly work on the evolution of UGH HLS tool. Thus, we
    66 are looking for profil with strong informatic skills and good knowledge in
     66are looking for a profile with strong informatic skills and good knowledge in
    6767computer architecture.
    6868The second student will mainly work on dynamic reconfiguration and HPC. The required
    … …  
    9999\item [Personnel costs]
    100100The faculty members involved in the project are
    101 associate professors (Philippe COUSSY, Cyrille CHAVET) or research ingeneers (Dominique HELLER).
     101associate professors (Philippe COUSSY, Cyrille CHAVET) or research engineers (Dominique HELLER).
    102102All non-permanent personnel costs are estimated in men*months
    103103for senior researchers (post-doc or research engineers).
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