Changeset 134 for anr/section-2.1.tex

Timestamp:

Feb 13, 2010, 3:24:29 PM (14 years ago)

Author:

coach

Message:

IA: fixed mutek, altera, xilinx, and neutal architectural template

File:

• anr/section-2.1.tex (modified) (3 diffs)

anr/section-2.1.tex

@@ -38 +38 @@
 choice for low-to-medium volume applications. 
 Since their introduction in the mid eighties, FPGAs evolved from a simple, 
-low-capacity gate array to devices (\altera STRATIX III, Xilinx Virtex V) that
+low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that
 provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, 
 on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
@@ -74 +74 @@
 software library that reflect the hardware configuration.
 %% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
-%% IA: ces lignes ont ete verifiees et corrigée pa altera. De plus C2H est plutot limite.
+%% IA: ces lignes ont ete verifiees et corrigée pa \altera. De plus C2H est plutot limite.
 Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
 simulate the platform at a high design level (systemC). 
@@ -96 +96 @@
 \begin{enumerate}
   \item a virtual prototyping environment such as SoCLib for system level exploration,
-  \item an architecture compiler (such as SOPC Builder from \altera, or System generator from Xilinx)
-        to define the hardware architecture,
+  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
+  from \xilinx) to define the hardware architecture,
   \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for 
         coprocessor synthesis,