Changeset 99 for anr/section-2.1.tex


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Timestamp:
Feb 8, 2010, 12:11:05 AM (14 years ago)
Author:
coach
Message:

IA: 1) mise en page et verification de 2, 2.1, 2.2 4.1. 2) entrer bull/xilinx/navtel dans 6.1 3) xilinx dans 7.

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  • anr/section-2.1.tex

    r97 r99  
     1\begin{table}\leavevmode\center
     2\begin{small}\begin{tabular}{|l|l|l|l|}\hline
     3Segment                 & 2010   & 2011    & 2012 \\\hline\hline
     4Communications          & 1,867  & 1,946   & 2,096 \\
     5High end                & 467    & 511     & 550 \\\hline
     6Consumer                & 550    & 592     & 672 \\
     7High end                & 53     & 62      & 75 \\\hline
     8Automotive              & 243    & 286     & 358 \\
     9High end                & -      & -       & - \\\hline
     10Industrial              & 1,102  & 1,228   & 1,406 \\
     11High end                & 177    & 188     & 207 \\\hline
     12Military/Aereo          & 566    & 636     & 717 \\
     13High end                & 56     & 65      & 82 \\\hline\hline
     14Total FPGA/PLD          & 4,659  & 5,015   & 5,583 \\
     15Total High-End  FPGA    & 753    & 826     & 914 \\\hline
     16\end{tabular}\end{small}
     17\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
     18\end{table}
     19%
    120Microelectronic components allow the integration of complicated functions into products, increases
    221commercial attractivity of these products and improves their competitivity.
    322Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
    423thanks to the developpment of design methodologies and tools for embedded systems.
    5 \par
    624Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing
    725and manufacturing ASICs is very high.
    … …  
    1129Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium
    1230volume markets.
    13 \par
     31\parlf
    1432Today, FPGAs become important actors in the computational domain that was originally dominated
    1533by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
    … …  
    2038choice for low-to-medium volume applications.
    2139Since their introduction in the mid eighties, FPGAs evolved from a simple,
    22 low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that
     40low-capacity gate array to devices (\altera STRATIX III, Xilinx Virtex V) that
    2341provide a mix of coarse-grained data path units, memory blocks, microprocessor cores,
    2442on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
    2543complex systems like multi-processors platform with application dedicated coprocessors.
    2644Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
    27 various application domains.
     45various application domains. The ``high end'' lines concern only FPGA with high logic
     46capacity for complex system implementations.
    2847This market is in significant expansion and is estimated to 914\,M\$ in 2012.
    29 
    30 \begin{table}\leavevmode\center
    31 \begin{tabular}{|l|l|l|l|}\hline
    32 Segment         & 2010  & 2011  & 2012 \\\hline\hline
    33 Communications  & 1,867 & 1,946 & 2,096 \\
    34 High end        & 467   & 511   & 550 \\\hline
    35 Consumer        & 550   & 592   & 672 \\
    36 High end        & 53    & 62    & 75 \\\hline
    37 Automotive      & 243   & 286   & 358 \\
    38 High end        & -     & -     & - \\\hline
    39 Industrial      & 1,102 & 1,228 & 1,406 \\
    40 High end        & 177   & 188   & 207 \\\hline
    41 Military/Aereo  & 566   & 636   & 717 \\
    42 High end        & 56    & 65    & 82 \\\hline\hline
    43 Total FPGA/PLD  & 4,659 & 5,015 & 5,583 \\
    44 Total High-End  FPGA    & 753   & 826   & 914 \\\hline
    45 \end{tabular}
    46 \caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
    47 \end{table}
    48 \par
    49 
    50 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions
    51 is limited by the lack of design flow automation. Nowadays, there are neither commercial
    52 nor academic  tools covering the whole design process from the system level specification to the bit stream
    53 generation.
    54 %For instance, with SOPC Builder from Altera, users can select and parameterize IP components
    55 %from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor
    56 %and bus interface cores, as well as incorporate their own IP. Designers can then generate
    57 %a synthesized netlist, simulation test bench and custom software library that reflect the hardware
    58 %configuration.
    59 %Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
    60 (%Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
    61 %simulate the platform at a high design level (systemC).
    62 %In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
    63 %tool to implement designs on Altera devices (Stratix, Arria, Cyclone).
    64 %PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description.
    65 %Nevertheless, they can only deal with data dominated applications and they do not handle the platform level.
    66 %The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to
    67 %Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs.
    68 %Designers can design and simulate a system using MATLAB and Simulink. The tool will then
    69 %automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx
    70 %pre-optimized algorithms.
    71 %However, this tool targets only DSP based algorithms.
    72 
    73 Consequently, a designer developping an embedded system needs to master
    74 four different design environment : a virtual prototyping environment such as SoCLib for system level exploration,
    75 an architecture compiler (such as SOPC Builder from Altera, or System generator from Xilinx) to define the
    76 hardware architecture, one or several HLS tools (such as PICO [CITATION] ou CATAPULT [CITATION]) for
    77 coprocessor synthesis, and finally a backend synthesis tool (such as Quartus or YYYY) for the bit-stream generation.
    78 
     48The HPC market size is estimated today by FPGA providers at 214\,M\$.
     49Using FPGA limits the NRE costs to the design cost.
     50This boosts the developpment of automatic design tools and methodologies.
     51%
     52%Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
     53%Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
     54%for very high performance (HPC) primes over other requirements. They tend to use the highest
     55%performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
     56%architectures and algorithms. These companies show up in different "traditional" applications and market
     57%segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
     58%emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
     59%at 214\,M\$.
     60%%%
     61\parlf
     62This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
     63of FPGA-based solutions is limited by the lack of design flow automation.
     64Nowadays, there are neither commercial nor academic tools covering the whole design process
     65from the system level specification to the bit stream generation.
     66\\
     67% IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
     68%              au dessous n'a pas de sens.
     69% Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
     70For instance, with SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
     71parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
     72processor,  bus core, ...) as well as incorporate their own IP.
     73Designers can then generate a synthesized netlist, simulation test bench and custom
     74software library that reflect the hardware configuration.
     75%% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
     76%% IA: ces lignes ont ete verifiees et corrigée pa altera. De plus C2H est plutot limite.
     77Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
     78simulate the platform at a high design level (systemC).
     79In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
     80tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
     81\\
     82For instance, PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
     83coprocessors from a C++ description.
     84Nevertheless, they can only deal with data dominated applications and they do not handle
     85the platform level.
     86\\
     87Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
     88Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
     89Designers can design and simulate a system using MATLAB and Simulink. The tool will then
     90automatically generate synthesizable Hardware Description Language (HDL) code mapped to
     91\xilinx pre-optimized macro-cells.
     92However, this tool targets only DSP based algorithms.
     93\\
     94Consequently, a designer developping an embedded system needs to master four different
     95design environments:
     96\begin{enumerate}
     97  \item a virtual prototyping environment such as SoCLib for system level exploration,
     98  \item an architecture compiler (such as SOPC Builder from \altera, or System generator from Xilinx)
     99        to define the hardware architecture,
     100  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
     101        coprocessor synthesis,
     102  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
     103\end{enumerate}
     104Furthermore, mixing these tools requires an important interfacing effort and this makes
     105the design process very complex and achievable only by designers skilled in many domains.
     106\begin{center}\begin{minipage}{.8\linewidth}\textit{
    79107The aim of the COACH project is to integrate all these design steps into a single design framework.
    80108and to allow \textbf{pure software} developpers to develop embedded systems.
    81 \par
    82 We believe that the combination of a design environment dedicated to software developpers and the FPGA target,
     109}\end{minipage}\end{center}
     110\parlf
     111We believe that the combination of a design environment dedicated to software developpers
     112and the FPGA target,
    83113allows small and even very small companies to propose embedded system and accelerating solutions
    84114for standard software applications with acceptable prices.
    85 
    86115This new market may explode in the same way as the micro-computer market in the eighties,
    87116whose success was due to the low cost of the first micro-processors (compared to main frames)
    88117and the advent of high level programming languages which allowed a high number of programmers
    89118to launch start-ups in software engineering.
    90 
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