Changeset 134 for anr/task-2.tex
- Timestamp:
- Feb 13, 2010, 3:24:29 PM (14 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
anr/task-2.tex
r126 r134 24 24 to allow the demonstrators to start working. 25 25 This release will include the standard communication schemes (base on SocLib MWMR component) 26 and support the COACHarchitectural template for prototyping and hardware generation.26 and support the neutral architectural template for prototyping and hardware generation. 27 27 \end{objectif} 28 28 % 29 29 \begin{workpackage} 30 \subtask This \ST corresponds to the C oachSystem Generator (CSG) software.30 \subtask This \ST corresponds to the COACH System Generator (CSG) software. 31 31 \begin{livrable} 32 32 \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch} 33 The first software release of the CSG tool that will allow demonstrators to start working by using the COACH34 hardware architecturetemplate.33 The first software release of the CSG tool that will allow demonstrators to start 34 working by using the neutral architectural template. 35 35 \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} 36 The second release of CSG supports the XILINX and ALTERAarchitectural36 The second release of CSG supports the \xilinx and \altera architectural 37 37 templates and the enhanced communication system, but only for SystemC prototyping. 38 38 This release integrates a first integration of HLS tools. 39 39 \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} 40 40 This milestone extends CSG (\csgPrototypingOnly) to 41 FPGA-SoC generation for the XILINX and ALTERAarchitectural template.41 FPGA-SoC generation for the \xilinx and \altera architectural template. 42 42 \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6} 43 43 Final release of CSG. … … 45 45 \subtask This \ST deals with the components of the architectural templates. 46 46 \\ 47 For the COACHarchitectural template, it consists of the development of the VHDL47 For the neutral architectural template, it consists of the development of the VHDL 48 48 synthesizable description of the missing communication components (MWMR) 49 49 in order to support the process network communication model. … … 52 52 ANR project. 53 53 \\ 54 For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERAIPs (NIOS, Microblaze, memories, busses...).54 For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...). 55 55 \begin{livrable} 56 \itemL{0}{12}{h}{\Supmc}{ COACHarchitecture}{1:0:0}56 \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0} 57 57 \setMacroInAuxFile{csgCoachArchTempl} 58 58 The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. 59 59 \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0} 60 60 This deliverable consists in optimizing the VHDL descriptions of the components of 61 the COACHarchitectural template (deliverable \novers{\csgCoachArchTempl}) to the61 the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the 62 62 \xilinx RTL synthesis tools. 63 63 \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation 64 64 listing that proposes VHDL generation enhancements. 65 \itemV{6}{18}{x}{\Stima}{ XILINXarchitecture}65 \itemV{6}{18}{x}{\Stima}{\xilinx architecture} 66 66 \setMacroInAuxFile{csgXilinxSystemC} 67 67 The SystemC simulation module of the MWMR component with a PLB bus interface plus 68 the SystemC modules of the components of the XILINXarchitectural template68 the SystemC modules of the components of the \xilinx architectural template 69 69 currently not available in the SocLib component library. 70 \itemL{18}{24}{h}{\Stima}{ XILINXarchitecture}{9:9:0}70 \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0} 71 71 The synthesizable VHDL description of the MWMR component corresponding to the 72 72 SystemC module of the former delivrable (\csgXilinxSystemC). … … 76 76 \tima will provide MWMR VHDL description, \xilinx will provide back a documentation 77 77 listing that proposes VHDL generation enhancements. 78 \itemV{6}{18}{x}{\Sirisa}{ ALTERAarchitecture}78 \itemV{6}{18}{x}{\Sirisa}{\altera architecture} 79 79 \setMacroInAuxFile{csgAlteraSystemC} 80 80 The SystemC simulation module of the MWMR component with an AVALON bus interface plus 81 the SystemC modules of the components of the ALTERAarchitectural template81 the SystemC modules of the components of the \altera architectural template 82 82 currently not available in the SocLib component library. 83 \itemL{18}{24}{h}{\Sirisa}{ ALTERAarchitecture}{6:6:0}83 \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0} 84 84 The synthesizable VHDL description of the MWMR component corresponding to the 85 85 SystemC module of the former delivrable (\csgAlteraSystemC); … … 100 100 listing that proposes VHDL generation enhancements. 101 101 \end{livrable} 102 \subtask This \ST consists of the configuration of the SocLib MUTEK and DNA operating102 \subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating 103 103 system and the development of drivers for the hardware architectural templates 104 104 and enhanced communication schemes defined in \novers{\specCsgManual} delivrable. 105 For the ALTERA and XILINXarchitectural templates, the OSs must also be ported on105 For the \altera and \xilinx architectural templates, the OSs must also be ported on 106 106 the NIOS2 and MICROBLAZE processors. 107 107 \begin{livrable} 108 \itemV{6}{8}{x}{\Supmc}{MUTEK OS}108 \itemV{6}{8}{x}{\Supmc}{MUTEKH OS} 109 109 The drivers required for the first CSG milestone (delivrable \csgCoachArch). 110 \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}110 \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S} 111 111 The drivers required for the second CSG milestone ({\csgPrototypingOnly}). 112 \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2}112 \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2} 113 113 Maintenance work. 114 \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0}115 Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors.114 \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0} 115 Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors. 116 116 \itemV{6}{8}{x}{\Stima}{DNA OS} 117 117 The drivers required for the first CSG milestone (delivrable \csgCoachArch).
Note: See TracChangeset
for help on using the changeset viewer.