Changeset 247 for anr


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Timestamp:
Feb 17, 2010, 2:27:40 PM (15 years ago)
Author:
coach
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UBS

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anr
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  • anr/section-2.1.tex

    r237 r247  
    4646capacity for complex system implementations.
    4747This market is in significant expansion and is estimated to 914\,M\$ in 2012.
    48 The HPC market size is estimated today by FPGA providers at 214\,M\$.
    49 Using FPGA limits the NRE costs to the design cost.
    50 This boosts the developpment of automatic design tools and methodologies.
     48%The HPC market size is estimated today by FPGA providers at 214\,M\$.
     49%Using FPGA limits the NRE costs to the design cost.
     50%This boosts the developpment of automatic design tools and methodologies.
    5151%
    52 %Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
    53 %Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
    54 %for very high performance (HPC) primes over other requirements. They tend to use the highest
    55 %performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
    56 %architectures and algorithms. These companies show up in different "traditional" applications and market
    57 %segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
    58 %emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
    59 %at 214\,M\$.
    60 %%%
    6152\parlf
     53Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
     54Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
     55for very high performance (HPC) primes over other requirements. They tend to use the highest
     56performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
     57architectures and algorithms. These companies show up in different "traditional" applications and market
     58segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
     59emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
     60at 214\,M\$.
    6261This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
    6362of FPGA-based solutions is limited by the lack of design automation.
     63\\
    6464Nowadays, there are neither commercial nor academic tools covering the whole design process
    65 from the system level specification to the bit stream generation.
    66 % IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
    67 %              au dessous n'a pas de sens.
    68 % Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
    69 By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
    70 parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
    71 processor,  bus core, ...) as well as incorporate their own IP.
    72 Designers can then generate a synthesized netlist, simulation test bench and custom
    73 software library that reflect the hardware configuration.
    74 %% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
    75 %% IA: ces lignes ont ete verifiees et corrigée pa \altera. De plus C2H est plutot limite.
    76 Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
    77 simulate the platform at a high design level (systemC).
    78 In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
    79 tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
    80 PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
    81 coprocessors from a C++ description.
    82 Nevertheless, they can only deal with data dominated applications and they do not handle
    83 the platform level.
    84 Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
    85 Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
    86 Designers can design and simulate a system using MATLAB and Simulink. The tool will then
    87 automatically generate synthesizable Hardware Description Language (HDL) code mapped to
    88 \xilinx pre-optimized macro-cells.
    89 However, this tool targets only DSP based algorithms.
    90 \\
    91 Consequently, a designer developping an embedded system needs to master four different
    92 design environments:
    93 \begin{enumerate}
    94   \item a virtual prototyping environment such as SoCLib for system level exploration,
    95   \item an architecture compiler (such as SOPC Builder from \altera, or System generator
    96   from \xilinx) to define the hardware architecture,
    97   \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
    98         coprocessor synthesis,
    99   \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
    100 \end{enumerate}
    101 Furthermore, mixing these tools requires an important interfacing effort and this makes
    102 the design process very complex and achievable only by designers skilled in many domains.
     65from the system level specification to the bit stream generation neither for embedded system design
     66nor for HPC.
     67
     68%PC => IA et Alain
     69%Le paragraphe ci dessous n'a rien a faire dans la partie Economic et societal issue
     70%Je le mets donc en commentaire
     71
     72%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
     73%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
     74%processor,  bus core, ...) as well as incorporate their own IP.
     75%Designers can then generate a synthesized netlist, simulation test bench and custom
     76%software library that reflect the hardware configuration.
     77%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
     78%simulate the platform at a high design level (systemC).
     79%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
     80%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
     81%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
     82%coprocessors from a C++ description.
     83%Nevertheless, they can only deal with data dominated applications and they do not handle
     84%the platform level.
     85%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
     86%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
     87%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
     88%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
     89%\xilinx pre-optimized macro-cells.
     90%However, this tool targets only DSP based algorithms.
     91%\\
     92%Consequently, a designer developping an embedded system needs to master four different
     93%design environments:
     94%\begin{enumerate}
     95%  \item a virtual prototyping environment such as SoCLib for system level exploration,
     96%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
     97%  from \xilinx) to define the hardware architecture,
     98%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
     99%        coprocessor synthesis,
     100%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
     101%\end{enumerate}
     102%Furthermore, mixing these tools requires an important interfacing effort and this makes
     103%the design process very complex and achievable only by designers skilled in many domains.
     104
    103105\begin{center}\begin{minipage}{.8\linewidth}\textit{
    104106The aim of the COACH project is to integrate all these design steps into a single design framework
    105107and to allow \textbf{pure software} developpers to develop embedded systems.
    106108}\end{minipage}\end{center}
     109
     110%PC => IA et Alain
     111% le paragraphe suivant est coupé collé de la section suivante 2.2
     112
     113
    107114\parlf
     115The COACH project proposes an open-source framework for mapping multi-tasks software applications
     116on Field Programmable Gate Array circuits (FPGA).
     117It aims to propose solutions to the societal/economical challenges by
     118providing SMEs novel design capabilities enabling them to increase their
     119design productivity with design exploration and synthesis methods that are placed on top
     120of the state-of-the-art methods.
    108121We believe that the combination of a design environment dedicated to software developpers
    109122and FPGA targets,

  • anr/section-2.2.tex

    r241 r247  
    11% Relevance of the proposal
    2 The COACH proposal addresses directly the \emph{Embedded Systems} item of
    3 the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
    4 providing SMEs novel design capabilities enabling them to increase their
    5 design productivity with design exploration and synthesis methods that are placed on top
    6 of the state-of-the-art methods.
    7 This project proposes an open-source framework for mapping multi-tasks software applications
    8 on Field Programmable Gate Array circuits (FPGA).
     2%The COACH proposal addresses directly the \emph{Embedded Systems} item of
     3%the ARPEGE program.
     4
     5%PC => IA et ALain
     6%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1
     7
     8%It aims to propose solutions to the societal/economical challenges by
     9%providing SMEs novel design capabilities enabling them to increase their
     10%design productivity with design exploration and synthesis methods that are placed on top
     11%of the state-of-the-art methods.
     12%This project proposes an open-source framework for mapping multi-tasks software applications
     13%on Field Programmable Gate Array circuits (FPGA).
    914%%%
    1015\parlf
    … …  
    5661    silicon density and power efficiency, able to adapt its computing
    5762    structure to computation patterns that can be speed-up and/or
    58     power efficient.  The ROMA project study a pipeline of
    59     evolved low-power coarse grain reconfigurable operators to avoid
    60     traditional overhead, in reconfigurable devices, related to the
    61     interconnection network.  The project will borrow from the ROMA
     63    power efficient.  %The ROMA project study a pipeline of
     64    %evolved low-power coarse grain reconfigurable operators to avoid
     65    %traditional overhead, in reconfigurable devices, related to the
     66    %interconnection network. 
     67        The project will borrow from the ROMA
    6268    ANR project and the ongoing joint INRIA-STMicro
    6369    Nano2012 project to adapt existing pattern extraction algorithms
    … …  
    9096  \item
    9197    Regarding system level architecture, the project is based on the know-how
    92     acquired by the \upmc and \tima laboratories in the framework of various projects 
     98    acquired by \upmc and \tima in the framework of various projects 
    9399    in the field of communication architectures for shared memory multi-processors systems
    94100    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
    … …  
    109115    parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb},
    110116    process construction \cite{Feau:96} and memory management \cite{bee}
    111     will be very useful as a front-end for the a high-level synthesis tools.
     117    will be very useful as a front-end for HLS tools.
    112118\end{itemize}
    113119%%%
    … …  
    120126Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
    121127constraints and objectives (real-time, low-power). It will permit designing  complex SoC
    122 based on IP cores (memory, peripherals, network controllers, communication processors),
     128based on IP cores (memory, peripherals...),
    123129running Embedded Software, as well as an Operating System with associated middleware and
    124130API and using hardware accelerator automatically generated. It will also permit to use

  • anr/section-3.1.tex

    r237 r247  
    7979In addition, \xilinx System Generator and SOPC Builder are closed world
    8080since each one imposes their own IPs which are not interchangeable.
     81%By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
     82%parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
     83%processor,  bus core, ...) as well as incorporate their own IP.
     84%Designers can then generate a synthesized netlist, simulation test bench and custom
     85%software library that reflect the hardware configuration.
     86%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
     87%simulate the platform at a high design level (systemC).
     88%In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
     89%tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
     90%PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
     91%coprocessors from a C++ description.
     92%Nevertheless, they can only deal with data dominated applications and they do not handle
     93%the platform level.
     94%Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
     95%Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
     96%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
     97%automatically generate synthesizable Hardware Description Language (HDL) code mapped to
     98%\xilinx pre-optimized macro-cells.
     99%However, this tool targets only DSP based algorithms.
     100%\\
     101%Consequently, a designer developping an embedded system needs to master four different
     102%design environments:
     103%\begin{enumerate}
     104%  \item a virtual prototyping environment such as SoCLib for system level exploration,
     105%  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
     106%  from \xilinx) to define the hardware architecture,
     107%  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
     108%        coprocessor synthesis,
     109%  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
     110%\end{enumerate}
     111%Furthermore, mixing these tools requires an important interfacing effort and this makes
     112%the design process very complex and achievable only by designers skilled in many domains.
    81113
    82114\subsubsection{High Level Synthesis}
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