Changeset 275 for anr/section-3.2.tex

Timestamp:

Nov 22, 2010, 10:17:21 PM (14 years ago)

Author:

coach

Message:

Introduced IP-XACT in the coach.

File:

• anr/section-3.2.tex (modified) (2 diffs)

anr/section-3.2.tex

@@ -1 +1 @@
 % les objectifs scientifiques/techniques du projet.
 The design steps are presented figure~\ref{coach-flow}.
+\ADDED{
+The end-user input is
+either a HPC application (an application running on a PC that must be accelarate),
+or an embedded application (a standalone application),
+or a function of a larger design.}
 \begin{figure}[hbtp]\leavevmode\center
   \includegraphics[width=.8\linewidth]{flow}
@@ -13 +18 @@
 COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels.
 The user input will consist of a process network describing the coarse grain parallelism
-of the application, an instance of a generic hardware platform
-and a mapping of processes on the platform components. 
+of the application, an instance of an architectural template
+and a mapping of processes on the architectural template components. 
 COACH will offer different targets to map the processes:  
 software (the process runs as a software task on a SoC processor),
 ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
 and hardware (the process is implemented as a synthesized hardware coprocessor).
-\item[Application compilation:] Once the SoC architecture is validated through performances 
-analysis, COACH will generate automatically an executable containing the host application and
+\item[Application compilation:]
+\begin{SUPPRESSEDENV}
+Once the SoC architecture is validated through performances analysis,
+COACH will generate automatically an executable containing the host application and
 the FPGA bitstream. This bitstream contains 
 both the hardware architecture and the SoC application software.
 The user will be able to launch the application by
 loading the bitstream on an FPGA and running the executable on PC.
+\end{SUPPRESSEDENV}\begin{ADDEDENV}
+Once the SoC architecture is validated through performances analysis,
+COACH generates its bitstream in the case of HPC or embedded application,
+or its IP-XACT description for its integration in the case of a function.
+Both descriptions contain the hardware architecture and the application software.
+Furthermore in the HPC case, an executable containing the host application is
+also generated and the user will be able to launch the application by loading
+the bitstream on an FPGA and running the executable on PC.
+\end{ADDEDENV}
 \end{description}