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Changeset 275
- Timestamp:
- Nov 22, 2010, 10:17:21 PM (14 years ago)
- Location:
- anr
- Files:
-
- 4 edited
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architecture-csg.fig (modified) (4 diffs)
-
flow.fig (modified) (2 diffs)
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section-3.2.tex (modified) (2 diffs)
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section-4.1.tex (modified) (2 diffs)
Legend:
- Unmodified
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- Removed
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anr/architecture-csg.fig
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anr/flow.fig
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5 173 9600 5775 7650 5775 7650 3900 9600 3900 9600 5775 174 2 1 1 2 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 175 7650 5325 9600 5325 183 12855 1960 10650 1960 10650 1275 12855 1275 12855 1960 176 184 4 0 0 50 -1 2 16 0.0000 4 195 1305 11100 1650 Executable\001 177 4 0 0 50 -1 2 16 0.0000 4 255 1065 11250 6750 Running\001178 185 4 0 0 50 -1 2 16 0.0000 4 255 690 2250 675 Input\001 179 186 4 0 0 50 -1 2 16 0.0000 4 255 1290 4800 675 HPC setup\001 180 187 4 0 0 50 -1 2 16 0.0000 4 255 1305 8025 675 SoC design\001 181 4 0 0 50 -1 2 12 0.0000 4 150 240 8475 5100 T0\001 182 4 0 0 50 -1 2 12 0.0000 4 150 240 8025 4275 T1\001 183 4 0 0 50 -1 2 12 0.0000 4 150 240 9000 4275 T2\001 184 4 0 0 50 -1 2 16 0.0000 4 195 1905 7725 5625 Process network\001 185 4 0 0 50 -1 2 16 0.0000 4 255 2535 4200 6750 Performance analysis\001 186 4 0 0 50 -1 2 16 0.0000 4 255 2535 7350 6750 Performance analysis\001 188 4 0 0 50 -1 2 16 0.0000 4 255 2535 7350 6300 Performance analysis\001 189 4 0 0 50 -1 2 16 0.0000 4 255 2535 4275 6300 Performance analysis\001 190 4 0 0 50 -1 2 16 0.0000 4 255 2805 10350 6300 Running or Integration\001 -
anr/section-3.2.tex
r272 r275 1 1 % les objectifs scientifiques/techniques du projet. 2 2 The design steps are presented figure~\ref{coach-flow}. 3 \ADDED{ 4 The end-user input is 5 either a HPC application (an application running on a PC that must be accelarate), 6 or an embedded application (a standalone application), 7 or a function of a larger design.} 3 8 \begin{figure}[hbtp]\leavevmode\center 4 9 \includegraphics[width=.8\linewidth]{flow} … … 13 18 COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels. 14 19 The user input will consist of a process network describing the coarse grain parallelism 15 of the application, an instance of a generic hardware platform16 and a mapping of processes on the platformcomponents.20 of the application, an instance of an architectural template 21 and a mapping of processes on the architectural template components. 17 22 COACH will offer different targets to map the processes: 18 23 software (the process runs as a software task on a SoC processor), 19 24 ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), 20 25 and hardware (the process is implemented as a synthesized hardware coprocessor). 21 \item[Application compilation:] Once the SoC architecture is validated through performances 22 analysis, COACH will generate automatically an executable containing the host application and 26 \item[Application compilation:] 27 \begin{SUPPRESSEDENV} 28 Once the SoC architecture is validated through performances analysis, 29 COACH will generate automatically an executable containing the host application and 23 30 the FPGA bitstream. This bitstream contains 24 31 both the hardware architecture and the SoC application software. 25 32 The user will be able to launch the application by 26 33 loading the bitstream on an FPGA and running the executable on PC. 34 \end{SUPPRESSEDENV}\begin{ADDEDENV} 35 Once the SoC architecture is validated through performances analysis, 36 COACH generates its bitstream in the case of HPC or embedded application, 37 or its IP-XACT description for its integration in the case of a function. 38 Both descriptions contain the hardware architecture and the application software. 39 Furthermore in the HPC case, an executable containing the host application is 40 also generated and the user will be able to launch the application by loading 41 the bitstream on an FPGA and running the executable on PC. 42 \end{ADDEDENV} 27 43 \end{description} 28 44 -
anr/section-4.1.tex
r255 r275 11 11 \caption{\label{archi-hpc} Software architecture of HPC} 12 12 \end{figure} 13 %FIXME: la figure ne montre que l'aspect simulation. Intégrer la partie génération (PC API, PCIX, FPGA-IP, bridge vers VCI, SoC API) serait un plus, non ?14 13 % 15 14 Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} … … 30 29 controls the HAS tools described below. 31 30 From these inputs \verb!CSG! can generate the entire system (both software and 32 hardware) either as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the 31 hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger 32 design or} 33 as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the 33 34 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and 34 35 launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the 35 36 FPGA device\footnote{Additional partial bitstreams are generated in case of 36 37 dynamic partial reconfiguration}. 38 \begin{ADDEDENV} 39 \\ 40 Furthermore the architecture template and hardware component libraries will be described 41 under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other 42 architecture or the enhancement of existing template with IP. 43 \end{ADDEDENV}% 37 44 \parlf 38 45 The software architecture for HAS is presented in figure~\ref{archi-hls}.
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