Changeset 275 for anr/section-4.1.tex

Timestamp:

Nov 22, 2010, 10:17:21 PM (14 years ago)

Author:

coach

Message:

Introduced IP-XACT in the coach.

File:

• anr/section-4.1.tex (modified) (2 diffs)

anr/section-4.1.tex

@@ -11 +11 @@
 \caption{\label{archi-hpc} Software architecture of HPC}
 \end{figure}
-%FIXME: la figure ne montre que l'aspect simulation. Intégrer la partie génération (PC API, PCIX, FPGA-IP, bridge vers VCI, SoC API) serait un plus, non ?
 %
 Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc}
@@ -30 +29 @@
 controls the HAS tools described below.
 From these inputs \verb!CSG! can generate the entire system (both software and
-hardware) either as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
+hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger
+design or}
+as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
 launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the
 FPGA device\footnote{Additional partial bitstreams are generated in case of
  dynamic partial reconfiguration}.
+ \begin{ADDEDENV}
+ \\
+ Furthermore the architecture template and hardware component libraries will be described
+ under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other
+ architecture or the enhancement of existing template with IP.
+ \end{ADDEDENV}%
 \parlf
 The software architecture for HAS is presented in figure~\ref{archi-hls}.