Changeset 283 for anr


Ignore:
Timestamp:
Nov 30, 2010, 6:14:47 PM (14 years ago)
Author:
coach
Message:

Suppressed reference to Flexras and Navtel.

Location:
anr
Files:
3 edited

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  • anr/anr.tex

    r278 r283  
    5959\def\ubs{LAB-STICC\xspace}        \def\Subs{\Sformat{UBS}\xspace}
    6060\def\upmc{LIP6\xspace}            \def\Supmc{\Sformat{LIP6}\xspace}
     61\def\bull{BULL\xspace}            \def\Sbull{\Sformat{BULL}\xspace}
     62\def\thales{THALES\xspace}        \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales
     63\def\mds{MAGILLEM DESIGN SERVICES\xspace} \def\Smds{\Sformat{MDS}\xspace}
     64
    6165\def\altera{ALTERA\xspace}        \def\Saltera{\Sformat{ALTE}\xspace}
    6266\def\xilinx{XILINX\xspace}        \def\Sxilinx{\Sformat{XILX}\xspace}
    63 \def\bull{BULL\xspace}            \def\Sbull{\Sformat{BULL}\xspace}
    64 \def\thales{THALES\xspace}        \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales
    65 \def\zied{FLEXRAS\xspace}         \def\Szied{\Sformat{FLEX}\xspace}
    66 \def\navtel{NAVTEL-SYSTEM\xspace} \def\Snavtel{\Sformat{NAV}\xspace}
    67 \def\mds{MAGILLEM DESIGN SERVICES\xspace} \def\Smds{\Sformat{MDS}\xspace}
    6867
    6968\def\alllabs{\irisa \citi \lip \tima \ubs \upmc}
    70 \def\allcompagnies{\bull \thales \zied\xspace}
     69\def\allcompagnies{\bull \thales \mds\xspace}
    7170
    7271%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    … …  
    270269    \Sirisa for \irisa, \Slip for \lip, \Stima for \tima, \Subs for \ubs,
    271270    \Supmc for \upmc, \Sxilinx for \xilinx, \Sbull for \bull, \Sthales for \thales,
    272     \Szied for \zied and \Snavtel for \navtel.
     271    and \Smds for \mds.
    273272  \item[kind of the deliverable]
    274273    \texttt{x} for a software, \texttt{d} for a document and \texttt{h} for a hardware

  • anr/section-5.tex

    r268 r283  
    4343optimised cache controllers, peripheral controllers, or bus controllers.
    4444For non commercial use (i.e. research or education in an academic context, 
    45 or feasbility study in an industrial context), the synthesizable VHDL models will be freely available.
    46 For commercial use, commercial licenses will be negociated between the owners and the customers.
     45or feasibility study in an industrial context), the synthesizable VHDL models will be freely available.
     46For commercial use, commercial licenses will be negotiated between the owners and the customers.
    4747\item
    48 The proprietary \altera, \xilinx and \zied IP core libraries are commercial products
     48The proprietary \altera and \xilinx IP core libraries are commercial products
    4949that are not involved by the free software policy, but these libraries will be supported by the
    50 synthesis tools developped in the COACH project.
     50synthesis tools developed in the COACH project.
    5151\end{itemize}
    5252
    … …  
    5757\subsection{Indusrial Interest in COACH}
    5858
     59\subsubsection*{Partner: \textit{\mds}}
     60
     61\mustbecompleted{Emanuel ....}
     62
    5963\subsubsection*{Partner: \textit{\bull}}
    6064The team of \bull participating to the COACH project is from the Server Development
    … …  
    6367FPGA parallelism) to add to existing Bull HPC solutions.
    6468
    65 \subsubsection*{Partner: \textit{\xilinx}}
    66 Computing power potential of our FPGA architectures
    67 growing very quickly on one side, and complexity of designs implemented
    68 using our FPGAs dramatically increasing on the other side, it is very
    69 interesting for us to get high level design methodologies progressing
    70 quickly and targetting our FPGAs in the most possible efficient way.
    71 \parlf
    72 \xilinx goal is to get COACH to generate bitstream optimized as much as possible for
    73 \xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
    74 future work of our customers.
     69%\subsubsection*{Partner: \textit{\xilinx}}
     70%Computing power potential of our FPGA architectures
     71%growing very quickly on one side, and complexity of designs implemented
     72%using our FPGAs dramatically increasing on the other side, it is very
     73%interesting for us to get high level design methodologies progressing
     74%quickly and targetting our FPGAs in the most possible efficient way.
     75%\parlf
     76%\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
     77%\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
     78%future work of our customers.
    7579
    7680\subsubsection*{Partner: \textit{\thales}}
    … …  
    107111border monitoring.
    108112
    109 \subsubsection*{Partner: \textit{\zied}}
     113\subsubsection*{Industrial supports}
    110114
    111 \zied is developing a new architecture for embedded system. Our interest in using COACH
    112 are:
    113 \begin{itemize}
    114   \item firstly, to validate our new architecture by emulating it with COACH.
    115   \item Secondly, to use this emulator and the COACH potential to quickly setup
    116   demonstrator to our customer.
    117 \end{itemize}
    118 
    119 \subsubsection*{Partner: \textit{\navtel}}
    120 \navtel has a platform for high performence computation based on ARM processor and FPGAs
    121 that embedde coprocessors. Currently, the coprocessors are handmade and their designs
    122 constitute an important part of our product cost. We have try free HLS tools to diminish
    123 them but the quality of the generated designs was not sufficient to be useable.
    124 So our interest in COACH is mainly the HLS tools.
    125 
    126 \subsubsection*{Industrial supports}
     115\mustbecompleted{NON A JOUR}
    127116The following SMEs demonstrate interest to the COACH project (see the "letters of
    128117interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will

  • anr/section-6.1.tex

    r267 r283  
    152152\parlf
    153153Even if the preferred dissemination policy for the COACH design flow will be the free
    154 software policy, (following the SoCLib model), the SoC department is ready to support
    155 start-ups : Six startup companies (including \zied) have been created by former
     154software policy, the SoC department is ready to support start-ups :
     155Six startup companies have been created by former
    156156researchers from  the SoC department of LIP6 between 1997 and 2002.
    157157
    … …  
    189189the fact of the increase of the architecture complexity and due to the use of FPGA
    190190component for low power applications.
     191
     192%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     193\subsubsection{\mds}
     194
     195\mustbecompleted{Emanuel ....}
    191196
    192197%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    … …  
    247252computing embedded systems.
    248253
    249 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    250 \subsubsection{\zied}
    251 
    252 \zied is an innovative start-up specialized in the conception of configurable circuits
    253 and the development of CAD tools. \zied provides a complete front-to-back-end generator
    254 of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs.
    255 \zied solution is based on a patented FPGA architecture delivering an unprecedented
    256 level of logic density. This high capacity is accessible using a traditional RTL flow from
    257 Verilog/VHDL synthesis all the way to bitstream generation.
    258 \parlf
    259 \zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the
    260 French National Competition for Business Startup and Innovative Technology in 2007 and
    261 2009 in "emergence" and "creation" categories respectively.
    262 
    263 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    264 \subsubsection{\navtel}
    265 
    266 \navtel was created in 1994 to develop flexible systems based on FPGAs and currently
    267 focuses on intelligent signal mining for knowlege based signal processing systems.
    268 The company main activity covers the following domains: satellite communication,
    269 aeronautics, imaging and security.
    270 \navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
    271 and imaging systems and 30\% to its own research programmes in collaboration with French
    272 and international partners.
    273 \parlf
    274 The multi disciplinary technical team comprises 6 engineers for signal processing and
    275 hardware development and one technician.
    276 \parlf
    277 \navtel has its own Ph.D program which includes in the past (classification technology
    278 and MIMO for FPGA implementation) and currently the preparation of a project for remote
    279 sensing with signal intelligence for satellite application. The company participates in
    280 national and European level projects contributing to a strategic alliance between academic
    281 and  industrial partners.\\
    282 The current research covers particle filter applications for communication and RADAR,
    283 Cognitive Radio, Satellite communication, embedded super computing and focuses on low
    284 power algorithms for implementation in FPGA and  soft computing.
    285 \parlf
    286 For manufacturing and industrialization, \navtel works with ISO certified partners.
    287 The company clients include the CNES, Thal\`{e}s Alenia Space, Thal\`{e}s Communication, EADS,
    288 Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase up to the
    289 system delivery.
    290 \begin{description}
    291 \item[Recognitions:]\mbox{}
    292 \begin{itemize}
    293   \item HEC Challenge+  program for innovative projects (promotion 9)
    294   \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
    295   \item Recognition by the French Senate for company creation  during the
    296         \og Semaine de l'entrepreneur \fg 2005.
    297 \end{itemize}
    298 \end{description}
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