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Timestamp:
Dec 23, 2010, 11:53:37 AM (14 years ago)
Author:
coach
Message:

MAJ des donnees LIP6 (quasi la derniere)

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  • anr/section-project-task-schedule.tex

    r300 r304  
    1414\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7}
    1515\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4}
    16 \immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24}
     16\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=27}
    1717%\def\ganttlabelstyle#1{\begin{small}#1\end{small}}
    1818\def\ganttlabelstyle#1{\begin{small}\hyperlink{#1}{#1}\end{small}}
    … …  
    4949%The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project.
    5050Before the final release (T0+36), there are 4 milestones (red lines on the figures) at
    51 $T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent
     51$T0+6$, $T0+12$, $T0+18$ and $T0+27$ that are rendez-vous points of the precedent
    5252deliverables.
    5353\begin{description}
    54 \item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of
     54  \item[Milestone 1 ($T0+6$)]
     55    Specification of COACH inputs, of the \xcoach format and of
    5556    the demonstatrors as a reference software.
    56 \item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are
    57     written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
     57  \item[Milestone 2 ($T0+12$)]
     58    The first COACH release. At this step the demonstrators are
     59    written in the COACH input format. This COACH release allows to prototype
     60    and to generate the FPGA-SoC.
    5861    The main restrictions are:
    5962    1) Only the neutral architectural template is supported,
    … …  
    6164    3) Enhanced communication schemes are not available.
    6265    4) ASIP compilation flow is not available.
    63 \item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
    64     features are availables. A preliminary version of the ASIP synthesis flow is supported, for a
    65    simple extensible MIPS model. The main restriction is that COACH can not yet
    66    generate FPGA-SoC for \altera and \xilinx architectural templates.
     66  \item[Milestone 3 ($T0+18$)]
     67    The second COACH release. At this step most of the COACH features are available.
     68    A preliminary version of the ASIP synthesis flow is supported, for a
     69    simple extensible MIPS model. The main restriction is that COACH can not yet
     70    generate FPGA-SoC for \altera and \xilinx architectural templates.
    6771    The others restriction is that the HAS tools are not yet fully operational.
    68 \item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
    69     supported.
    70     The main restriction are:
    71     1) The backend HAS tools have not been yet enhanced,
    72     2) Dynamic partial reconfiguration is not supported,
    73     3) NIOS processor instruction set extension is supported, but only for user specified patterns.
     72\item[Milestone 4 ($T0+27$)]
     73    The pre-release of the COACH project. The full design flow is supported.
     74    The main restrictions are:
     75    1) Automatic frequency calibration of coprocessor is not available.
     76    2) Automatic HPC set up is not yet available.
     77    3) NIOS processor instruction set extension is supported, but only for user
     78    specified patterns.
     79    4) GAUT enhencements are not available.
    7480\item[Final Release ($T0+36$)]
    75        
     81
    7682\end{description}
    77 This organisation allows the project to globally progress step by step mixing development
    78 and demonstrator deliverables.
    79 Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
    80 at the integration phase is significantly reduced.
     83This organisation allows the project to globally progress step by step mixing
     84development and demonstrator deliverables.
     85Hence, demonstrator feed-back will arrive early and so the risk to point out
     86incompatibility at the integration phase is significantly reduced.
    8187\par
    8288The risks that have been identified at the beginning of the project are the following:
    8389\begin{description}
    84 \item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})]
    85         Partners have to agree on a convenient exchange format for all tools involved.
    86         Because all the HAS tools rely on it, the \xcoach format specification is a
    87     crucial step. There are no work-around but as mentionned in
    88     section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it
    89         for a full year and a preliminary document already exists.
     90  \item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})]
     91    Partners have to agree on a convenient exchange format for all tools involved.
     92    Because all the HAS tools rely on it, the \xcoach format specification is a
     93    crucial step.
     94    There are no work-around but as mentionned in section~\ref{xcoach-problem}
     95    (page~\pageref{xcoach-problem}) the five academic partners have worked on it
     96    for a full year and a preliminary document already exists.
    9097%\item[\xcoachplus format (\novers{\specXcoachDoc},
    9198%      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
    … …  
    93100%    By centralizing the coprocessor generation, it guarantees their functioning
    94101%    independently of the used HAS tools.
    95 %       Our experience with UGH and GAUT give us confidence in the succes of this
    96 %       task.
    97 \item[Virtual prototyping of \altera \& \xilinx architectural templates ({\NOVERScsgImplementation})]
    98      The SoCLib component library contains several SystemC models used for the virtual
    99      prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).
    100      Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
    101      If the workload of this simulation model development is too important, virtual prototyping
    102          of those architectural templates will not be directly supported.
    103          The three architectural templates being quite similar, the virtual
    104          prototyping will use the neutral architectural template.
    105 \item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
    106      If one of these tasks is impossible or too important or leads to inefficiency,
    107      it will be abandoned.
    108      In this case, the neutral architectural template will not be available for HPC and
    109      a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
    110      virtual prototyping.
     102%   Our experience with UGH and GAUT give us confidence in the succes of this
     103%   task.
     104  \item[Virtual prototyping  ({\NOVERScsgImplementation})]
     105    In this project, only the virtual prototyping of the neutral architectural
     106    template is supported.
     107    We think that this restriction is not a serious problem.
     108    Indeed the \altera \& \xilinx architectural templates being architecturally close of
     109    the neutral architectural template, an efficient software/hardware partition
     110    on the neutral architectural template is also an efficient on the other
     111    architectural templates.
     112    The project will allow to verify experimentally this assumption.
     113%  \item[Virtual prototyping of \altera \& \xilinx architectural templates
     114%    ({\NOVERScsgImplementation})]
     115%    The SoCLib component library contains several SystemC models used for the
     116%    virtual prototyping of the \altera and \xilinx architectural templates
     117%    (NIOS and Microblaze processor cores).
     118%    Nevertheless, at this time we do not know how many IP cores SystemC
     119%    simulation models have to be developped.
     120%    If the workload of this simulation model development is too important,
     121%    virtual prototyping of those architectural templates will not be directly
     122%    supported.
     123%    The three architectural templates being quite similar, the virtual
     124%    prototyping will use the neutral architectural template.
     125  \item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
     126    These bridges may decrease the efficiency of the \altera \& \xilinx
     127    architectural templates.
     128    Developing the communication components (MWMR) for the AVALON and PLB buses
     129    will correct this problem.
     130%    If one of these tasks is impossible or too important or leads to inefficiency,
     131%    it will be abandoned.
     132%    In this case, the neutral architectural template will not be available for HPC and
     133%    a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
     134%    virtual prototyping.
    111135\end{description}
    112136\parlf
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