Changeset 311 for anr

Timestamp:

Jan 16, 2011, 10:37:52 AM (13 years ago)

Author:

coach

Message:

Changed microblaze/plb in \xilinxcpu/\xilinxbus that extend arm/AMBA

Location:

anr

Files:

• annexe-reponse.tex (modified) (2 diffs)
• anr.tex (modified) (1 diff)
• section-1.tex (modified) (1 diff)
• section-2.tex (modified) (1 diff)
• section-project-task-schedule.tex (modified) (2 diffs)
• task-csg.tex (modified) (3 diffs)

anr/annexe-reponse.tex

@@ -240 +240 @@
     composant de communication (MWMR) pour les patrons architecturaux XILINX et ALTERA.
     Ces choix conduisaient à 4 implantations du composants de communication
-    (MWMR) (1 VHDL MWMR/PLB, 1 VHDL MWMR/AVALON, 1 SystemC MWMR/PLB et
+    (MWMR) (1 VHDL MWMR/\xilinxbus, 1 VHDL MWMR/AVALON, 1 SystemC
+    MWMR/\xilinxbus et
     1 SystemC MWMR/AVALON) et probablement à quelques autres modules SystemC.\\
     \textit{Nous avons Îté ces développements}.
     En effet pour l'implantation matériel des patrons architecturaux, on
-    utilisera les ponts VCI/PLB et VCI/AVALON qui sont nécessaires au HPC et
+    utilisera les ponts VCI/\xilinxbus et VCI/AVALON qui sont nécessaires au HPC et
     pour le prototypage, on se limitera au patron architectural neutre.
 \end{itemize}
@@ -277 +278 @@
 \t\note{SL4}
 Enfin une réserve concerne l'utilisation du bus VCI jugé obsolÚte via les composants
-SoCLib. Le projet prévoit le développement de pont VCI/AVALON et VCI/PLB ce qui
+SoCLib. Le projet prévoit le développement de pont VCI/AVALON et VCI/\xilinxbus ce qui
 permettra l'utilisation des IP de XILINX et ALTERA dans la patron architectural
 neutre.

anr/anr.tex

@@ -53 +53 @@
 \def\Backbone{Backbone infrastructure\xspace}
 \def\hommemois{men*months\xspace}
+\def\xilinxcpu{ARM\xspace}
+\def\xilinxbus{AMBA\xspace}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

anr/section-1.tex

@@ -80 +80 @@
     \item An \altera architectural template based on the \altera IP core library, the
       AVALON system bus and the NIOS processor.
-    \item A \xilinx architectural template based on the \xilinx IP core library, the PLB
-      system bus and the Microblaze processor.
+    \item A \xilinx architectural template based on the \xilinx IP core library,
+      the \xilinxbus system bus and the \xilinxcpu processor.
     \end{enumerate}
 \item[Hardware/Software communication middleware:]

anr/section-2.tex

@@ -28 +28 @@
 During this project, the COACH partners will develop three different architectural templates:
 \begin{enumerate}
-\item An \altera architectural template based on the \altera IP core library, the AVALON system bus and the NIOS processor.
-\item A \xilinx architectural template based on the \xilinx IP core library, the PLB system bus and the Microblaze processor.
+\item An \altera architectural template based on the \altera IP core library,
+    the AVALON system bus and the NIOS processor.
+\item A \xilinx architectural template based on the \xilinx IP core library, the
+    \xilinxbus system bus and the \xilinxcpu processor.
 \item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP
-      communication infrastructure.
+    communication infrastructure.
 \end{enumerate}
 %The proposed design flow starts from a high level description of the application, specified as a set of 

anr/section-project-task-schedule.tex

@@ -115 +115 @@
 %    The SoCLib component library contains several SystemC models used for the
 %    virtual prototyping of the \altera and \xilinx architectural templates
-%    (NIOS and Microblaze processor cores).
+%    (NIOS and \xilinxcpu processor cores).
 %    Nevertheless, at this time we do not know how many IP cores SystemC
 %    simulation models have to be developped.
@@ -123 +123 @@
 %    The three architectural templates being quite similar, the virtual
 %    prototyping will use the neutral architectural template.
-  \item[VCI/AVALON \& VCI/PLB bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
+  \item[VCI/AVALON \& VCI/\xilinxbus bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})]
     These bridges may decrease the efficiency of the \altera \& \xilinx
     architectural templates.
-    Developing the communication components (MWMR) for the AVALON and PLB buses
+    Developing the communication components (MWMR) for the AVALON and \xilinxbus buses
     will correct this problem.
 %    If one of these tasks is impossible or too important or leads to inefficiency,

anr/task-csg.tex

@@ -29 +29 @@
     \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:3:3}
         \setMacroInAuxFile{hpcPlbBridge}
-        The synthesizable VHDL description of a PLB/VCI bridge.
+        The synthesizable VHDL description of a VCI/\xilinxbus bridge.
     \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:3:3}
         \setMacroInAuxFile{hpcAvalonBridge}
-        The synthesizable VHDL description of an AVALON/VCI bridge.
+        The synthesizable VHDL description of an VCI/AVALON bridge.
     \end{livrable}
 \subtask{OS setup}
@@ -38 +38 @@
     system and the development of drivers for the hardware architectural templates.
     For the \altera and \xilinx architectural templates, the OS must also be ported on
-    the NIOS2 and MICROBLAZE processors.
+    the NIOS2 and \xilinxcpu processors.
     \begin{livrable}
     \itemV{6}{8}{x}{\Stima}{DNA OS}
@@ -51 +51 @@
     \itemL{12}{18}{x}{\Stima}{Driver ports}{0:2:0}
         \OtherPartner{6}{33}{\Supmc}  {0:2:0}
-    \mustbecompleted{TIMA: tima sur Microblaze, UPMC sur Nios}
-        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
+    \mustbecompleted{TIMA: tima sur \xilinxcpu, UPMC sur Nios}
+        Porting of DNA OS on the NIOS2 and \xilinxcpu processors.
     \end{livrable}
 \subtask{Implementation of CSG}