Changeset 312 for anr


Ignore:
Timestamp:
Jan 17, 2011, 8:07:37 PM (14 years ago)
Author:
coach
Message:

Update EV+IA

Location:
anr
Files:
5 edited

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  • anr/anr.bib

    r304 r312  
     1%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     2%%%%% MDS
     3@inproceedings{mds:2008,
     4 author = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin, Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe, de Paoli Serge and Vaumorin Emmanuel},
     5 title = {Industrial IP integration flows based on IP-XACT standards},
     6 booktitle = {Proceedings of the conference on Design, automation and test in Europe},
     7 series = {DATE '08},
     8 year = {2008},
     9 isbn = {978-3-9810801-3-1},
     10 location = {Munich, Germany},
     11 pages = {32--37},
     12 numpages = {6},
     13 url = {http://doi.acm.org/10.1145/1403375.1403386},
     14 doi = {http://doi.acm.org/10.1145/1403375.1403386},
     15 acmid = {1403386},
     16 publisher = {ACM},
     17 address = {New York, NY, USA},
     18}
     19
     20@report{rapportministere,
     21 author = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy},
     22 title = {Briques g\'en\'eriques du logiciel embarqu\'e},
     23 year = {2010},
     24 publisher = {Mininist\'ere de l'industrie},
     25}
     26
    127%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    228%%%%% LIP6
  • anr/section-consortium-people.tex

    r309 r312  
    3333
    3434\peopletabularentry{\mds}           
    35 coordinator & Vaumorin    & Emannuel    & Strategic Project Manager & ESL   & ... & Project leader \\\hline
    36 ...         & Spasevski   & Cyril       & CTO                 & EDA         & ... & Technical specifications \\\hline
    37 ...         & Guntz       & St\'ephane  & VP of Engineering   & EDA         & ... & Demonstrator specification and management \\\hline                       ...         & Lucas       & Ronan       &         & EDA         & ... & Tools and demonstrator implementation \\\hline       
     35coordinator & Vaumorin    & Emannuel    & Strategic Project Manager & ESL      & 20 & Project leader \\\hline
     36contributor & Spasevski   & Cyril       & CTO                 & EDA            & 6 & Technical specifications \\\hline
     37contributor & Guntz       & St\'ephane  & VP of Engineering   & EDA            & 12 & Demonstrator specification and management \\\hline
     38contributor & Lucas       & Ronan       & R\&D Engineer       & HW/SW Codesign & 12 & Tools and demonstrator implementation \\\hline
    3839
    3940\peopletabularentry{\irisa}
  • anr/section-issues.tex

    r307 r312  
    77d’application, 
). Indicateurs des gains environnementaux, cycle de vie.}
    88%
    9 \subsubsection*{Predominance of FPGA in the global electronic market}
     9\subsubsection*{The electronic market}
    1010\begin{table}\leavevmode\center
    1111\begin{small}\begin{tabular}{|l|l|l|l|}\hline
     
    2929Microelectronic components allow the integration of complex functions into products, increases
    3030commercial attractivity of these products and improves their competitivity.
    31 Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
     31\cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 minimum.
     32Multimedia and communication sectors have taken advantage from microelectronics facilities
    3233thanks to the developpment of design methodologies and tools for embedded systems.
    3334Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
     
    3536An IC foundry costs several billions of euros and the fabrication of a specific circuit
    3637costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
    37 million USD.
    38 Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
    39 volume markets.
     38million USD.C onsequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
     39volume markets and the new trend for building the new generation products will be multi processors SoCs and programmable logic for co-processsing.
     40\\
     41According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), the global growth is 30 Billons\$ between 2009-2013 for multimedia and communication sectors; this is 6 times more than all other domains like security, home automation, health.
     42The predominance of market of multimedia and communication sectors results in the fact that they are mainly mass market.
    4043%
    4144\subsubsection*{FPGAs and Embedded Systems}
    42 Today, FPGAs become important actors in the computational domain that was originally dominated
     45Today, FPGAs become important in the computational domain that was originally dominated
    4346by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
    4447on a per-application basis. For many applications, FPGAs offer significant performance benefits over
     
    7477\subsubsection*{Evolution of architectures}
    7578Nowadays processors mixing core and programmable matrix are available on the market (eg. Intel ATOM E600C).
    76 "Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic
     79Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic
    7780products (eg. PDAs and nomad items) and even personal computers.
    7881To take benefit of such architecture, developping and deploying application will require innovative codesign methods and tools.
     
    8285Nowadays, there are no commercial or academic tools covering the whole design flow
    8386from the system level specification to the bitstream generation neither for embedded system design
    84 nor for HPC.
     87nor for HPC. 
    8588\begin{center}\begin{minipage}{.9\linewidth}\textit{
    8689The aim of the COACH project is to integrate all these design steps into a single design framework
     
    102105and the advent of high level programming languages which allowed a high number of programmers
    103106to launch start-ups in software engineering.
     107\\
     108So this may increase the total amount of engineers working in this domain: today in France the total is only 26,000 in which 16,000 in big companies \cite{rapport-ministere}.
  • anr/task-demonstrator.tex

    r308 r312  
    109109        \NOVERStrtSpearde, \NOVERSmdsAppSpecification)
    110110        using the COACH milestone of T0+18.
    111       \itemV{27}{30}{d+x}{\Smds}{Evaluation}
    112         Same as former but for the milestone of T0+27.
    113       \itemL{30}{36}{d+x}{\Smds}{Evaluation}{0:5:5}
     111      \itemL{27}{36}{d+x}{\Smds}{Evaluation}{0:3:3}
    114112        \OtherPartner{18}{36}{Sbull}{0:4:5}
    115         \OtherPartner{18}{36}{Sthales}{0:5:5}
     113        \OtherPartner{18}{36}{Sthales}{0:4:5}
    116114        This deliverable is a document that validates and evaluates the COACH final release
    117115        for the demonstrators.
  • anr/task-dissemination.tex

    r308 r312  
    7878  \subtask{Publications and Communications}
    7979   \begin{livrable}
    80    \itemL{12}{36}{d}{\Smds}{Publication, communication}{0:3:3}
     80   \itemL{12}{36}{d}{\Smds}{Publication, communication}{0:2:3}
    8181        \OtherPartner{12}{36}{\Sirisa} {0:1:1}
    8282        \OtherPartner{12}{36}{\Slip}   {0:1:1}
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