Changeset 36 for anr/task-5.tex
- Timestamp:
- Jan 18, 2010, 9:31:49 AM (14 years ago)
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anr/task-5.tex
r35 r36 29 29 the application part running on the FPGA-SoC. 30 30 \begin{livrable} 31 \item{-VF}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API. 31 \item{}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API. 32 \global\edef\hpcCommApi{\name} 32 33 \end{livrable} 33 \item This \ST aims with the application partitioning help. It is a library implementing 34 the communication API with features to profile the application partionning. 34 \item This \ST aims consists in helping the application partitioning help. 35 It is a library implementing the communication API with features to profile 36 the application partionning. 35 37 \begin{livrable} 36 \item{-VF}{0}{12}{x}{\Supmc}{HPC partionning help} A library. 38 \item{}{6}{12}{x}{\Supmc}{HPC partionning helper} A library implementing the communication 39 API defined in the {\hpcCommApi} delivrable. 37 40 \end{livrable} 38 41 \item This \ST aims with the implementation of the communication API on the both sides (PC 39 42 part and FPGA-SoC). 40 43 \begin{livrable} 41 \item{}{0}{21}{x}{\Supmc}{HPC API for Linux PC} 42 \item{}{0}{21}{x}{\Stima}{HPC API for DNA OS} 43 \item{}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} 44 \item{}{12}{21}{x}{\Supmc}{HPC API for Linux PC} The PC part of the HPC communication API 45 that comminicate with the FPGA-SOC, a library and probably a LINUX module. 46 \item{}{12}{21}{x}{\Supmc}{HPC API for MUTEK OS} The FPGA-SoC part of the communication API, a 47 driver.\global\edef\hpcMutekDriver{\name} 48 \item{}{21}{24}{x}{\Stima}{HPC API for DNA OS} Port of the {\hpcMutekDriver} driver on the DNA OS. 44 49 \end{livrable} 45 50 \item This \ST aims with the implementation of hardware required by the COACH 46 51 architectural template for using the PCI/X IP of \altera and \xilinx. 47 52 \begin{livrable} 48 \item{}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description 49 of a PLB/VCI bridge. 50 \item{}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description 51 of a AVALON/VCI bridge. 53 \item{}{9}{18}{h}{\Stima}{HPC hardware \xilinx} 54 \setMacroInAuxFile{hpcPlbBridge} 55 The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. 56 \item{}{9}{18}{h}{\Saltera}{HPC hardware \altera} 57 \setMacroInAuxFile{hpcAvalonBridge} 58 The synthesizable VHDL description of a AVALON/VCI bridge and its corresponding SystemC model. 52 59 \end{livrable} 53 60 \item This \ST aims with the dynamic reconfiguration of FPGA. 54 61 \begin{livrable} 55 \item{}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers} 56 \item{}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers} 57 \item{}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration} 58 \item{}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration} 62 \item{}{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers} 63 \global\edef\hpcDynconfDriver{\name} 64 \mustbecompleted{FIXME:TIMA ....} 65 \item{}{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers} 66 Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS. 67 \item{}{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration} 68 \mustbecompleted{FIXME:TIMA ....} 69 \item{}{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration} 70 \mustbecompleted{FIXME:TIMA ....} 59 71 \end{livrable} 60 72 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board … … 62 74 They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. 63 75 \begin{livrable} 64 \item{}{0}{6}{ x}{\Saltera}{HPC development boards}76 \item{}{0}{6}{m}{\Saltera}{HPC development boards} Two PCI/X FPGA boards. 65 77 \end{livrable} 66 78 \end{workpackage}
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