Changeset 356 for anr/section-2.tex

Timestamp:

Feb 6, 2011, 2:29:09 PM (13 years ago)

Author:

coach

Message:

1ere Pre-release

File:

• anr/section-2.tex (modified) (2 diffs)

anr/section-2.tex

@@ -1 +1 @@
 Embedded systems (SoC and MPSoC) have become an inevitable evolution in the microelectronic industry.
-Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuits) 
-is not an option for SMEs (Small and Medium Enterprises).
+The ASIC technology (Application Specific Integrated Circuits) 
+is not an option for markets with small series of products due to ROI.
 Fortunately, the new FPGA (Field Programmable Gate Array) components,
-such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete
+such as the Virtex6 family from \xilinx, or the Stratix4 family from \altera can implement a complete
 multi-processor architecture on a single device.
 But the design of embedded system is a long and complex task that requires expertise in software,
-software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling.
+software/hardware portioning, operating system, hardware design, VHDL/Verilog modeling.
 Only very few SMEs have these multiple expertises and are present on the embedded system market.
+The corresponding development cost is high and it is not compliant with
+specification or standard evolution (problem of flexibility).
 Furthermore, even small design shops in big companies are facing the same issue.
 \begin{center}\begin{minipage}{.8\linewidth}\textit{
@@ -74 +76 @@
 unadapted to the current GPU based solutions.
 \parlf
-Coach generates SoCs which are part of larger systems. Thus it is important to take
- into account the existing industrial design flow. For this reason COACH will use the 
+COACH generates SoCs which are part of larger systems. Thus it is important to take
+into account the existing industrial design flow. For this reason COACH will use the 
 IP-XACT IEEE 1685 standard for packaging these generated SoCs.
 \begin{center}\begin{minipage}{.8\linewidth}\textit{