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Timestamp:
Feb 15, 2011, 11:20:41 AM (14 years ago)
Author:
coach
Message:

Anglais. Voir deux questions de fond.

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  • anr/section-etat-de-art.tex

    r356 r369  
    1919The High-Performance Computing (HPC) world is composed of three main families of architectures:
    2020many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA.
    21 The first  two families are dominating the market by taking benefit
     21Today, the first  two families are dominating the market by taking benefit
    2222of the strength and influence of mass-market leaders (Intel, Nvidia).
    2323%such as Intel for many-core CPU and Nvidia for GPGPU.
    … …  
    2626FPGAs architectures enable better performance
    2727(typically an acceleration factor between 10 and 100)
    28 while using smaller size and less energy (and heat).
     28while using smaller size and less energy (and generating less heat).
    2929However, using FPGAs presents significant challenges~\cite{hpc06a}.
    3030First, the operating frequency of an FPGA is low compared to a high-end microprocessor.
    31 Second, based on Amdahl law,  HPC/FPGA application performance is unusually sensitive
     31Second, % based on Amdahl law,
     32 HPC/FPGA application performance is unusually sensitive
    3233to the implementation quality~\cite{hpc06b}.
    3334% Thus, the performance strongly relies on the detected parallelism.
    … …  
    4445researches on HPC-FPGA are mainly conducted in the USA.
    4546None of the approaches developed in these researches are fulfilling entirely the
    46 challenges described above. For example, Convey Computer proposes application-specific instruction set extension of x86 cores in an FPGA accelerator,
     47challenges described above. For example, Convey Computer proposes application-specific instruction
     48set extension of x86 cores in an FPGA accelerator,
    4749but extension generation is not automated and requires hardware design skills.
    4850Mitrionics has an elegant solution based on a compute engine specifically
    … …  
    5860appears very interesting for improving HPC performance as well as reducing required area.
    5961
     62%oui, mais il me semble que COACH ne va rien faire à ce sujet. Est-ce la peine de
     63%donner des verges pour nous faire battre? En outre, je ne vois pas bien l'intérêt.
     64%
     65%Paul
     66
    6067\subsubsection{System Synthesis}
    6168\label{soa:system:synthesis}
    6269Today, several solutions for system design are proposed and commercialized.
    6370The existing commercial or free tools do not
    64 cover the whole system synthesis process in a full automatic way. Moreover,
    65 they are bound to a particular device family and to IPs library.
     71cover the whole system synthesis process in a fully automatic way. Moreover,
     72they are bound to a particular device family and to an IP library.
    6673The most commonly used are provided by \altera and \xilinx to promote their
    6774FPGA devices. These representative tools used to synthesize SoC on FPGA
    … …  
    7178plug-in to Simulink that enables designers to develop high-performance DSP
    7279systems for \xilinx FPGAs.
    73 Designers can design and simulate a system using MATLAB and Simulink. The
     80Designers can specify and simulate a system using MATLAB and Simulink. The
    7481tool will then automatically generate synthesizable Hardware Description
    7582Language (HDL) code mapped to \xilinx pre-optimized algorithms.
    76 However, this tool targets onlysignal processing algorithms, \xilinx FPGAs and
     83However, this tool targets only signal processing algorithms, \xilinx FPGAs and
    7784cannot handle a complete SoC. Thus, it is not really a system synthesis tool.
    7885\\
    … …  
    8087Platform Studio XPS from \xilinx allow to describe a system, to synthesize it,
    8188to program it into a target FPGA and to upload a software application.
    82 Both SOPC Builder and XPS, allow designers to select and parameterize components from
     89Both SOPC Builder and XPS allow designers to select and parameterize components from
    8390an extensive drop-down list of IP cores (I/O core, DSP, processor,  bus core, ...)
    84 as well as incorporate their own IP. Nevertheless, all the previously introduced tools
     91as well as to incorporate their own IP. Nevertheless, all the previously introduced tools
    8592do not provide any facilities to synthesize coprocessors and to simulate the platform
    8693at a high level (SystemC).
    87 System designer must provide the synthesizable description of its own IP-cores with
    88 the feasible bus interface. Design Space Exploration is thus limited
    89 and SystemC simulation is not possible neither at transactional nor at cycle
     94A system designer must provide the synthesizable description of its own IP-cores with
     95a feasible bus interface.%
     96%qu'est-ce que c'est qu'un ``feasible bus interface''? a *standard* bus interface? Paul
     97%
     98Design Space Exploration is thus limited
     99and SystemC simulation is not possible either at transactional or at cycle
    90100accurate level.
    91101\\
    … …  
    121131to the HLS input dialect and perform engineering work to exploit the synthesis result
    122132at the system level,
    123 \item Current HLS tools can not target control AND data oriented applications,
     133\item Current HLS tools cannot target control AND data oriented applications,
    124134\item HLS tools take into account mainly a unique constraint while realistic design
    125135is multi-constrained.
    126 Low power consumption constraint which is mandatory for embedded systems is not yet
     136The power consumption constraint which is mandatory for embedded systems is not yet
    127137well handled or not handled at all by the HLS tools already available,
    128 \item The parallelism is extracted from the initial specification.
     138\item The parallelism is limited to that present in the initial specification.
    129139To get more parallelism or to reduce the amount of required memory in the SoC, the user
    130140must re-write the algorithmic specification while there are techniques such as polyhedral
    131 transformations to increase the intrinsic parallelism,
     141transformations that can automate this process.
    132142\item While they support limited loop transformations like loop unrolling and loop
    133143pipelining, current HLS tools do not provide support for design space exploration, either
    134 through automatic loop transformations or through memory mapping,
     144through automatic loop transformations or for improving the memory mapping,
    135145\item Despite having the same input language (C/C++), they are sensitive to the style in
    136146which the algorithm is written. Consequently, engineering work is required to swap from
    … …  
    159169\par
    160170In this context, ASIP design based on Instruction Set Extensions (ISEs) has
    161 received a lot of interest~\cite{NIOS2}, as it makes micro architecture synthesis
     171received a lot of interest~\cite{NIOS2}, as it makes micro-architecture synthesis
    162172more tractable \footnote{ISEs rely on a template micro-architecture in which
    163173only a small fraction of the architecture has to be specialized}, and help ASIP
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