Changeset 356 for anr/section-etat-de-art.tex

Timestamp:

Feb 6, 2011, 2:29:09 PM (14 years ago)

Author:

coach

Message:

1ere Pre-release

File:

• anr/section-etat-de-art.tex (modified) (5 diffs)

anr/section-etat-de-art.tex

@@ -25 +25 @@
 By adapting architecture to the software, % (the opposite is done in the others families)
 FPGAs architectures enable better performance
-(typically between x10 and x100 accelerations)
+(typically an acceleration factor between 10 and 100)
 while using smaller size and less energy (and heat).
 However, using FPGAs presents significant challenges~\cite{hpc06a}.
@@ -128 +128 @@
 \item The parallelism is extracted from the initial specification.
 To get more parallelism or to reduce the amount of required memory in the SoC, the user
-must re-write the algorithmic specification while there are techniques such as polyedric
+must re-write the algorithmic specification while there are techniques such as polyhedral
 transformations to increase the intrinsic parallelism,
 \item While they support limited loop transformations like loop unrolling and loop
@@ -213 +213 @@
 Since hardware is inherently parallel, finding parallelism in sequential
 programs in an important prerequisite for HLS. The large FPGA chips of
-today can accomodate much more parallelism than is available in basic blocks.
+today can accommodate much more parallelism than is available in basic blocks.
 The polyhedral model is the ideal tool for finding more parallelism in
 loops.
@@ -219 +219 @@
 As a side effect, it has been observed that the polyhedral model is a useful
 tool for many other optimization, like memory reduction and locality
-improvement. Itshould be noted 
+improvement. It should be noted 
 that the polyhedral model \emph{stricto sensu} applies only to
 very regular programs. Its extension to more general programs is
@@ -251 +251 @@
 further releases.
 \parlf
-In IP-XACT the flow automation and data constistency is ensured by generators, which 
+In IP-XACT the flow automation and data consistency is ensured by generators, which 
 are program modules that process IP-XACT XML data into something useful 
 for the design. They are key portable mechanism for encapsulating specialist design
 knowledge and enable designers to deploy specialist knowledge in their design. It is
 always possible to create generators in order to link several design or analysis tools
-around a centric representation of metadata in IP-XACT. This kind of XML schema for
-metadata management is a good solution for the federation of heterogeneous design domains
+around a centric representation of meta-data in IP-XACT. This kind of XML schema for
+meta-data management is a good solution for the federation of heterogeneous design domains
 (models, tools, languages, methodologies, etc.).
 
-%\subsubsection{High Performance Computing}
-%Accelerating high-performance computing (HPC) applications with field-programmable
-%gate arrays (FPGAs) can potentially improve performance. 
-%However, using FPGAs presents significant challenges~\cite{hpc06a}.
-%First, the operating frequency of an FPGA is low compared to a high-end microprocessor.
-%Second, based on Amdahl law,  HPC/FPGA application performance is unusually sensitive 
-%to the implementation quality~\cite{hpc06b}.
-%Finally, High-performance computing programmers are a highly sophisticated but scarce 
-%resource. Such programmers are expected to readily use new technology but lack the time 
-%to learn a completely new skill such as logic design~\cite{hpc07a} . 
-%\\
-%HPC/FPGA hardware is only now emerging and in early commercial stages, 
-%but these techniques have not yet caught up. 
-%Thus, much effort is required to develop design tools that translate high level
-%language programs to FPGA configurations.
-