Changeset 56 for anr/task-5.tex

Timestamp:

Feb 1, 2010, 6:07:27 PM (14 years ago)

Author:

coach

Message:

Modifications de TIMA, task-5 et section-3.1 principalement

File:

• anr/task-5.tex (modified) (6 diffs)

anr/task-5.tex

@@ +1 @@
+% vim:set spell:
+% vim:spell spelllang=en:
+
 \begin{taskinfo}
 \let\UPMC\leader
@@ -10 +13 @@
 \begin{itemize}
 \item Helping the HPC designer to find a good partition of the initial application
-    (figure~\ref{archi-hpc}.
-\item Providing communication schemes between the software part runing on the PC and the
+    (figure~\ref{archi-hpc}).
+\item Providing communication schemes between the software part running on the PC and the
 FPGA-SoC.
 \item Implementing the communication scheme at all levels: partition help, software
 implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
-\item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA}
+\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order to optimize FPGA ressource usage.
 \end{itemize}
+
 The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
 transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
@@ -22 +26 @@
 This will allow us at least to be inspired by GPU communication schemes and may be to reuse
 parts of the GPU softwares.
+
+
 \end{objectif}
 %
@@ -31 +37 @@
     \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0}
         \setMacroInAuxFile{hpcCommApi}
-        User refernce manual describing the API.
+        User reference manual describing the API.
     \end{livrable}
-\item This \ST consists in helping to partition the application.
+\item This \ST consists in helping to partition applications.
     It is a library implementing the communication API with features to profile
     the partitioned application.
+%FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application.
+% It is a profiling (or simulation) library implementing the communication API
+
     \begin{livrable}
     \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0}
@@ -52 +61 @@
         Port of the {\hpcMutekDriver} driver on the DNA OS.
     \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
-        Maintenance work of HPC API for both Lunix PC and MUTEK OS.
+        Maintenance work of HPC API for both Linux PC and MUTEK OS.
     \end{livrable}
 \item This \ST deals with the implementation of hardware required by the COACH
@@ -64 +73 @@
         The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
     \end{livrable}
-\item This \ST deals with the dynamic reconfiguration of an FPGA.
+\item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
+It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
+
     \begin{livrable}
+    \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}
+        Extension of the \xilinx architectural template ({\csgAllArch})
+in order to integrate dynamic partial reconfiguration regions.
+Modification of CSG software to support the extended \xilinx template.
     \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:0:0}
         \setMacroInAuxFile{hpcDynconfDriver}
-        \mustbecompleted{FIXME:TIMA ....}
+        The drivers required by the DNA OS in order to manage dynamic partial reconfiguration inside the SoC-FPGA.
     \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
-        Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS.
-    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2}
-        \mustbecompleted{FIXME:TIMA ....}
-    \itemL{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}{0:0:0}
-        \mustbecompleted{FIXME:TIMA ....}
-    \end{livrable}
+        Port of the {\hpcDynconfDriver} drivers on the MUTEK OS.
+    \itemL{18}{36}{x}{\Stima}{HPC support for \ganttlf dynamic reconfiguration}{0:0:2}
+Extension of the HPC partionning helper in order to integrate dynamic partial reconfiguration dedicated features
+(reconfiguration time of regions, variable number of coprocessors)
+\end{livrable}
 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
     with its PCI/X IP. These boards are dedicated to the COACH HPC development.