Changeset 97 for anr


Ignore:
Timestamp:
Feb 5, 2010, 10:16:22 PM (15 years ago)
Author:
alain
Message:

Alain : refonte de la section 2

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anr
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8 edited

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  • anr/anr.tex

    r62 r97  
    111111
    112112% 2.1
    113 \pagefeed\subsection{Context, economic and societal issues}
     113\pagefeed\subsection{Economic and societal issues}
    114114\anrdoc{(2 pages maximum) Décrire le contexte économique, social, réglementaire
    115115dans lequel se situe le projet en présentant une analyse des enjeux sociaux,

  • anr/section-1.tex

    r89 r97  
    22The market of digital systems is about 4,600 M\$ today and is estimated to
    335,600 M\$ in 2012. However the ever growing applications complexity involves
    4 higher integration of heterogeneous technologies and requires the design of
     4integration of heterogeneous technologies and requires the design of
    55complex Multi-Processors System on Chip (MPSoC).
    6 During the last decade, the design of complex digital ASICs (Application Specific
     6\par
     7During the last decade, the design of ASICs (Application Specific
    78Integrated Circuits) appeared to be more and more reserved to high volume markets, because
    89the design and fabrication costs of such components exploded, due to increasing NRE (Non
    910Recurring-Engineering) costs.
    10 \\
    11 FPGA (Field Programmable Gate Array) components, such as the
     11Fortunately, FPGA (Field Programmable Gate Array) components, such as the
    1212Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
    13 implement a complete MPSoC with multiple processors and several
     13implement a complete MPSoC with multiple processors and several dedicated
    1414coprocessors for a few keuros per device.
    1515In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
    … …  
    2020major companies to design innovative devices and to enter new, low and
    2121medium volume markets.
    22 \\
     22\par
    2323The objective of COACH is to provide an integrated design flow, based on the
    2424SoCLib infrastructure~\cite{soclib}, and optimized for the design of
    25 multi-processors digital systems targetting FPGA devices.
     25multi-processors digital systems targeting FPGA devices.
    2626Such digital systems are generally integrated
    2727into one or several chips, and there are two types of applications:
    28 It can be embedded (autonomous) applications
    29 such as personal digital assistants (PDA), ambiant computing components
     28They can be embedded (autonomous) applications
     29such as personal digital assistants (PDA), ambiant computing components,
    3030or wireless sensor networks (WSN)
    3131They can also be extension boards connected to a PC to accelerate a specific computation,
    3232as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
    33 \\
    34 The COACH project fundamental issues are related to design methodologies
    35 for digital systems, providing estimation, exploration and design tools
    36 targeting both performance and power optimization at all the abstraction
    37 levels of the flow (system, architecture, algorithm and logic).
    38 
     33\par
    3934%verrous scientifiques et techniques
    4035\vspace*{.9ex}\par
    41 The COACH environment mixes and integrates several hardware and software technologies.
    42 The more important technologies are:
     36The COACH environment will integrate several hardware and software technologies:
    4337\begin{description}
    4438\item[Design Space Exploration]
    … …  
    6054    The HLS tools of COACH will support a common language and coding style to avoid
    6155    re-engineering by the designer.
    62 \item[Targeted hardware architecture and technology]
     56\item[Platform based design]
    6357    COACH will handle both \altera and \xilinx FPGA devices.
    6458    COACH will define architectural templates that can be customized by adding
    6559    dedicated coprocessors and ASIPs and by fixing template parameters such as
    66     the number of CPU and the operating system.
     60    the number of embedded processors or the number of sizes of embedde memory banks,
     61    or the embedded the operating system.
    6762    Basically, the 3 following architectural templates will be provided:
    6863    \begin{enumerate}
    … …  
    7671    Moreover, the specification of the application will be independant of both the
    7772    architectural template and the target FPGA device.
    78 \item[Communication interfaces]
    79     Coach will define and implement an homogeneous HW/SW communication infrastructure and
    80     communication APIs (Application Programming Interface).
    81     These laters are on-chip communications between processors and coprocessors,
    82     and external communications between the FPGA and the host PC.
     73\item[Hardware/Software communication middleware]
     74    Coach will implement an homogeneous HW/SW communication infrastructure and
     75    communication APIs (Application Programming Interface), that will be used for
     76    communications between software tasks running on embedded processors and
     77    dedicated hardware coprocessors,
    8378\end{description}
    8479The COACH design flow will be dedicated to system designers, and will as
    … …  
    9994MPSoC architectures (\tima, \ubs, \upmc),
    10095ASIP architectures (\irisa),
    101 High Level Synthesis (\tima, \ubs, \upmc) and compilation (\lip).
     96High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip).
    10297\\
    103 %The CoACH proposal can be described as an extension of the SoCLib virtual
    104 %prototyping platform to the FPGA technologies.
    10598The COACH project does not start from scratch.
    10699It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
    … …  
    115108\par
    116109The COACH proposal has been prepared during one year by a technical working group
    117 involving all the academic partners (one monthly meeting from january 2009 to february
    118 2010). The objective of these meetings was to analyse the issues of integrating
    119 and enhancing the formers tools and tecnnologies into a unique framework allowing to both
    120 virtual prototyping and hardware generation.
     110involving the 5 academic partners (one monthly meeting from january 2009 to february
     1112010). The objective was to analyse the issues of integrating
     112and enhancing the existing tools and tecnnologies into a unique framework.
     113Most of the general software architecture of the proposed design flow (including the
     114exchange format specification) has been define by this working group.
    121115Because the SocLib platform is the base of this project, it may be described as an
    122116extension of the SoCLib platform.
     117
     118%The main development steps of the COACH project are:
     119%\begin{enumerate}
     120%   \item Definition of the end user inputs:
     121%    The coarse grain parallelism of the application will be described as a communicating
     122%    task graph, each task being described in C language.
     123%    Similarly the architectural templates with their parameters and the design constraints
     124%    will be specified.
     125%  \item Definition of an internal format for representing task.
     126%  \item Development of the GCC pluggin for generating the internal format of a
     127%    C task.
     128%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
     129%    the internal format. This will allow to swap from one tool to another one, and to
     130%    chain them if necessary.
     131%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
     132%    platform to generate the bitstream for the various FPGA families and architectural
     133%    templates.
     134%  \item Development of new tools such as ASIP compiler, HPC design environment and
     135%    dynamic reconfiguration of FPGA devices.
     136%\end{enumerate}
     137
    123138\par
    124 The main development steps of the COACH project are:
    125 \begin{enumerate}
    126    \item Definition of the end user inputs:
    127     The coarse grain parallelism of the application will be described as a communicating
    128     task graph, each task being described in C language.
    129     Similarly the architectural templates with their parameters and the design constraints
    130     will be specified.
    131   \item Definition of an internal format for representing task.
    132   \item Development of the GCC pluggin for generating the internal format of a
    133     C task.
    134   \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
    135     the internal format. This will allow to swap from one tool to another one, and to
    136     chain them if necessary.
    137   \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
    138     platform to generate the bitstream for the various FPGA families and architectural
    139     templates.
    140   \item Development of new tools such as ASIP compiler, HPC design environment and
    141     dynamic reconfiguration of FPGA devices.
    142 \end{enumerate}
    143 \par
    144 The two major FPGA companies \altera and \xilinx are participating in this
    145 project to support the partners providing the software technologies, and to
    146 help to generate efficient bitsream for both FPGA families.
     139Two major FPGA companies are involved in the project : \xilinx will contribute
     140as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
     141providing documentation and development boards (\altera). These two companies are strongly motivated
     142to help the COACH project to generate efficient bitsream for both FPGA families.
    147143The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
    148144real use cases to benchmark the COACH design environment.
    … …  
    152148The architectural templates, and the COACH software tools will be distributed under the
    153149GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
    154 IP core library) will be freely available for non commercial use. Commercial licences
    155 will be negociated for industrial exploitation.
     150IP core library) will be freely available for non commercial use. For industrial exploitation
     151the technology providers are ready to propose commercial licenses, directly to the end user,
     152or through a third party.
    156153

  • anr/section-2.1.tex

    r72 r97  
    1 Microelectronic allows the integration of complicated functions into products, increases
     1Microelectronic components allow the integration of complicated functions into products, increases
    22commercial attractivity of these products and improves their competitivity.
    3 Multimedia and communication sectors have taken advantage from microelectronics facilities
    4 thanks to the developpment of design methodologies and tools for real time embedded
    5 systems.
    6 Many other sectors could benefit from microelectronics if these methologies and tools were
    7 adapted to their features. The Non Recurring Engineering (NRE) costs involded in designing
    8 and manufacturing an ASIC is very high.
     3Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
     4thanks to the developpment of design methodologies and tools for embedded systems.
     5\par
     6Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing
     7and manufacturing ASICs is very high.
    98An IC foundry costs several billions of euros and the fabrication of a specific circuit
    109costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
    1110million USD.
    12 Consequently, it is generally unfeasible to design and fabricate ASICs in
    13 low volumes and ICs are designed to cover a broad applications spectrum at the cost of
    14 some performance degradation.
    15 \\
     11Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium
     12volume markets.
     13\par
    1614Today, FPGAs become important actors in the computational domain that was originally dominated
    1715by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
    18 on a per-application basis. At the same time, for many applications, FPGAs offer significant performance benefits over
    19 microprocessors implementation. Although these benefits are still
    20 generally an order of magnitude less than in equivalent ASIC implementations, low costs
     16on a per-application basis. For many applications, FPGAs offer significant performance benefits over
     17microprocessors implementation. There is still a performance degradation of one order
     18of magnitude versus an equivalent ASIC implementations, but low cost
    2119(500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive
    2220choice for low-to-medium volume applications.
    … …  
    2725complex systems like multi-processors platform with application dedicated coprocessors.
    2826Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
    29 various application domains. The ``high end'' lines concern only FPGA with high logic capacity for complex system implementations.
     27various application domains.
    3028This market is in significant expansion and is estimated to 914\,M\$ in 2012.
    31 Using FPGA limits the NRE costs to the design cost. This boosts the developpment of of automatic design tools and methodologies.
    3229
    3330\begin{table}\leavevmode\center
    … …  
    5047\end{table}
    5148\par
    52 Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
    53 Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
    54 for very high performance (HPC) primes over other requirements. They tend to use the highest
    55 performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
    56 architectures and algorithms. These companies show up in different "traditional" applications and market
    57 segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
    58 emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
    59 at 214\,M\$.
    60 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
    61 of FPGA-based solutions is limited by the lack of design flow automation. Nowadays, there are neither commercial
    62 nor academic  tools covering the whole design process.
    63 For instance, with SOPC Builder from Altera, users can select and parameterize IP components
    64 from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor
    65 and bus interface cores, as well as incorporate their own IP. Designers can then generate
    66 a synthesized netlist, simulation test bench and custom software library that reflect the hardware
    67 configuration.
    68 Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
    69 (Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
    70 simulate the platform at a high design level (systemC).
    71 In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
    72 tool to implement designs on Altera devices (Stratix, Arria, Cyclone).
    73 PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description.
    74 Nevertheless, they can only deal with data dominated applications and they do not handle the platform level.
    75 The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to
    76 Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs.
    77 Designers can design and simulate a system using MATLAB and Simulink. The tool will then
    78 automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx
    79 pre-optimized algorithms.
    80 However, this tool targets only DSP based algorithms.
    81 \\
    82 Consequently, designers developping an embedded system needs to master for example
    83 SoCLib for design exploration,
    84 SOPC Builder at the platform level,
    85 PICO for synthesizing the data dominated coprocessors
    86 and Quartus for design implementation.
    87 This requires an important tools interfacing effort and makes the design process very complex
    88 and achievable only by designers skilled in many domains.
    89 The aim of the COACH project is to integrate all these tools in the same framework and to allow \textbf{pure software} developpers to realize embedded systems.
     49
     50This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion of FPGA-based solutions
     51is limited by the lack of design flow automation. Nowadays, there are neither commercial
     52nor academic  tools covering the whole design process from the system level specification to the bit stream
     53generation.
     54%For instance, with SOPC Builder from Altera, users can select and parameterize IP components
     55%from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor
     56%and bus interface cores, as well as incorporate their own IP. Designers can then generate
     57%a synthesized netlist, simulation test bench and custom software library that reflect the hardware
     58%configuration.
     59%Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
     60(%Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
     61%simulate the platform at a high design level (systemC).
     62%In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
     63%tool to implement designs on Altera devices (Stratix, Arria, Cyclone).
     64%PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description.
     65%Nevertheless, they can only deal with data dominated applications and they do not handle the platform level.
     66%The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to
     67%Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs.
     68%Designers can design and simulate a system using MATLAB and Simulink. The tool will then
     69%automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx
     70%pre-optimized algorithms.
     71%However, this tool targets only DSP based algorithms.
     72
     73Consequently, a designer developping an embedded system needs to master
     74four different design environment : a virtual prototyping environment such as SoCLib for system level exploration,
     75an architecture compiler (such as SOPC Builder from Altera, or System generator from Xilinx) to define the
     76hardware architecture, one or several HLS tools (such as PICO [CITATION] ou CATAPULT [CITATION]) for
     77coprocessor synthesis, and finally a backend synthesis tool (such as Quartus or YYYY) for the bit-stream generation.
     78
     79The aim of the COACH project is to integrate all these design steps into a single design framework.
     80and to allow \textbf{pure software} developpers to develop embedded systems.
    9081\par
    91 The combination of the framework dedicated to software developpers and FPGA target, allows to gain
    92 market share over Multi-core CPUs and GPUs HPC based solutions.
    93 Moreover, one can expect that small and even very small companies will be able to propose embedded
    94 system and accelerating solutions for standard software applications with acceptable prices, thanks
    95  to the elimination of huge hardware investment in opposite to ASIC based solution.
    96 \\
    97 This new market may explode in the same way as the micro-computer market in the eighties. This success was due
    98 to the low cost of the first micro-processors (compared to main frames) and the advent of high level
    99 programming languages which allowed a high number of programmers to launch start-ups in software
    100 engineering.
     82We believe that the combination of a design environment dedicated to software developpers and the FPGA target,
     83allows small and even very small companies to propose embedded system and accelerating solutions
     84for standard software applications with acceptable prices.
    10185
     86This new market may explode in the same way as the micro-computer market in the eighties,
     87whose success was due to the low cost of the first micro-processors (compared to main frames)
     88and the advent of high level programming languages which allowed a high number of programmers
     89to launch start-ups in software engineering.
     90

  • anr/section-2.2.tex

    r94 r97  
    22% Relevance of the proposal
    33
    4 The COACH proposal addresses directly the Embedded Systems of
     4The COACH proposal addresses directly the \emph{Embedded Systems} item of
    55the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
    6 providing the industry the novel design capabilities enabling them to increase their
     6providing SMEs novel design capabilities enabling them to increase their
    77design productivity with design exploration and synthesis methods that are placed on top
    8 of the state-of-the-art methods, and thus, allowing the industry to better cope with the
    9 complexity of designed digital systems.
     8of the state-of-the-art methods.
     9This project proposes an open-source framework for mapping multi-tasks software applications
     10on Field Programmable Gate Array circuits (FPGA).
     11
    1012\par
    11 COACH will also contribute to the following strategic objectives of the ARPEGE program:
    12 COACH will specifically contribute to enable the building of open development and run-time
    13 environments for software and services, interoperable middleware and tools to support
     13COACH will contribute to build an open development and run-time
     14environment, including communication middleware and tools to support
    1415developers in the production of embedded software, through all phases of the software lifecycle,
    1516from requirements analysis until deployment and maintenance.
    16 \\
     17
    1718More specifically, COACH focuses on:
    1819\begin{itemize}
    … …  
    2526environment, suitable for co-operative and distributed development.
    2627\end{itemize}
     28
    2729COACH outcome will contribute to strengthen Europe's competitive position by developing
    2830technologies and methodologies for product development, focusing (in compliance with the
    … …  
    3133in COACH will enable new and emerging information technologies for the development,
    3234manufacturing and integration of devices and related software into end-products.
    33 \\
    34 This project proposes an open-source framework for architecture synthesis targeting
    35 Field Programmable Gate Array circuits (FPGA).
     35
    3636\par
    37 % LIEN AVEC AUTRES PROJETS: LIP6/TIMA OK
    38 To evaluate the different architectures, the project uses the prototyping platform of the SoCLIB ANR project (2006-2009).
    39 \\ % LIEN AVEC AUTRES PROJETS: IRISA
    40 The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing
    41 joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern
     37The COACH project will benefit from a number of previous projects:
     38\begin{itemize}
     39\item SOCLIB :
     40The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories
     41and 6 industrial companies.
     42It supports system level virtual prototyping of shared memory, multi-processors
     43architectures, and provides tools to map multi-tasks software application on these
     44architectures, for reliable performance evaluation.
     45The core  of this platform is a library of SystemC simulation models for
     46general purpose IP cores such as processors, buses, networks, memories, IO controller.
     47The platform provides also embedded operating systems and software/hardware
     48communication middleware.
     49The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
     50this project enhances SoCLib by providing the synthesisable VHDL models required
     51for FPGA synthesis.
     52\item ROMA :
     53The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
     54reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
     55computing structure to computation patterns that can be speed-up and/or power efficient.
     56The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
     57operators to avoid traditional overhead, in reconfigurable devices, related to
     58the interconnection network.
     59The project will  borrow from the ROMA ANR xxproject (2007-2009) and the ongoing
     60joint INRIA-STMicro Nano2012 project to adapt existing pattern
    4261extraction algorithms and datapath merging techniques to the synthesis of customized
    4362ASIP processors.
    44 \par
     63\item TSAR :
     64The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a
     65scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
     66plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
     67models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
     68\item BioWic
    4569On the HPC application side, we also hope to benefit from the experience in
    4670hardware acceleration of bioinformatic algorithms/workfows gathered by the
    4771CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    4872be able to validate the framework on real-life HPC applications.
     73\end{itemize}
     74
     75
    4976\par
    50 %%% EXPERTISE DANS DES DOMAINES: LIP6/TIMA/LAB-STIC OK
    51 Regarding the expertise in  High Level Synthesis (HLS), the project
    52 leverages on know-how acquired over 15 years with GAUT~\cite{gaut08} project
    53 developped in Lab-STIC laboratory and UGH~\cite{ugh08} project developped
    54 in LIP6 and TIMA laboratories. \\
    55 Regarding architecture synthesis skills, the project is based on a know-how
    56 acquired over 10 years with the COSY European project (1998-2000) and the
    57 DISYDENT~\cite{disydent05} project developped in LIP6.\\
    58 %%% EXPERTISE DANS DES DOMAINES: IRISA OK
     77The laboratories involved in the COACH project have a well estabished expertise
     78in the following domains:
     79\begin{itemize}
     80\item
     81In the field of High Level Synthesis (HLS), the project
     82leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
     83developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped
     84by the LIP6 and TIMA laboratories.
     85\item
     86Regarding system level architecture, the project is based on the know-how
     87acquired by the LIP6 and TIMA laboratories in the framework of various projects 
     88(COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication
     89architectures for shared memory multi-processors systems.
     90As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
     91\item
    5992Regarding Application Specific Instruction Processor (ASIP) design, the
    6093CAIRN group at INRIA Bretagne Atlantique benefits from several years of
    … …  
    6295(Armor/Calife\cite{CODES99} since 1996, and the Gecos
    6396compilers\cite{ASAP05} since 2002).
    64 %%% EXPERTISE DANS DES DOMAINES: LIP OK
    65 Compsys was founded in 2002 by several senior researchers with experience in
     97\item
     98In the field of compilers, the Compsys group was founded in 2002
     99by several senior researchers with experience in
    66100high performance computing and automatic parallelization. They have been
    67101among the initiators of the polyhedral model, a theory which serve to
    … …  
    69103programs. It is expected that the techniques developped by Compsys for
    70104parallelism detection, scheduling, process construction and memory management
    71 will be very useful as a first step for a high-level synthesis tool.
     105will be very useful as a Rfront end for the a high-level synthesis tools.
     106\end{itemize}
     107
    72108
    73109\par
    74 %%% DESCRIPTION DES PROJETS ANR UTILISES: SOCLIB OK
    75 The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to
    76 describe hardware architectures with shared memory space and to deploy software
    77 applications on them to evaluate their performance.
    78 The heart of this platform is a library containing simulation models (in SystemC)
    79 of hardware IP cores such as processors, buses, networks, memories, IO controller.
    80 The platform provides also embedded operating systems and software/hardware
    81 communication components useful to implement applications quickly.
    82 However, the synthesisable description of IPs have to be provided by users. \\
    83 This project enhances SoCLib by providing synthesisable VHDL of standard IPs.
    84 In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable
    85 description of an IP (coprocessor) from a sequential algorithm.
    86 \par
    87 
    88 %In multimedia applications, image processing is the major challenge embedded systems
    89 %have to face.  It is computationally intensive with power requirements to meet. Image
    90 %processing at pixel level, like image filtering, edge detection, pixel correlation or at
    91 %bloc level such as motion estimation have to be accelerated. For that goal,
    92 
    93 The ROMA project involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
    94 reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
    95 computing structure to computation patterns that can be speed-up and/or power efficient.
    96 On the contrary of previous attempts  to design reconfigurable processors, which have
    97 focused on the definition of complex interconnection network between simple operators,
    98 the ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
    99 operators to avoid traditional overhead, in reconfigurable devices, related to
    100 the interconnection network.
    101 %%% DESCRIPTION DES PROJETS ANR UTILISES: ROMA FIXME:IRISA (~10 lignes)
    102 %%% 2 IRISA ?
    103 %%% 2 ASIP tool such as ...
    104 %%% 2 ...
    105 %%% 2 Coach uses pattern extractions from ROMA
    106 \mustbecompleted{ROMA \\...\\...\\...\\...\\...\\...\\...\\IRISA (SD)\\}
    107 \par
    108110% FIXME A VERIFIER L'appel d'offre
    109 The different points proposed in this project cover priorities defined by the commission
     111Finally, it is worth to note that this project cover priorities defined by the commission
    110112experts in the field of Information Technolgies Society (IST) for Embedded
    111 systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
     113Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
    112114and allowing to apply efficiently applications and various products on embedded platforms,
    113115considering resources constraints (delais, power, memory, etc.), security and quality
    114116services$>>$.
    115 \\
    116 Our team aims at covering all the steps of the design flow of architecture synthesis.
    117 Our project overcomes the complexity of using various synthesis tools and description
    118 languages required today to design architectures.
    119117
     118

  • anr/section-2.tex

    r69 r97  
    1 The emerging complex and integrated heterogeneous embedded system platforms require
    2 adequate design methods to efficiently model, explore, analyze and design the ever complex software
    3 and hardware architectures. In order to rapidly meet the increasing performance requirements and a pressure
    4 to lower development cost and shorten time-to-market, future embedded systems suppliers
    5 will have to adopt new design methodologies and flows in order to keep pace with the increasing
    6 complexity of design problems. Such methods, addressing these challenges starting from high levels of
    7 abstraction, will have to perform large solution space explorations both for software and (possibly
    8 reconfigurable) hardware, reducing the design effort and offering a high predictability of results
    9 with respect to cost and performance objectives.
    10 \\
    11 Current design methodologies provide quite low-level abstraction capabilities. However in a few years
    12 from now, tens of programmable processors will be embedded in an IC with more than 100M
    13 transistors, therefore adding to the complexity of the problem of designing such systems.
    14 Taking into account that the complexity of the software part is increasing at an even
    15 faster rate, current solutions for design space exploration, mainly manually based, by no
    16 means do supply an adequate efficiency.
    17 Consequently, there is an urgent need to leverage system level
    18 exploration through the use of a high-level specification of the application and an early design
    19 space exploration step. The first system oriented approaches are appearing, among which those
    20 based on C/C++ and SystemC are the most popular. Such approaches can take place before and/or after
    21 the co-design or architecture refinement steps and target the design space pruning in order to fully
    22 exploit potential solutions that meet design and application constraints (power, latency,
    23 throughput) within the design and market timeframe.
    24 \\
    25 Thus, new system-level design flows need to be developed, enabling the exploration of an application
    26 independently of the implementation, almost at the beginning of the design process.
    27 A fundamental element of this evolution is the definition of abstraction layers that should allow the
    28 performance driven re-use of software and hardware components at the system level.
    29 In this context, COACH will combine modeling and estimation methods and compilers and
    30 design space exploration techniques. This approach will be a radical innovation in
    31 embedded system design methodology.
    32 \\
    33 The reason is that the COACH framework is applied before high-level design tools in the embedded
    34 systems design flow. In that way, it will make possible a real and efficiently combined
    35 exploitation of high-level synthesis tools, parallelizing approaches and compilers, already
    36 available on the market. These tools and approaches are not yet massively adopted, precisely
    37 because this preliminary design step is missing. COACH will indeed permit (i) to predict and
    38 control implementation optimizations, (ii) to target multiple implementation technologies
    39 (and thus the associated tools) from a unique specification and (iii) to efficiently integrate high
    40 and low-level design tools in a unique seamless design flow.
    41 \\
    42 The performance estimation methods combined with the design space exploration techniques will
    43 finally allow the design process to start from system level specification and automatically explore the
    44 potential architectures in order to find out the optimal implementation in a shorter design time and at
    45 a lower global cost.
     1The first objective of COACH is to provide SMEs (Small and Medium Enterprises) an open-source framework to
     2design embedded system on FPGA devices.
     3
     4Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit)
     5is not an option for most SMEs. Fortunately, the new FPGA (Field Programmable Gate Array) components,
     6such as the Virtex5 family from Xilinx, or the Stratix4 family from Altera can implement a complete
     7multi-processor architecture on a single chip.
     8
     9%But the design of a SoC (System on Chip) or MPSoC (Multi-Processor System on Chip) is a complex
     10%task, requiring adequate design methods to efficiently model, explore, and analyze the
     11%interactions between the software application and the hardware architectures. Moreover, most SMEs do not have
     12%in-home expertise in the field of hardware design or VHDL/Verilog modeling.
     13%In order to meet the increasing performance requirements, to decrease the development cost, and to
     14%shorten the time-to-market, they need new design methodologies.
     15
     16%Current design methodologies provide quite low-level abstraction capabilities, and
     17%there is an urgent need to leverage system level exploration through the use of a high-level
     18%specification of the application and  design space exploration tools.
     19
     20%The first system oriented approaches are appearing, among which those
     21%based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs.
     22
     23The COACH project will leverage on the expertise gained in the field of virtual prototyping
     24with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
     25An architectural template is a generic, parametrized architecture, relying on a predefined library
     26of IP cores.
     27Besides using a specific collection of general purpose IP cores (such as processors cores,
     28embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural
     29template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools.
     30During this project, the COACH partners will develop three different architectural templates:
     31
     32\begin{enumerate}
     33\item An \altera architectural template based on the \altera IP core library and the AVALON system bus.
     34\item A \xilinx architectural template based on the Xlinx IP core library and the OPB system bus.
     35\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure.
     36\end{enumerate}
     37
     38The proposed design flow starts from a high level description of the application, specified as a set of
     39parallel tasks written in C, without any assumption on the hardware or software implementation
     40of these tasks. It let the system
     41designer in charge of expessing the coarse grain parallelism of the application, gives the designer
     42the possibility to explore various mapping of the application on the selected template architecture,
     43and offers a high predictability of results with respect to cost and performance objectives.
     44
     45When this interactive, system level, design space exploration is completed (converging to
     46a specific mapping on a specific version of the selected architectural template), the rest of the flow
     47is fully automated: The synthesisable VHDL models for the various hardware components, as well as the binary
     48code for the software running on the embedded processors, and the bit-stream to program the the target FPGA
     49will be automatically generated by the COACH tools.
     50
    4651\par
    47 To get an efficient embedded system, the system designer has to take into account
    48 application characteristics when it chooses one of the available technologies.
    49 This choice is not easy and in most cases the designer has to try different
    50 technologies to retain the most adapted one.
    51 \\
    52 The first objective of COACH is to provide an open-source framework to
    53 design embedded system on FPGA devices.
    54 The COACH framework allows the designer to explore various software/hardware
    55 partitions of the target application, to run timing and functional
    56 simulations and to generate automatically both the software and the
    57 synthesizable description of the hardware.
    58 The main topics of the project are:
    59 \begin{itemize}
    60 \item
    61 \textbf{Design space exploration}: It consists in analysing the application running
    62 on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
    63 hardware/software partitioning of tasks depending on technology choice.
    64 This exploration is driven basically by throughput, latency and power
    65 consumption criteria.
    66 \item
    67 \textbf{Micro-architectural exploration}: When hardware components are required, the
    68 HLS tools of the framework generate them automatically. At this stage the
    69 framework provides various HLS tools that allow the micro-architectural space
    70 design exploration. The exploration criteria also are throughput, latency
    71 and power consumption.
    72 At this stage, preliminary source-level transformations will be
    73 required to improve the efficiency of the target component.
    74 For instance, one may transform a loop nest to expose parallelism,
    75 or shrink an array to promote it to a register or reduce a memory footprint.
     52The strength of the COACH approach is the strong integration of the high-level synthesis tools
     53in a plat-form based design flow supporting virtual prototyping and design space exploration.
     54Most building blocks already exist (resulting from previous projects): the GAUT
     55or UGH synthesis tools, the MutekH or DNA embedded operating systems, the ASIP technology,
     56the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool,
     57as well as the SoCLib library of systemC simulation models. They must now be integrated in
     58a consistent design flow.
     59%The five academic laboratories worked very closely during more than one year (one monthly meeting
     60%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
     61%those various technologies, and to define the detailed architecture of the proposed design flow.
     62\par
    7663
    77 \item
    78 \textbf{Performance measurement}: For each point in the design space,
    79 figures of merit are available such as throughput, latency, power
    80 consumption, area, memory allocation and data locality. They are evaluated
    81 using virtual prototyping, estimation or analyzing methodologies.
    82 \item
    83 \textbf{Targeted hardware technology}: The COACH description of a system is
    84 independent of the FPGA family.  Every point of the design
    85 space can be implemented on any FPGA having the required resources.
    86 Basically, COACH handles both Altera and Xilinx FPGA families.
    87 \end{itemize}
    88 As an extension of embedded system design, COACH deals also with High
    89 Performance Computing (HPC).
    90 In HPC, the kind of targeted application is an existing one running on a PC.
    91 The COACH framework helps designer to accelerate it by migrating critical parts into a
    92 SoC implemented on an FPGA plugged to the PC bus.
    93 \par
    94 COACH is the result of the will of several laboratories to unify their knowhow
    95 and skills in the following domains: Operating system and hardware
    96 communication (\tima, \upmc), SoC and MPSoC (\upmc and \tima), ASIP (\irisa) and
    97 HLS (\upmc, \ubs) and compilation (\irisa, \lip).
    98 The project objective is to integrate these various domains into a unique
    99 free framework (licence ...) masking as much as possible these domains and
    100 its different tools to the user.
     64In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks
     65have been previously developed by academic laboratories.
    10166
     67
     68%Finally, the key points of the proposed design flow are :
     69%\begin{itemize}
     70%\item
     71%\textbf{System level exploration}: The application coarse grain parallelism
     72%is explicitely described as a Tasks and Communication Graph (TCG).
     73%A template architecture is selected, and the performances are evaluated
     74%on various variant of this architecture using the SoCLib virtual protyping
     75%environment. This result in a specific hardware/software partitioning. 
     76%This system level exploration is fully controlled by the system designer, and is driven
     77%by cost, throughput, latency and power consumption criteria.
     78%
     79%\item
     80%\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been
     81%identified as mandatory, they will be generated by the high level synthesis (HLS) tools.
     82%The Coach framework will integrate various HLS tools, supporting the micro-architectural space
     83%design exploration. Here again, the exploration criteria are cost, throughput, latency
     84%and power consumption.
     85%At this stage, preliminary source-level transformations and optimisations by front-end
     86%tools will be required to improve the efficiency of the back-end HLS tools.
     87%
     88%\item
     89%\textbf{Early performance evaluation}: For each point in the design space,
     90%figures of merit must be available such as throughput, latency, power
     91%consumption, area, memory allocation and data locality. They are evaluated
     92%by reliable estimators obtained by running the actual multi-task software
     93%application on the virtual prototype.
     94%
     95%\item
     96%\textbf{Independance from the Target FPGA}: The COACH description of the system
     97%(both hardware and software) should be independent of the FPGA family. 
     98%Every point of the design space can be implemented on any FPGA component,
     99%as long as it contains the hardware ressources required by the selected architectural template.
     100%Basically, COACH will support both Altera and Xilinx FPGA families.
     101%\end{itemize}
     102%
     103
     104
     105

  • anr/section-6.1.tex

    r96 r97  
    102102The LIP6 is in charge of the technical coordination of the SoCLib national project, and is hosting
    103103the SoCLib WEB server.
    104 %The LIP6 will be in charge of integrating the Coach results in the frame work of
    105 %the SoCLib infrastructure to provide an open access to the Coach design environment.
    106 Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis,
    107 and the DSX tool for design space exploration, that will be two building blocks for the Coach design-flow.
     104In the SoCLin platform, the DSX tool is used for design space exploration.
     105It helps the system designer to describe the coarse grain parallelism of the software application
     106as a Task and Communication Graph, to configure the hardware architecture, and to map the
     107multi-task software application on the multi-processors architecture.
     108The DSX toll will be extended to support the FPGA target.
     109Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis
     110of control-dominated coprocessors.
     111This tool will be modified to be integrated in the Coach design flow.
    108112Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
    109113(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies

  • anr/table_lip_full.tex

    r90 r97  
    1 \begin{tabular}{|c|p{3.5cm}||r|r|r||r|}\hline
    2 number & \multicolumn{1}{c||}{title} & \multicolumn{3}{c||}{years } & total \\\cline{3-5}
    3  & & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c||}{3} &  \\\hline\hline
    4 D230 & \resstablestyletitle{Specification of {\tt xcoach} format} & 9.0 & 4.5 & 0.0 & 13.5 \\\hline
    5  & total Task-2 & 9.0 & 4.5 & 0.0 & 13.5 \\\hline
    6 \hline D430 & \resstablestyletitle{Process generation method} & 4.5 & 0.0 & 10.5 & 15.0 \\\hline
    7 D431 & \resstablestyletitle{Process and FIFO construction} & 4.5 & 12.0 & 15.0 & 31.5 \\\hline
    8  & total Task-4 & 9.0 & 12.0 & 25.5 & 46.5 \\\hline
    9 \hline
    10  & total & 18.0 & 16.5 & 25.5 & 60.0 \\\hline
    11 \end{tabular}

  • anr/table_lip_short.tex

    r90 r97  
    1 \begin{center}\begin{small}\begin{tabular}{|c|l||r|r|r||r|}\hline
    2  & title & \multicolumn{3}{c||}{years } & total \\\cline{3-5}
    3  &       & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c||}{3} &  \\\hline\hline
    4 Task-2 & Backbone infrastructure & 9.0 & 4.5 & 0.0 & 13.5 \\\hline
    5 Task-4 & HAS front-end & 9.0 & 12.0 & 25.5 & 46.5 \\\hline
    6 \hline
    7  & total &  18.0 & 16.5 & 25.5 & 60.0 \\\hline
    8 \end{tabular}\end{small}\end{center}
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