[59] | 1 | /* |
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| 2 | * $Id: test1.cpp 113 2009-04-14 18:39:12Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[82] | 9 | /* |
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| 10 | |
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[59] | 11 | #include <queue> |
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| 12 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h" |
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| 13 | |
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| 14 | |
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[62] | 15 | //===================================================================={test} |
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[71] | 16 | void test1 (string name, |
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[59] | 17 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param) |
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| 18 | { |
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| 19 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 20 | |
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| 21 | #ifdef STATISTICS |
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[71] | 22 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); |
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[59] | 23 | #endif |
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| 24 | |
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| 25 | Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(), |
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| 26 | #ifdef STATISTICS |
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[71] | 27 | _parameters_statistics, |
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[59] | 28 | #endif |
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[71] | 29 | _param); |
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[59] | 30 | |
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| 31 | #ifdef SYSTEMC |
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[82] | 32 | |
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[59] | 33 | string rename = ""; |
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| 34 | |
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| 35 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 36 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 37 | |
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| 38 | sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 39 | sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 40 | sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str()); |
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[71] | 41 | sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 42 | sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str()); |
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[59] | 43 | sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str()); |
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| 44 | sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str()); |
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| 45 | sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str()); |
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| 46 | sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); |
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| 47 | sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); |
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[78] | 48 | sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str()); |
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[59] | 49 | sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 50 | sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 51 | sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[78] | 52 | sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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| 53 | sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str()); |
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[59] | 54 | sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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[78] | 55 | sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 56 | sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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[59] | 57 | |
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[71] | 58 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 59 | sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 60 | sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 61 | sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 62 | sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 63 | sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); |
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[78] | 64 | // sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str()); |
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| 65 | sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str()); |
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[71] | 66 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 67 | sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str()); |
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| 68 | sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str()); |
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[78] | 69 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 70 | sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str()); |
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| 71 | sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str()); |
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[71] | 72 | sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str()); |
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[78] | 73 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 74 | sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str()); |
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[59] | 75 | |
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| 76 | sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 77 | sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 78 | sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 79 | sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); |
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| 80 | sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str()); |
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| 81 | sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str()); |
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| 82 | sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str()); |
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| 83 | |
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| 84 | sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 85 | sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 86 | sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 87 | sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); |
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| 88 | sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str()); |
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| 89 | sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str()); |
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| 90 | |
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[78] | 91 | sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; |
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| 92 | sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; |
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| 93 | sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; |
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| 94 | sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; |
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[59] | 95 | |
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[78] | 96 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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[71] | 97 | { |
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| 98 | out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 99 | out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 100 | out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str()); |
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| 101 | out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str()); |
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| 102 | } |
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[59] | 103 | |
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[82] | 104 | // Instanciation |
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[59] | 105 | |
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| 106 | cout << "<" << name << "> Instanciation of _Load_store_unit" << endl; |
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| 107 | |
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| 108 | (*(_Load_store_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 109 | (*(_Load_store_unit->in_NRESET)) (*(in_NRESET)); |
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| 110 | |
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| 111 | (*(_Load_store_unit-> in_MEMORY_IN_VAL ))(*( in_MEMORY_IN_VAL )); |
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| 112 | (*(_Load_store_unit->out_MEMORY_IN_ACK ))(*(out_MEMORY_IN_ACK )); |
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[71] | 113 | if (_param->_have_port_context_id) |
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[78] | 114 | (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(*( in_MEMORY_IN_CONTEXT_ID )); |
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[71] | 115 | if (_param->_have_port_front_end_id) |
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[78] | 116 | (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(*( in_MEMORY_IN_FRONT_END_ID )); |
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[71] | 117 | if (_param->_have_port_ooo_engine_id) |
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[78] | 118 | (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(*( in_MEMORY_IN_OOO_ENGINE_ID )); |
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[71] | 119 | if (_param->_have_port_packet_id) |
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[78] | 120 | (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); |
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[59] | 121 | (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); |
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[78] | 122 | (*(_Load_store_unit-> in_MEMORY_IN_TYPE ))(*( in_MEMORY_IN_TYPE )); |
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[59] | 123 | (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); |
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[78] | 124 | if (_param->_have_port_load_queue_ptr) |
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[59] | 125 | (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); |
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[78] | 126 | (*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT )); |
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[59] | 127 | (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(*( in_MEMORY_IN_IMMEDIAT )); |
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| 128 | (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(*( in_MEMORY_IN_DATA_RA )); |
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| 129 | (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(*( in_MEMORY_IN_DATA_RB )); |
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[78] | 130 | (*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC )); |
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| 131 | (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD )); |
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[59] | 132 | (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(*( in_MEMORY_IN_NUM_REG_RD )); |
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[78] | 133 | (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); |
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| 134 | (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); |
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[59] | 135 | |
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[71] | 136 | (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); |
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| 137 | (*(_Load_store_unit-> in_MEMORY_OUT_ACK ))(*( in_MEMORY_OUT_ACK )); |
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| 138 | if (_param->_have_port_context_id) |
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[78] | 139 | (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID )); |
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[71] | 140 | if (_param->_have_port_front_end_id) |
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[78] | 141 | (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))(*(out_MEMORY_OUT_FRONT_END_ID )); |
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[71] | 142 | if (_param->_have_port_ooo_engine_id) |
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[78] | 143 | (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID )); |
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[71] | 144 | if (_param->_have_port_packet_id) |
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[78] | 145 | (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); |
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| 146 | // (*(_Load_store_unit->out_MEMORY_OUT_OPERATION ))(*(out_MEMORY_OUT_OPERATION )); |
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| 147 | (*(_Load_store_unit->out_MEMORY_OUT_TYPE ))(*(out_MEMORY_OUT_TYPE )); |
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[71] | 148 | (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); |
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| 149 | (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); |
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| 150 | (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD )); |
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[78] | 151 | (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE )); |
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| 152 | (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE )); |
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| 153 | (*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE )); |
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[71] | 154 | (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION )); |
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[78] | 155 | (*(_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))(*(out_MEMORY_OUT_NO_SEQUENCE )); |
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| 156 | (*(_Load_store_unit->out_MEMORY_OUT_ADDRESS ))(*(out_MEMORY_OUT_ADDRESS )); |
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[59] | 157 | |
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| 158 | (*(_Load_store_unit->out_DCACHE_REQ_VAL ))(*(out_DCACHE_REQ_VAL )); |
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| 159 | (*(_Load_store_unit-> in_DCACHE_REQ_ACK ))(*( in_DCACHE_REQ_ACK )); |
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[71] | 160 | if (_param->_have_port_dcache_context_id) |
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| 161 | (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID)); |
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[59] | 162 | (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID )); |
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| 163 | (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS ))(*(out_DCACHE_REQ_ADDRESS )); |
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| 164 | (*(_Load_store_unit->out_DCACHE_REQ_TYPE ))(*(out_DCACHE_REQ_TYPE )); |
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| 165 | (*(_Load_store_unit->out_DCACHE_REQ_WDATA ))(*(out_DCACHE_REQ_WDATA )); |
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| 166 | |
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| 167 | (*(_Load_store_unit-> in_DCACHE_RSP_VAL ))(*( in_DCACHE_RSP_VAL )); |
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| 168 | (*(_Load_store_unit->out_DCACHE_RSP_ACK ))(*(out_DCACHE_RSP_ACK )); |
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[71] | 169 | if (_param->_have_port_dcache_context_id) |
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| 170 | (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID)); |
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[59] | 171 | (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID )); |
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| 172 | (*(_Load_store_unit-> in_DCACHE_RSP_RDATA ))(*( in_DCACHE_RSP_RDATA )); |
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| 173 | (*(_Load_store_unit-> in_DCACHE_RSP_ERROR ))(*( in_DCACHE_RSP_ERROR )); |
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| 174 | |
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| 175 | { |
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[78] | 176 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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[59] | 177 | { |
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[71] | 178 | (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); |
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| 179 | if (_param->_have_port_ooo_engine_id) |
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| 180 | (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i])); |
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| 181 | (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))(*(out_BYPASS_MEMORY_NUM_REG [i])); |
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| 182 | (*(_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))(*(out_BYPASS_MEMORY_DATA [i])); |
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[59] | 183 | } |
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| 184 | } |
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| 185 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 186 | Time * _time = new Time(); |
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| 187 | |
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[82] | 188 | // Simulation - Begin |
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[59] | 189 | |
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| 190 | // Initialisation |
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| 191 | |
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| 192 | const uint32_t seed = 0; |
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[71] | 193 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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[59] | 194 | |
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| 195 | srand(seed); |
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| 196 | |
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| 197 | const uint32_t nb_request = _param->_nb_packet; |
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| 198 | const uint32_t nb_word = nb_request; |
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| 199 | |
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[71] | 200 | //const int32_t percent_transaction_memory_in = 100; |
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| 201 | const int32_t percent_transaction_memory_out = 75; |
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| 202 | const int32_t percent_transaction_dcache = 75; |
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[59] | 203 | |
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[71] | 204 | const int32_t percent_exception = 0; |
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[59] | 205 | const int32_t percent_type_load = 0; |
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[71] | 206 | const int32_t percent_type_store = 50; |
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| 207 | const int32_t percent_miss_spec = 20; |
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| 208 | |
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| 209 | const uint32_t miss_rate = 10; |
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| 210 | const uint32_t miss_penality = 5; |
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[59] | 211 | |
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| 212 | if ((percent_type_load + |
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| 213 | percent_type_store ) > 100) |
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| 214 | TEST_KO("sum of percent_type > 100"); |
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| 215 | |
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[62] | 216 | const int32_t seuil_type_load = percent_type_load; |
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| 217 | const int32_t seuil_type_store = percent_type_store+percent_type_load; |
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[59] | 218 | |
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| 219 | uint32_t nb_request_memory_in ; |
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| 220 | uint32_t nb_request_memory_out; |
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| 221 | uint32_t nb_request_dcache ; |
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| 222 | |
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| 223 | MemoryRequest_t tab_request [nb_request]; |
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| 224 | priority_queue<MemoryRequest_t> fifo_request; |
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| 225 | |
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[71] | 226 | // emulation of memory |
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| 227 | Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, nb_word, _param->_size_general_data); |
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| 228 | Cache_t * _cache = new Cache_t (miss_rate, miss_penality); |
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[59] | 229 | |
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[71] | 230 | |
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[59] | 231 | SC_START(0); |
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| 232 | |
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| 233 | LABEL("Initialisation"); |
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| 234 | |
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| 235 | in_MEMORY_IN_VAL ->write(0); |
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| 236 | in_MEMORY_OUT_ACK->write(0); |
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| 237 | in_DCACHE_REQ_ACK->write(0); |
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| 238 | in_DCACHE_RSP_VAL->write(0); |
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| 239 | |
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| 240 | in_NRESET ->write(0); |
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| 241 | SC_START(5); |
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| 242 | in_NRESET ->write(5); |
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| 243 | |
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| 244 | LABEL("Loop of Test"); |
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| 245 | |
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[71] | 246 | try |
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[59] | 247 | { |
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[71] | 248 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 249 | { |
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| 250 | LABEL("Iteration "+toString(iteration)); |
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[62] | 251 | |
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[71] | 252 | LABEL("Structure's initialisation"); |
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[62] | 253 | |
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[71] | 254 | nb_request_memory_in = 0; |
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| 255 | nb_request_memory_out = 0; |
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| 256 | nb_request_dcache = 0; |
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[59] | 257 | |
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[71] | 258 | // Fill the request_queue |
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[59] | 259 | |
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[71] | 260 | Tlsq_ptr_t store_queue_ptr_write = 0; |
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| 261 | Tlsq_ptr_t load_queue_ptr_write = 0; |
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[59] | 262 | |
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[71] | 263 | bool store_queue_use [_param->_size_store_queue]; |
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| 264 | uint32_t nb_store_slot_use = 0; |
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| 265 | bool load_queue_use [_param->_size_load_queue ]; |
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[59] | 266 | |
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[71] | 267 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
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| 268 | store_queue_use [i] = false; |
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| 269 | for (uint32_t i=0; i<_param->_size_load_queue ; i++) |
---|
| 270 | load_queue_use [i] = false; |
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[59] | 271 | |
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[113] | 272 | double current_cycle = simulation_cycle(); |
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[71] | 273 | double cycle_min = current_cycle; |
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[59] | 274 | |
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[71] | 275 | Toperation_t operation_store [4] = {OPERATION_MEMORY_STORE_8, |
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| 276 | OPERATION_MEMORY_STORE_16, |
---|
| 277 | OPERATION_MEMORY_STORE_32, |
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| 278 | OPERATION_MEMORY_STORE_64}; |
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| 279 | |
---|
| 280 | Toperation_t operation_load [8] = {OPERATION_MEMORY_LOAD_8_Z, |
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| 281 | OPERATION_MEMORY_LOAD_8_S, |
---|
| 282 | OPERATION_MEMORY_LOAD_16_Z, |
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| 283 | OPERATION_MEMORY_LOAD_16_S, |
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| 284 | OPERATION_MEMORY_LOAD_32_Z, |
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| 285 | OPERATION_MEMORY_LOAD_32_S, |
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| 286 | OPERATION_MEMORY_LOAD_64_Z, |
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| 287 | OPERATION_MEMORY_LOAD_64_S}; |
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| 288 | |
---|
| 289 | Toperation_t operation_other [5] = {OPERATION_MEMORY_LOCK , |
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| 290 | OPERATION_MEMORY_INVALIDATE , |
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| 291 | OPERATION_MEMORY_PREFETCH , |
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| 292 | OPERATION_MEMORY_FLUSH , |
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| 293 | OPERATION_MEMORY_SYNCHRONIZATION}; |
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| 294 | |
---|
| 295 | |
---|
| 296 | const uint32_t nb_operation_store = (log2(_param->_size_general_data/8)+1); |
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| 297 | const uint32_t nb_operation_load = 2*(log2(_param->_size_general_data/8)+1); |
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| 298 | const uint32_t nb_operation_other = 5; |
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| 299 | |
---|
| 300 | LABEL("Fifo request initialisation"); |
---|
| 301 | // Init fifo_request |
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| 302 | for (uint32_t i=0; i<nb_request; i++) |
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| 303 | { |
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| 304 | double cycle; |
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| 305 | Tcontext_t context_id = 0; |
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| 306 | Tcontext_t front_end_id = 0; |
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| 307 | Tcontext_t ooo_engine_id = rand () % _param->_nb_ooo_engine; |
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| 308 | Tpacket_t packet_id = i; |
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| 309 | Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write; |
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| 310 | Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ; |
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| 311 | Toperation_t operation; |
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[59] | 312 | |
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[71] | 313 | int32_t percent = rand()%100; |
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[59] | 314 | |
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[71] | 315 | uint32_t size_queue; |
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[62] | 316 | |
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[71] | 317 | if (percent < seuil_type_load) |
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[62] | 318 | { |
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[71] | 319 | LABEL(" * LOAD"); |
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| 320 | operation = operation_load[(rand()%nb_operation_load)]; |
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| 321 | size_queue = _param->_size_load_queue; |
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| 322 | load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); |
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[62] | 323 | } |
---|
| 324 | else |
---|
| 325 | { |
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[71] | 326 | if (percent < seuil_type_store) |
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| 327 | { |
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| 328 | LABEL(" * STORE"); |
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| 329 | |
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| 330 | |
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| 331 | operation = operation_store[(rand()%nb_operation_store)]; |
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| 332 | size_queue = _param->_size_store_queue; |
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| 333 | store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue); |
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| 334 | } |
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| 335 | else |
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| 336 | { |
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| 337 | LABEL(" * OTHERS"); |
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| 338 | operation = operation_other[(rand()%nb_operation_other)]; |
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| 339 | // operation = operation_other[4]; |
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| 340 | size_queue = _param->_size_load_queue; |
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| 341 | load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue); |
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| 342 | } |
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[62] | 343 | } |
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[59] | 344 | |
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[71] | 345 | cycle = cycle_min; |
---|
| 346 | cycle_min ++; |
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[62] | 347 | |
---|
[71] | 348 | Ttype_t type = TYPE_MEMORY; |
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| 349 | Tgeneral_data_t address = rand()%(nb_word); |
---|
| 350 | Tgeneral_data_t offset = rand()%(nb_word); |
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[59] | 351 | |
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[71] | 352 | // LABEL ("Address step 1 : "+toString(address)+" - "+toString(offset)); |
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[59] | 353 | |
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[71] | 354 | percent = rand()%100; |
---|
| 355 | if (percent > percent_exception) |
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| 356 | address = address & (~ mask_memory_access(operation)); |
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| 357 | |
---|
| 358 | // LABEL ("Address step 2 : "+toString(address)+" - mask : "+toString((~ mask_memory_access(operation)))); |
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[59] | 359 | |
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[71] | 360 | if (offset > address) // max |
---|
| 361 | offset = address; |
---|
[59] | 362 | |
---|
[71] | 363 | Tgeneral_data_t immediat = offset; |
---|
| 364 | Tgeneral_data_t data_ra = address - offset; |
---|
[59] | 365 | |
---|
[71] | 366 | // LABEL ("Address step 3 : "+toString(address)+", "+toString(data_ra)+" - "+toString(immediat)); |
---|
| 367 | |
---|
| 368 | Tgeneral_data_t data_rb = static_cast<Tgeneral_data_t>(rand()); |
---|
| 369 | Tcontrol_t write_rd = 0; |
---|
| 370 | Tgeneral_address_t num_reg_rd = 0; |
---|
| 371 | bool write_spec_ko = is_operation_memory_store(operation) and ((rand()%100)<percent_miss_spec); |
---|
| 372 | |
---|
| 373 | tab_request [i].modif(cycle , |
---|
| 374 | context_id , |
---|
| 375 | front_end_id , |
---|
| 376 | ooo_engine_id , |
---|
| 377 | packet_id , |
---|
| 378 | operation , |
---|
| 379 | type , |
---|
| 380 | store_queue_ptr_write_old, |
---|
| 381 | load_queue_ptr_write_old , |
---|
| 382 | immediat , |
---|
| 383 | data_ra , |
---|
| 384 | data_rb , |
---|
| 385 | write_rd , |
---|
| 386 | num_reg_rd , |
---|
| 387 | write_spec_ko); |
---|
| 388 | |
---|
| 389 | cout << tab_request [i] << endl; |
---|
[62] | 390 | |
---|
[71] | 391 | fifo_request.push(tab_request [i]); |
---|
[62] | 392 | |
---|
[71] | 393 | double cycle_head = 0; |
---|
[62] | 394 | |
---|
[71] | 395 | if (is_operation_memory_store(operation)) |
---|
| 396 | { |
---|
| 397 | cycle_head = cycle_min; |
---|
| 398 | cycle_min ++; |
---|
[59] | 399 | |
---|
[71] | 400 | cout << " * Write head : " << toString(cycle_head) |
---|
| 401 | << endl |
---|
| 402 | << endl; |
---|
[62] | 403 | |
---|
[71] | 404 | fifo_request.push(MemoryRequest_t(cycle_head, |
---|
| 405 | context_id, |
---|
| 406 | front_end_id, |
---|
| 407 | ooo_engine_id, |
---|
| 408 | packet_id, |
---|
| 409 | (write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK, |
---|
| 410 | type, |
---|
| 411 | store_queue_ptr_write_old, |
---|
| 412 | 0, |
---|
| 413 | 0, |
---|
| 414 | 0, |
---|
| 415 | 0, |
---|
| 416 | 0, |
---|
| 417 | 0, |
---|
| 418 | write_spec_ko)); |
---|
| 419 | } |
---|
[59] | 420 | } |
---|
[62] | 421 | |
---|
[71] | 422 | LABEL("Simulation of this iteration ..."); |
---|
[62] | 423 | |
---|
[71] | 424 | while (nb_request_memory_out < nb_request) |
---|
| 425 | { |
---|
| 426 | cout << "*********************************************" << endl; |
---|
| 427 | cout << "Dump STORE_QUEUE_USE : " << endl; |
---|
| 428 | cout << " use " << nb_store_slot_use << endl; |
---|
| 429 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
| 430 | cout << " [" << i << "] " << store_queue_use [i] << endl; |
---|
| 431 | cout << "Dump LOAD_QUEUE_USE : " << endl; |
---|
| 432 | for (uint32_t i=0; i<_param->_size_load_queue ; i++) |
---|
| 433 | cout << " [" << i << "] " << load_queue_use [i] << endl; |
---|
| 434 | cout << "*********************************************" << endl; |
---|
[62] | 435 | |
---|
| 436 | |
---|
[71] | 437 | // ***** MEMORY_IN ***** |
---|
[59] | 438 | |
---|
[71] | 439 | // memory_in_val depends of three factors : |
---|
| 440 | // 1) request's fifo is not empty ? |
---|
| 441 | // 2) the slot destination is free ? |
---|
| 442 | // 3) The head of request's fifo can be issue : the number of cycle is more than current cycle |
---|
| 443 | |
---|
| 444 | bool can_execute = false; |
---|
| 445 | |
---|
| 446 | if (is_operation_memory_store(fifo_request.top()._operation)) |
---|
| 447 | can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation); |
---|
| 448 | else |
---|
| 449 | can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write]; |
---|
[59] | 450 | |
---|
[71] | 451 | in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and |
---|
| 452 | can_execute and |
---|
[113] | 453 | (simulation_cycle() >= fifo_request.top()._cycle)); |
---|
[59] | 454 | |
---|
[71] | 455 | if (_param->_have_port_context_id) |
---|
| 456 | in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id ); |
---|
| 457 | if (_param->_have_port_front_end_id) |
---|
| 458 | in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id ); |
---|
| 459 | if (_param->_have_port_ooo_engine_id) |
---|
| 460 | in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id ); |
---|
| 461 | if (_param->_have_port_packet_id) |
---|
| 462 | in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id ); |
---|
| 463 | in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation ); |
---|
| 464 | in_MEMORY_IN_TYPE ->write (fifo_request.top()._type ); |
---|
| 465 | in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write); |
---|
[78] | 466 | if (_param->_have_port_load_queue_ptr) |
---|
[71] | 467 | in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write ); |
---|
| 468 | in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat ); |
---|
| 469 | in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra ); |
---|
| 470 | in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb ); |
---|
| 471 | // in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd ); |
---|
| 472 | in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd ); |
---|
[59] | 473 | |
---|
[71] | 474 | in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out); |
---|
[62] | 475 | |
---|
[71] | 476 | // ***** DCACHE_REQ ***** |
---|
| 477 | in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache); |
---|
[62] | 478 | |
---|
[71] | 479 | // ***** DCACHE_RSP ***** |
---|
| 480 | bool have_rsp = _cache->have_rsp (); |
---|
| 481 | in_DCACHE_RSP_VAL->write(have_rsp); |
---|
[59] | 482 | |
---|
[71] | 483 | if (have_rsp) |
---|
| 484 | { |
---|
| 485 | in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id); |
---|
| 486 | in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id ); |
---|
| 487 | in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata ); |
---|
| 488 | in_DCACHE_RSP_ERROR ->write(_cache->front()._error ); |
---|
| 489 | } |
---|
[62] | 490 | |
---|
[71] | 491 | SC_START(0); |
---|
[59] | 492 | |
---|
[71] | 493 | LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read())); |
---|
| 494 | LABEL(" * fifo_request.empty : "+toString(fifo_request.empty())); |
---|
| 495 | LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle)); |
---|
| 496 | LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write))); |
---|
| 497 | LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write))); |
---|
| 498 | LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation ))); |
---|
| 499 | LABEL(" * can_execute : "+toString(can_execute)); |
---|
| 500 | |
---|
| 501 | if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read()) |
---|
[59] | 502 | { |
---|
[71] | 503 | LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in)); |
---|
| 504 | cout << fifo_request.top(); |
---|
| 505 | |
---|
| 506 | if (is_operation_memory_store(fifo_request.top()._operation)) |
---|
| 507 | { |
---|
| 508 | if (not is_operation_memory_store_head(fifo_request.top()._operation)) |
---|
| 509 | { |
---|
| 510 | store_queue_use [fifo_request.top()._store_queue_ptr_write] = true; |
---|
| 511 | nb_store_slot_use ++; |
---|
| 512 | } |
---|
| 513 | } |
---|
| 514 | else |
---|
| 515 | load_queue_use [fifo_request.top()._load_queue_ptr_write] = true; |
---|
| 516 | |
---|
| 517 | fifo_request.pop(); |
---|
| 518 | |
---|
| 519 | nb_request_memory_in ++; |
---|
[59] | 520 | } |
---|
| 521 | |
---|
[71] | 522 | LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read())); |
---|
| 523 | if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read()) |
---|
| 524 | { |
---|
| 525 | Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read(); |
---|
| 526 | |
---|
| 527 | LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id)); |
---|
| 528 | |
---|
| 529 | if (is_operation_memory_store(tab_request[packet_id]._operation)) |
---|
| 530 | { |
---|
| 531 | store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false; |
---|
| 532 | nb_store_slot_use --; |
---|
| 533 | } |
---|
| 534 | else |
---|
| 535 | load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false; |
---|
| 536 | |
---|
| 537 | nb_request_memory_out ++; |
---|
| 538 | |
---|
| 539 | // a lot of test |
---|
| 540 | TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id ); |
---|
| 541 | TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id ); |
---|
| 542 | TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id); |
---|
| 543 | TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id ); |
---|
[78] | 544 | // TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation ); |
---|
| 545 | TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY ); |
---|
[71] | 546 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), tab_request[packet_id]._write_rd ); |
---|
| 547 | TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd ); |
---|
| 548 | |
---|
| 549 | Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat; |
---|
| 550 | if (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation)))) |
---|
| 551 | TEST(Texception_t , out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_ALIGNMENT); |
---|
| 552 | else |
---|
| 553 | { |
---|
| 554 | if (tab_request[packet_id]._write_spec_ko) |
---|
| 555 | TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
| 556 | else |
---|
| 557 | { |
---|
| 558 | TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_NONE); |
---|
| 559 | |
---|
| 560 | if (is_operation_memory_load(tab_request[packet_id]._operation)) |
---|
| 561 | { |
---|
| 562 | Tgeneral_data_t read_lsq = _memory->read_lsq (((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | |
---|
| 563 | (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) | |
---|
| 564 | (tab_request[packet_id]._context_id)), |
---|
| 565 | (tab_request[packet_id]._immediat + |
---|
| 566 | tab_request[packet_id]._data_ra), |
---|
| 567 | tab_request[packet_id]._operation); |
---|
| 568 | cout << "MEMORY_OUT is a LOAD" << endl |
---|
| 569 | << " * operation : " << tab_request[packet_id]._operation << endl |
---|
| 570 | << std::hex |
---|
| 571 | << " * address : " << (tab_request[packet_id]._immediat + |
---|
| 572 | tab_request[packet_id]._data_ra) << endl |
---|
| 573 | << " * read_lsq : " << read_lsq << endl |
---|
| 574 | << " * memory_out_data : " << out_MEMORY_OUT_DATA_RD->read() << endl |
---|
| 575 | << std::dec; |
---|
| 576 | |
---|
| 577 | // TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), read_lsq); |
---|
| 578 | } |
---|
| 579 | } |
---|
| 580 | } |
---|
| 581 | } |
---|
| 582 | |
---|
| 583 | LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read())); |
---|
| 584 | if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read()) |
---|
| 585 | { |
---|
| 586 | Tcontext_t context_id; |
---|
| 587 | Tpacket_t packet_id ; |
---|
| 588 | if (_param->_have_port_dcache_context_id) |
---|
| 589 | context_id = out_DCACHE_REQ_CONTEXT_ID->read(); |
---|
| 590 | else |
---|
| 591 | context_id = 0; |
---|
| 592 | |
---|
| 593 | packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1; |
---|
[59] | 594 | |
---|
[71] | 595 | LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id)); |
---|
[59] | 596 | |
---|
[71] | 597 | // TEST(Tcontext_t ,out_DCACHE_REQ_CONTEXT_ID->read(),((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | |
---|
| 598 | // (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) | |
---|
| 599 | // (tab_request[packet_id]._context_id))); |
---|
| 600 | // TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS ->read(),(tab_request[packet_id]._immediat + |
---|
| 601 | // tab_request[packet_id]._data_ra) ); |
---|
| 602 | // TEST(Tdcache_type_t ,out_DCACHE_REQ_TYPE ->read(), operation_to_dcache_type(operation)); |
---|
| 603 | |
---|
| 604 | // if (is_operation_memory_store(operation)) |
---|
| 605 | // TEST(Tdcache_data_t ,out_DCACHE_REQ_WDATA ->read(),tab_request[packet_id]._data_rb); |
---|
[59] | 606 | |
---|
[71] | 607 | Tdcache_data_t rdata = _memory->access (context_id, out_DCACHE_REQ_ADDRESS->read(), out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read()); |
---|
[59] | 608 | |
---|
[71] | 609 | // test type : send or not a respons ! |
---|
| 610 | LABEL(" * rdata : " + toString(rdata)); |
---|
[62] | 611 | |
---|
[72] | 612 | if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or |
---|
[81] | 613 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_8 ) or |
---|
| 614 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_16) or |
---|
| 615 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_32) or |
---|
| 616 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_64)) |
---|
[71] | 617 | { |
---|
| 618 | LABEL(" * have_dcache_rsp"); |
---|
| 619 | |
---|
| 620 | _cache->push (context_id, |
---|
| 621 | out_DCACHE_REQ_PACKET_ID ->read(), |
---|
| 622 | rdata , |
---|
| 623 | 0); |
---|
| 624 | } |
---|
| 625 | } |
---|
[62] | 626 | |
---|
[82] | 627 | LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read())); |
---|
[71] | 628 | if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read()) |
---|
| 629 | { |
---|
| 630 | _cache->pop(); |
---|
| 631 | } |
---|
| 632 | |
---|
| 633 | _cache->end_cycle(); |
---|
| 634 | |
---|
| 635 | SC_START(1); |
---|
[62] | 636 | } |
---|
[59] | 637 | } |
---|
| 638 | } |
---|
[71] | 639 | catch (morpheo::ErrorMorpheo & error) |
---|
| 640 | { |
---|
| 641 | _memory->trace(); |
---|
| 642 | throw (error); |
---|
| 643 | } |
---|
| 644 | |
---|
| 645 | _memory->trace(); |
---|
| 646 | |
---|
[59] | 647 | |
---|
[82] | 648 | // Simulation - End |
---|
[59] | 649 | |
---|
| 650 | TEST_OK ("End of Simulation"); |
---|
| 651 | delete _time; |
---|
| 652 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
---|
| 653 | |
---|
| 654 | delete in_CLOCK; |
---|
| 655 | delete in_NRESET; |
---|
| 656 | |
---|
[71] | 657 | delete in_MEMORY_IN_VAL ; |
---|
| 658 | delete out_MEMORY_IN_ACK ; |
---|
| 659 | delete in_MEMORY_IN_CONTEXT_ID ; |
---|
| 660 | delete in_MEMORY_IN_FRONT_END_ID ; |
---|
| 661 | delete in_MEMORY_IN_OOO_ENGINE_ID ; |
---|
| 662 | delete in_MEMORY_IN_PACKET_ID ; |
---|
| 663 | delete in_MEMORY_IN_OPERATION ; |
---|
[59] | 664 | delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; |
---|
| 665 | delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; |
---|
[78] | 666 | delete in_MEMORY_IN_HAS_IMMEDIAT; |
---|
[71] | 667 | delete in_MEMORY_IN_IMMEDIAT ; |
---|
| 668 | delete in_MEMORY_IN_DATA_RA ; |
---|
| 669 | delete in_MEMORY_IN_DATA_RB ; |
---|
[78] | 670 | delete in_MEMORY_IN_DATA_RC ; |
---|
| 671 | delete in_MEMORY_IN_WRITE_RD ; |
---|
[71] | 672 | delete in_MEMORY_IN_NUM_REG_RD ; |
---|
[78] | 673 | delete in_MEMORY_IN_WRITE_RE ; |
---|
| 674 | delete in_MEMORY_IN_NUM_REG_RE ; |
---|
[71] | 675 | |
---|
[59] | 676 | delete out_MEMORY_OUT_VAL ; |
---|
| 677 | delete in_MEMORY_OUT_ACK ; |
---|
| 678 | delete out_MEMORY_OUT_CONTEXT_ID; |
---|
[71] | 679 | delete out_MEMORY_OUT_FRONT_END_ID; |
---|
| 680 | delete out_MEMORY_OUT_OOO_ENGINE_ID; |
---|
[59] | 681 | delete out_MEMORY_OUT_PACKET_ID ; |
---|
[78] | 682 | // delete out_MEMORY_OUT_OPERATION ; |
---|
| 683 | delete out_MEMORY_OUT_TYPE ; |
---|
[59] | 684 | delete out_MEMORY_OUT_WRITE_RD ; |
---|
| 685 | delete out_MEMORY_OUT_NUM_REG_RD; |
---|
| 686 | delete out_MEMORY_OUT_DATA_RD ; |
---|
[78] | 687 | delete out_MEMORY_OUT_WRITE_RE ; |
---|
| 688 | delete out_MEMORY_OUT_NUM_REG_RE; |
---|
| 689 | delete out_MEMORY_OUT_DATA_RE ; |
---|
[59] | 690 | delete out_MEMORY_OUT_EXCEPTION ; |
---|
[78] | 691 | delete out_MEMORY_OUT_NO_SEQUENCE; |
---|
| 692 | delete out_MEMORY_OUT_ADDRESS ; |
---|
[71] | 693 | |
---|
[59] | 694 | delete out_DCACHE_REQ_VAL ; |
---|
| 695 | delete in_DCACHE_REQ_ACK ; |
---|
| 696 | delete out_DCACHE_REQ_CONTEXT_ID; |
---|
| 697 | delete out_DCACHE_REQ_PACKET_ID ; |
---|
| 698 | delete out_DCACHE_REQ_ADDRESS ; |
---|
| 699 | delete out_DCACHE_REQ_TYPE ; |
---|
| 700 | delete out_DCACHE_REQ_WDATA ; |
---|
[71] | 701 | |
---|
[59] | 702 | delete in_DCACHE_RSP_VAL ; |
---|
| 703 | delete out_DCACHE_RSP_ACK ; |
---|
| 704 | delete in_DCACHE_RSP_CONTEXT_ID; |
---|
| 705 | delete in_DCACHE_RSP_PACKET_ID ; |
---|
| 706 | delete in_DCACHE_RSP_RDATA ; |
---|
| 707 | delete in_DCACHE_RSP_ERROR ; |
---|
[71] | 708 | |
---|
| 709 | { |
---|
| 710 | delete [] out_BYPASS_MEMORY_VAL ; |
---|
| 711 | delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; |
---|
| 712 | delete [] out_BYPASS_MEMORY_NUM_REG ; |
---|
| 713 | delete [] out_BYPASS_MEMORY_DATA ; |
---|
| 714 | } |
---|
[59] | 715 | #endif |
---|
| 716 | |
---|
| 717 | delete _Load_store_unit; |
---|
[71] | 718 | delete _memory; |
---|
| 719 | delete _cache; |
---|
[59] | 720 | #ifdef STATISTICS |
---|
| 721 | delete _parameters_statistics; |
---|
| 722 | #endif |
---|
| 723 | } |
---|
[82] | 724 | */ |
---|