[71] | 1 | /* |
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| 2 | * $Id: test2.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include <queue> |
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| 10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h" |
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| 11 | |
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| 12 | #define CYCLE_MAX 1024 |
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| 13 | |
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| 14 | #define LABEL(str) \ |
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| 15 | { \ |
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| 16 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ |
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| 17 | } while(0) |
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| 18 | |
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| 19 | #define SC_START(cycle_offset) \ |
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| 20 | do \ |
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| 21 | { \ |
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| 22 | /*cout << "SC_START (begin)" << endl;*/ \ |
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| 23 | \ |
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| 24 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
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| 25 | if (cycle_offset != 0) \ |
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| 26 | { \ |
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| 27 | cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \ |
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| 28 | } \ |
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| 29 | \ |
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| 30 | if (cycle_current > CYCLE_MAX) \ |
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| 31 | { \ |
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| 32 | TEST_KO("Maximal cycles Reached"); \ |
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| 33 | } \ |
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| 34 | sc_start(cycle_offset); \ |
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| 35 | /*cout << "SC_START (end )" << endl;*/ \ |
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| 36 | } while(0) |
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| 37 | |
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| 38 | |
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| 39 | //===================================================================={test} |
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| 40 | void test2 (void) |
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| 41 | { |
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| 42 | std::string name = "Test_Load_store_queue_manual"; |
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| 43 | |
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| 44 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 45 | |
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| 46 | |
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| 47 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters |
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| 48 | ( |
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| 49 | 4, //_size_store_queue |
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| 50 | 4, //_size_load_queue |
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| 51 | 2, //_size_speculative_access_queue |
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| 52 | 2, //_nb_port_check |
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| 53 | SPECULATIVE_LOAD_COMMIT, //_speculative_load |
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[78] | 54 | 0, //_nb_bypass_memory |
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[71] | 55 | 1, //_nb_context |
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| 56 | 1, //_nb_front_end |
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| 57 | 2, //_nb_ooo_engine |
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| 58 | 128,//_nb_packet |
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| 59 | 32, //_size_general_data |
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[78] | 60 | 2 , //_size_special_data |
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| 61 | 64, //_nb_general_register |
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| 62 | 16 //_nb_special_register |
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[71] | 63 | ); |
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| 64 | |
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| 65 | #ifdef STATISTICS |
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| 66 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); |
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| 67 | #endif |
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| 68 | |
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| 69 | Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(), |
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| 70 | #ifdef STATISTICS |
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| 71 | _parameters_statistics, |
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| 72 | #endif |
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| 73 | _param); |
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| 74 | |
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| 75 | #ifdef SYSTEMC |
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| 76 | /********************************************************************* |
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| 77 | * Déclarations des signaux |
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| 78 | *********************************************************************/ |
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| 79 | string rename = ""; |
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| 80 | |
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| 81 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 82 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 83 | |
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| 84 | sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 85 | sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 86 | sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 87 | sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 88 | sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 89 | sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str()); |
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| 90 | sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str()); |
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| 91 | sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str()); |
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| 92 | sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); |
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| 93 | sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); |
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[78] | 94 | sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str()); |
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[71] | 95 | sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 96 | sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 97 | sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[78] | 98 | sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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| 99 | sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str()); |
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[71] | 100 | sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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[78] | 101 | sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 102 | sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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[71] | 103 | |
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| 104 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 105 | sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 106 | sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 107 | sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 108 | sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 109 | sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); |
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[78] | 110 | // sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str()); |
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| 111 | sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str()); |
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[71] | 112 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 113 | sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str()); |
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| 114 | sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str()); |
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[78] | 115 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 116 | sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str()); |
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| 117 | sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str()); |
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[71] | 118 | sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str()); |
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[78] | 119 | sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 120 | sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str()); |
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[71] | 121 | |
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| 122 | sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 123 | sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 124 | sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 125 | sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); |
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| 126 | sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str()); |
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| 127 | sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str()); |
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| 128 | sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str()); |
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| 129 | |
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| 130 | sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 131 | sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 132 | sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 133 | sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); |
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| 134 | sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str()); |
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| 135 | sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str()); |
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| 136 | |
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[78] | 137 | sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; |
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| 138 | sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; |
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| 139 | sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; |
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| 140 | sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; |
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[71] | 141 | |
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[78] | 142 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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[71] | 143 | { |
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| 144 | out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str()); |
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| 145 | out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str()); |
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| 146 | out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str()); |
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| 147 | out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str()); |
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| 148 | } |
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| 149 | |
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| 150 | /******************************************************** |
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| 151 | * Instanciation |
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| 152 | ********************************************************/ |
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| 153 | |
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| 154 | cout << "<" << name << "> Instanciation of _Load_store_unit" << endl; |
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| 155 | |
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| 156 | (*(_Load_store_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 157 | (*(_Load_store_unit->in_NRESET)) (*(in_NRESET)); |
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| 158 | |
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| 159 | (*(_Load_store_unit-> in_MEMORY_IN_VAL ))(*( in_MEMORY_IN_VAL )); |
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| 160 | (*(_Load_store_unit->out_MEMORY_IN_ACK ))(*(out_MEMORY_IN_ACK )); |
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| 161 | if (_param->_have_port_context_id) |
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| 162 | (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(*( in_MEMORY_IN_CONTEXT_ID )); |
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| 163 | if (_param->_have_port_front_end_id) |
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| 164 | (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(*( in_MEMORY_IN_FRONT_END_ID )); |
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| 165 | if (_param->_have_port_ooo_engine_id) |
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| 166 | (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(*( in_MEMORY_IN_OOO_ENGINE_ID )); |
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| 167 | if (_param->_have_port_packet_id) |
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| 168 | (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); |
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| 169 | (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); |
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[78] | 170 | (*(_Load_store_unit-> in_MEMORY_IN_TYPE ))(*( in_MEMORY_IN_TYPE )); |
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[71] | 171 | (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); |
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[78] | 172 | if (_param->_have_port_load_queue_ptr) |
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[71] | 173 | (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); |
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[78] | 174 | (*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT )); |
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[71] | 175 | (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(*( in_MEMORY_IN_IMMEDIAT )); |
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| 176 | (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(*( in_MEMORY_IN_DATA_RA )); |
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| 177 | (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(*( in_MEMORY_IN_DATA_RB )); |
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[78] | 178 | (*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC )); |
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| 179 | (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD )); |
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[71] | 180 | (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(*( in_MEMORY_IN_NUM_REG_RD )); |
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[78] | 181 | (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); |
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| 182 | (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); |
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[71] | 183 | |
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| 184 | (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); |
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| 185 | (*(_Load_store_unit-> in_MEMORY_OUT_ACK ))(*( in_MEMORY_OUT_ACK )); |
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| 186 | if (_param->_have_port_context_id) |
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| 187 | (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID )); |
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| 188 | if (_param->_have_port_front_end_id) |
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| 189 | (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))(*(out_MEMORY_OUT_FRONT_END_ID )); |
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| 190 | if (_param->_have_port_ooo_engine_id) |
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| 191 | (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID )); |
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| 192 | if (_param->_have_port_packet_id) |
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| 193 | (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); |
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[78] | 194 | // (*(_Load_store_unit->out_MEMORY_OUT_OPERATION ))(*(out_MEMORY_OUT_OPERATION )); |
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| 195 | (*(_Load_store_unit->out_MEMORY_OUT_TYPE ))(*(out_MEMORY_OUT_TYPE )); |
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[71] | 196 | (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); |
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| 197 | (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); |
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| 198 | (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD )); |
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[78] | 199 | (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE )); |
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| 200 | (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE )); |
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| 201 | (*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE )); |
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[71] | 202 | (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION )); |
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[78] | 203 | (*(_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))(*(out_MEMORY_OUT_NO_SEQUENCE )); |
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| 204 | (*(_Load_store_unit->out_MEMORY_OUT_ADDRESS ))(*(out_MEMORY_OUT_ADDRESS )); |
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[71] | 205 | |
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| 206 | (*(_Load_store_unit->out_DCACHE_REQ_VAL ))(*(out_DCACHE_REQ_VAL )); |
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| 207 | (*(_Load_store_unit-> in_DCACHE_REQ_ACK ))(*( in_DCACHE_REQ_ACK )); |
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| 208 | if (_param->_have_port_dcache_context_id) |
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| 209 | (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID)); |
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| 210 | (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID )); |
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| 211 | (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS ))(*(out_DCACHE_REQ_ADDRESS )); |
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| 212 | (*(_Load_store_unit->out_DCACHE_REQ_TYPE ))(*(out_DCACHE_REQ_TYPE )); |
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| 213 | (*(_Load_store_unit->out_DCACHE_REQ_WDATA ))(*(out_DCACHE_REQ_WDATA )); |
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| 214 | |
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| 215 | (*(_Load_store_unit-> in_DCACHE_RSP_VAL ))(*( in_DCACHE_RSP_VAL )); |
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| 216 | (*(_Load_store_unit->out_DCACHE_RSP_ACK ))(*(out_DCACHE_RSP_ACK )); |
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| 217 | if (_param->_have_port_dcache_context_id) |
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| 218 | (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID)); |
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| 219 | (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID )); |
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| 220 | (*(_Load_store_unit-> in_DCACHE_RSP_RDATA ))(*( in_DCACHE_RSP_RDATA )); |
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| 221 | (*(_Load_store_unit-> in_DCACHE_RSP_ERROR ))(*( in_DCACHE_RSP_ERROR )); |
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| 222 | |
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| 223 | { |
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[78] | 224 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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[71] | 225 | { |
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| 226 | (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); |
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| 227 | if (_param->_have_port_ooo_engine_id) |
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| 228 | (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i])); |
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| 229 | (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))(*(out_BYPASS_MEMORY_NUM_REG [i])); |
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| 230 | (*(_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))(*(out_BYPASS_MEMORY_DATA [i])); |
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| 231 | } |
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| 232 | } |
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| 233 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 234 | Time * _time = new Time(); |
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| 235 | |
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| 236 | /******************************************************** |
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| 237 | * Simulation - Begin |
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| 238 | ********************************************************/ |
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| 239 | |
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| 240 | // Initialisation |
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| 241 | |
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| 242 | const uint32_t seed = 0; |
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| 243 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 244 | |
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| 245 | srand(seed); |
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| 246 | |
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| 247 | const int32_t percent_transaction_memory_out = 100; |
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| 248 | const int32_t percent_transaction_dcache = 100; |
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| 249 | const uint32_t miss_rate = 0; |
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| 250 | const uint32_t miss_penality = 0; |
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| 251 | |
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| 252 | uint32_t nb_request_memory_out=0; |
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| 253 | |
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| 254 | MemoryRequest_t tab_request [_param->_nb_packet]; |
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| 255 | priority_queue<MemoryRequest_t> fifo_request; |
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| 256 | |
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| 257 | const uint32_t size_memory = 0x100; |
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| 258 | // emulation of memory |
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| 259 | Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data); |
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| 260 | Cache_t * _cache = new Cache_t (miss_rate, miss_penality); |
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| 261 | |
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| 262 | SC_START(0); |
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| 263 | |
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| 264 | LABEL("Initialisation"); |
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| 265 | |
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| 266 | in_MEMORY_IN_VAL ->write(0); |
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| 267 | in_MEMORY_OUT_ACK->write(0); |
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| 268 | in_DCACHE_REQ_ACK->write(0); |
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| 269 | in_DCACHE_RSP_VAL->write(0); |
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| 270 | |
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| 271 | in_NRESET ->write(0); |
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| 272 | SC_START(5); |
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| 273 | in_NRESET ->write(5); |
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| 274 | |
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| 275 | LABEL("Loop of Test"); |
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| 276 | |
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| 277 | try |
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| 278 | { |
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| 279 | LABEL("Structure's initialisation"); |
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| 280 | |
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| 281 | bool store_queue_use [_param->_size_store_queue]; |
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| 282 | uint32_t nb_store_slot_use = 0; |
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| 283 | bool load_queue_use [_param->_size_load_queue ]; |
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| 284 | |
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| 285 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
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| 286 | store_queue_use [i] = false; |
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| 287 | for (uint32_t i=0; i<_param->_size_load_queue ; i++) |
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| 288 | load_queue_use [i] = false; |
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| 289 | |
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| 290 | |
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| 291 | //-------------------------------------------------------------------------------------------------------------- |
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| 292 | // c c f o p o t s l i d d w n w |
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| 293 | // y o r o a p y t o m a a r u r |
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| 294 | // c n o o c e p o a m t t i m i |
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| 295 | // l t n _ k r e r d e a a t _ t |
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| 296 | // e e t e e a e _ d _ _ e r e |
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| 297 | // x _ n t t _ p i r r _ _ _ |
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| 298 | // t e g _ i p t a a b r g s |
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| 299 | // _ n i i o t r t d _ p |
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| 300 | // i d n d n r _ r e |
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| 301 | // d _ e _ w d c |
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| 302 | // i _ w r _ |
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| 303 | // d i r i k |
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| 304 | // d i t o |
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| 305 | // t e |
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| 306 | // e |
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| 307 | // |
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| 308 | tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x10 ,0xdead1234,0,0,0); |
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| 309 | |
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| 310 | tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 311 | |
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| 312 | // READ 32b |
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| 313 | tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,1,0,0xdead1234); |
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| 314 | tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S ,TYPE_MEMORY,1,1,0x10 ,0x0 ,0x0 ,1,2,0,0xdead1234); |
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| 315 | |
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| 316 | // READ 16b |
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| 317 | tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,2,0x10 ,0x0 ,0x0 ,1,3,0,0x00001234); |
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| 318 | tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,3,0x12 ,0x0 ,0x0 ,1,4,0,0x0000dead); |
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| 319 | tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,5,0,0x00001234); |
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| 320 | tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,1,0x12 ,0x0 ,0x0 ,1,6,0,0xffffdead); |
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| 321 | |
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| 322 | // READ 8b |
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| 323 | tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,7,0,0x00000034); |
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| 324 | tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,8,0,0x00000012); |
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| 325 | tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,9,0,0x000000ad); |
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| 326 | tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,1,0,0x000000de); |
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| 327 | tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,2,0,0x00000034); |
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| 328 | tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,3,0,0x00000012); |
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| 329 | tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,4,0,0xffffffad); |
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| 330 | tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,5,0,0xffffffde); |
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| 331 | |
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| 332 | // STORE 16b |
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| 333 | tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x20 ,0x0 ,0xffffabcd,0,0,0); |
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| 334 | tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x22 ,0x0 ,0xffffdcba,0,0,0); |
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| 335 | tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 336 | tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 337 | tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x20 ,0x0 ,0x0 ,1,0,0,0xdcbaabcd); |
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| 338 | |
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| 339 | // STORE 8b and head / valid out order |
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| 340 | tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,3,0,0x1 ,0x4 ,0xffffff56,0,0,0); |
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| 341 | tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1 ,0x0 ,0x0 ,0,0,0); |
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| 342 | tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,0,0,0x0 ,0x4 ,0xffffff78,0,0,0); |
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| 343 | tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 344 | tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,1,0,0x3 ,0x4 ,0xffffff12,0,0,0); |
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| 345 | tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 346 | tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x2 ,0x4 ,0xffffff34,0,0,0); |
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| 347 | tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 348 | tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x2 ,0x2 ,0x0 ,1,0,0,0x12345678); |
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| 349 | |
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| 350 | // CHECK - with a store not present, store format is >= |
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| 351 | tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x30 ,0x21071981,0,0,0); |
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| 352 | tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 353 | tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x30 ,0x0 ,1,0,0,0x21071981); |
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| 354 | tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,3,0x0 ,0x30 ,0x0 ,1,0,0,0x00001981); |
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| 355 | tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,0,0x0 ,0x32 ,0x0 ,1,0,0,0x00002107); |
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| 356 | tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,0,1,0x0 ,0x31 ,0x0 ,1,0,0,0x00000019); |
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| 357 | |
---|
| 358 | // CHECK - with a store not present, multiple store and format is different |
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| 359 | tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x40 ,0xffffffff,0,0,0); |
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| 360 | tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 361 | tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x0 ,0x42 ,0xbaba ,0,0,0); |
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| 362 | tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 363 | tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x0 ,0x42 ,0xbe ,0,0,0); |
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| 364 | tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 365 | tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0xf00d ,0,0,0); |
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| 366 | tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 367 | tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x40 ,0x0 ,1,0,0,0xbabef00d); |
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| 368 | tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,2,3,0x0 ,0x40 ,0x0 ,1,0,0,0xbabaffff); |
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| 369 | tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0x0 ,1,0,0,0xbabeffff); |
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| 370 | tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,3,1,0x0 ,0x42 ,0x0 ,1,0,0,0xffffffbe); |
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| 371 | |
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| 372 | |
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| 373 | // CHECK - with different ooo_engine_id |
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| 374 | tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x0 ,0xdad1900d,0,0,0); |
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| 375 | tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 376 | tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x55508570,0,0,0); |
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| 377 | tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 378 | |
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| 379 | |
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| 380 | tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,2,0x0 ,0x2 ,0x0 ,1,0,0,0xffffdad1); |
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| 381 | tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,3,0x0 ,0x0 ,0x0 ,1,0,0,0xffff8570); |
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| 382 | |
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| 383 | |
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| 384 | // with a little exception |
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| 385 | tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x0 ,0x0 ,0xffff6996,0,0,1); |
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| 386 | tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 387 | tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use) |
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| 388 | tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // the memory have not change |
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| 389 | |
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| 390 | |
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| 391 | // multiple event |
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| 392 | // * store : miss_spec and aligment, priority : miss_spec > aligment |
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| 393 | // * load : miss_spec and aligment, priority : miss_spec > aligment |
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| 394 | tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,0,0,1); |
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| 395 | tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 396 | |
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| 397 | tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x0 ,0x0 ,1,0,0,0xdad1900d); |
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| 398 | tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,3,0x0 ,0x3 ,0x0 ,1,0,0); // miss_spec and alignment |
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| 399 | tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,1,0,0); // bus error and alignement |
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| 400 | tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,1,0x0 ,size_memory+1,0x0 ,1,0,0); // bus error and alignement |
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| 401 | |
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| 402 | |
---|
| 403 | |
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| 404 | tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,0,0,0); // bus error |
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| 405 | tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0); |
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| 406 | tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp |
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| 407 | |
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| 408 | const uint32_t nb_request = 64;//_param->_nb_packet; |
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| 409 | |
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| 410 | for (uint32_t i=0; i<nb_request; i++) |
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| 411 | { |
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| 412 | std::cout << tab_request [i] << std::endl; |
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| 413 | fifo_request.push(tab_request [i]); |
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| 414 | } |
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| 415 | LABEL("Simulation ..."); |
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| 416 | |
---|
| 417 | while (nb_request_memory_out < nb_request) |
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| 418 | { |
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| 419 | cout << "*********************************************" << endl; |
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| 420 | cout << "Dump STORE_QUEUE_USE : " << endl; |
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| 421 | cout << " use " << nb_store_slot_use << endl; |
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| 422 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
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| 423 | cout << " [" << i << "] " << store_queue_use [i] << endl; |
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| 424 | cout << "Dump LOAD_QUEUE_USE : " << endl; |
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| 425 | for (uint32_t i=0; i<_param->_size_load_queue ; i++) |
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| 426 | cout << " [" << i << "] " << load_queue_use [i] << endl; |
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| 427 | cout << "*********************************************" << endl; |
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| 428 | |
---|
| 429 | |
---|
| 430 | // ***** MEMORY_IN ***** |
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| 431 | |
---|
| 432 | // memory_in_val depends of three factors : |
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| 433 | // 1) request's fifo is not empty ? |
---|
| 434 | // 2) the slot destination is free ? |
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| 435 | // 3) The head of request's fifo can be issue : the number of cycle is more than current cycle |
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| 436 | |
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| 437 | bool can_execute = false; |
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| 438 | |
---|
| 439 | if (not fifo_request.empty()) |
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| 440 | { |
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| 441 | can_execute = sc_simulation_time() >= fifo_request.top()._cycle; |
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| 442 | if (is_operation_memory_store(fifo_request.top()._operation)) |
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| 443 | can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation); |
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| 444 | else |
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| 445 | can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write]; |
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| 446 | } |
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| 447 | in_MEMORY_IN_VAL ->write(can_execute); |
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| 448 | |
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| 449 | if (not fifo_request.empty()) |
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| 450 | { |
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| 451 | if (_param->_have_port_context_id) |
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| 452 | in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id ); |
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| 453 | if (_param->_have_port_front_end_id) |
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| 454 | in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id ); |
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| 455 | if (_param->_have_port_ooo_engine_id) |
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| 456 | in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id ); |
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| 457 | if (_param->_have_port_packet_id) |
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| 458 | in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id ); |
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| 459 | in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation ); |
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| 460 | in_MEMORY_IN_TYPE ->write (fifo_request.top()._type ); |
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| 461 | in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write); |
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[78] | 462 | if (_param->_have_port_load_queue_ptr) |
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[71] | 463 | in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write ); |
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| 464 | in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat ); |
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| 465 | in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra ); |
---|
| 466 | in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb ); |
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| 467 | // in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd ); |
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| 468 | in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd ); |
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| 469 | } |
---|
| 470 | in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out); |
---|
| 471 | |
---|
| 472 | // ***** DCACHE_REQ ***** |
---|
| 473 | in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache); |
---|
| 474 | |
---|
| 475 | // ***** DCACHE_RSP ***** |
---|
| 476 | bool have_rsp = _cache->have_rsp (); |
---|
| 477 | in_DCACHE_RSP_VAL->write(have_rsp); |
---|
| 478 | |
---|
| 479 | if (have_rsp) |
---|
| 480 | { |
---|
| 481 | in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id); |
---|
| 482 | in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id ); |
---|
| 483 | in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata ); |
---|
| 484 | in_DCACHE_RSP_ERROR ->write(_cache->front()._error ); |
---|
| 485 | } |
---|
| 486 | |
---|
| 487 | SC_START(0); |
---|
| 488 | |
---|
| 489 | LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read())); |
---|
| 490 | if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read()) |
---|
| 491 | { |
---|
| 492 | Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID->read(); |
---|
| 493 | |
---|
| 494 | LABEL(" * Accepted MEMORY_IN : " + toString(packet_id)); |
---|
| 495 | cout << fifo_request.top(); |
---|
| 496 | |
---|
| 497 | if (is_operation_memory_store(fifo_request.top()._operation)) |
---|
| 498 | { |
---|
| 499 | if (not is_operation_memory_store_head(fifo_request.top()._operation)) |
---|
| 500 | { |
---|
| 501 | store_queue_use [fifo_request.top()._store_queue_ptr_write] = true; |
---|
| 502 | nb_store_slot_use ++; |
---|
| 503 | } |
---|
| 504 | } |
---|
| 505 | else |
---|
| 506 | load_queue_use [fifo_request.top()._load_queue_ptr_write] = true; |
---|
| 507 | |
---|
| 508 | fifo_request.pop(); |
---|
| 509 | } |
---|
| 510 | |
---|
| 511 | LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read())); |
---|
| 512 | if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read()) |
---|
| 513 | { |
---|
| 514 | Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read(); |
---|
| 515 | |
---|
| 516 | LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id)); |
---|
| 517 | |
---|
| 518 | if (is_operation_memory_store(tab_request[packet_id]._operation)) |
---|
| 519 | { |
---|
| 520 | store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false; |
---|
| 521 | nb_store_slot_use --; |
---|
| 522 | nb_request_memory_out +=2; |
---|
| 523 | |
---|
| 524 | } |
---|
| 525 | else |
---|
| 526 | { |
---|
| 527 | if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) |
---|
| 528 | { |
---|
| 529 | nb_request_memory_out ++; |
---|
| 530 | |
---|
| 531 | load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false; |
---|
| 532 | } |
---|
| 533 | else |
---|
| 534 | { |
---|
| 535 | std::cout << "seth - have a load_speculative." << std::endl; |
---|
| 536 | tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait); |
---|
| 537 | tab_request[packet_id]._previous_load_speculative = 1; |
---|
| 538 | } |
---|
| 539 | } |
---|
| 540 | |
---|
| 541 | std::cout << "kane - nb_request_memory_out : " << nb_request_memory_out << std::endl; |
---|
| 542 | |
---|
| 543 | // a lot of test |
---|
| 544 | TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id ); |
---|
| 545 | TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id ); |
---|
| 546 | TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id ); |
---|
| 547 | TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id); |
---|
[78] | 548 | // TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation ); |
---|
| 549 | TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY ); |
---|
[71] | 550 | |
---|
| 551 | if (is_operation_memory_load (tab_request[packet_id]._operation)) |
---|
| 552 | { |
---|
| 553 | TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd ); |
---|
| 554 | } |
---|
| 555 | |
---|
| 556 | Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat; |
---|
| 557 | |
---|
| 558 | bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation)))); |
---|
| 559 | bool berr = (address >= size_memory); |
---|
| 560 | Texception_t exception = out_MEMORY_OUT_EXCEPTION->read(); |
---|
| 561 | |
---|
| 562 | if (is_operation_memory_store(tab_request[packet_id]._operation)) |
---|
| 563 | { |
---|
| 564 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 0); |
---|
| 565 | |
---|
| 566 | // store. |
---|
| 567 | // prioritary : miss_speculation > aligmnent > DBERR |
---|
| 568 | |
---|
| 569 | bool test_result_ko = false; |
---|
| 570 | |
---|
| 571 | if (tab_request[packet_id]._write_spec_ko) |
---|
| 572 | { |
---|
| 573 | TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
| 574 | } |
---|
| 575 | else |
---|
| 576 | if (error_alignment) |
---|
| 577 | { |
---|
| 578 | TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT); |
---|
| 579 | test_result_ko = true; |
---|
| 580 | } |
---|
| 581 | else |
---|
| 582 | if (berr) |
---|
| 583 | { |
---|
| 584 | // TODO NOT SUPPORTED |
---|
| 585 | // TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR); |
---|
| 586 | |
---|
| 587 | //test_result_ko = true; |
---|
| 588 | } |
---|
| 589 | else |
---|
| 590 | { |
---|
| 591 | TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE); |
---|
| 592 | } |
---|
| 593 | // In all case : test data |
---|
| 594 | if (test_result_ko) |
---|
| 595 | { |
---|
| 596 | TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address); |
---|
| 597 | } |
---|
| 598 | } |
---|
| 599 | else |
---|
| 600 | { |
---|
| 601 | // load |
---|
| 602 | // prioritary : miss_speculation > aligmnent > DBERR |
---|
| 603 | |
---|
| 604 | bool is_load = is_operation_memory_load(tab_request[packet_id]._operation); |
---|
| 605 | |
---|
| 606 | if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) |
---|
| 607 | { |
---|
| 608 | bool test_result_ko = false; |
---|
| 609 | |
---|
| 610 | if (tab_request[packet_id]._write_spec_ko) |
---|
| 611 | { |
---|
| 612 | // IS A LOAD :D |
---|
| 613 | TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
| 614 | TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1); |
---|
| 615 | } |
---|
| 616 | else |
---|
| 617 | if (error_alignment) |
---|
| 618 | { |
---|
| 619 | TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT); |
---|
| 620 | TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load); |
---|
| 621 | test_result_ko = true; |
---|
| 622 | } |
---|
| 623 | else |
---|
| 624 | if (berr) |
---|
| 625 | { |
---|
| 626 | TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR); |
---|
| 627 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load); |
---|
| 628 | test_result_ko = true; |
---|
| 629 | } |
---|
| 630 | else |
---|
| 631 | { |
---|
| 632 | TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE); |
---|
| 633 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative); |
---|
| 634 | } |
---|
| 635 | // In all case : test data |
---|
| 636 | if (test_result_ko) |
---|
| 637 | { |
---|
| 638 | TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address); |
---|
| 639 | } |
---|
| 640 | else |
---|
| 641 | { |
---|
| 642 | TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait); |
---|
| 643 | } |
---|
| 644 | } |
---|
| 645 | else |
---|
| 646 | { |
---|
| 647 | TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 1); |
---|
| 648 | } |
---|
| 649 | } |
---|
| 650 | } |
---|
| 651 | |
---|
| 652 | LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read())); |
---|
| 653 | if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read()) |
---|
| 654 | { |
---|
| 655 | Tcontext_t context_id; |
---|
| 656 | Tpacket_t packet_id ; |
---|
| 657 | Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read(); |
---|
| 658 | Tdcache_data_t rdata; |
---|
| 659 | Tdcache_error_t error = 0; |
---|
| 660 | if (_param->_have_port_dcache_context_id) |
---|
| 661 | context_id = out_DCACHE_REQ_CONTEXT_ID->read(); |
---|
| 662 | else |
---|
| 663 | context_id = 0; |
---|
| 664 | |
---|
| 665 | packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1; |
---|
| 666 | |
---|
| 667 | LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id)); |
---|
| 668 | |
---|
| 669 | if (address >= size_memory) |
---|
| 670 | { |
---|
| 671 | // Bus error |
---|
[72] | 672 | error = DCACHE_ERROR_BUS_ERROR; |
---|
[71] | 673 | rdata = address; // convention : cache return the address fautive ! |
---|
| 674 | } |
---|
| 675 | else |
---|
| 676 | { |
---|
| 677 | rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read()); |
---|
| 678 | LABEL(" * rdata : " + toString(rdata)); |
---|
| 679 | } |
---|
| 680 | |
---|
| 681 | // test type : send or not a respons ! |
---|
[72] | 682 | if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or |
---|
[81] | 683 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_8 ) or |
---|
| 684 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_16) or |
---|
| 685 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_32) or |
---|
| 686 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_64) or |
---|
[72] | 687 | ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_8 ) or |
---|
| 688 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_16) or |
---|
| 689 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_32) or |
---|
| 690 | (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_64) ))) |
---|
[71] | 691 | { |
---|
| 692 | LABEL(" * have_dcache_rsp"); |
---|
| 693 | |
---|
| 694 | _cache->push (context_id, |
---|
| 695 | out_DCACHE_REQ_PACKET_ID ->read(), |
---|
| 696 | rdata, |
---|
| 697 | error); |
---|
| 698 | } |
---|
| 699 | } |
---|
| 700 | |
---|
| 701 | LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read())); |
---|
| 702 | if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read()) |
---|
| 703 | { |
---|
| 704 | _cache->pop(); |
---|
| 705 | } |
---|
| 706 | |
---|
| 707 | _cache->end_cycle(); |
---|
| 708 | |
---|
| 709 | SC_START(1); |
---|
| 710 | } |
---|
| 711 | } |
---|
| 712 | catch (morpheo::ErrorMorpheo & error) |
---|
| 713 | { |
---|
| 714 | _memory->trace(); |
---|
| 715 | throw (error); |
---|
| 716 | } |
---|
| 717 | |
---|
| 718 | _memory->trace(); |
---|
| 719 | |
---|
| 720 | |
---|
| 721 | /******************************************************** |
---|
| 722 | * Simulation - End |
---|
| 723 | ********************************************************/ |
---|
| 724 | |
---|
| 725 | TEST_OK ("End of Simulation"); |
---|
| 726 | delete _time; |
---|
| 727 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
---|
| 728 | |
---|
| 729 | delete in_CLOCK; |
---|
| 730 | delete in_NRESET; |
---|
| 731 | |
---|
| 732 | delete in_MEMORY_IN_VAL ; |
---|
| 733 | delete out_MEMORY_IN_ACK ; |
---|
| 734 | delete in_MEMORY_IN_CONTEXT_ID ; |
---|
| 735 | delete in_MEMORY_IN_FRONT_END_ID ; |
---|
| 736 | delete in_MEMORY_IN_OOO_ENGINE_ID ; |
---|
| 737 | delete in_MEMORY_IN_PACKET_ID ; |
---|
| 738 | delete in_MEMORY_IN_OPERATION ; |
---|
| 739 | delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; |
---|
| 740 | delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; |
---|
[78] | 741 | delete in_MEMORY_IN_HAS_IMMEDIAT; |
---|
[71] | 742 | delete in_MEMORY_IN_IMMEDIAT ; |
---|
| 743 | delete in_MEMORY_IN_DATA_RA ; |
---|
| 744 | delete in_MEMORY_IN_DATA_RB ; |
---|
[78] | 745 | delete in_MEMORY_IN_DATA_RC ; |
---|
| 746 | delete in_MEMORY_IN_WRITE_RD ; |
---|
[71] | 747 | delete in_MEMORY_IN_NUM_REG_RD ; |
---|
[78] | 748 | delete in_MEMORY_IN_WRITE_RE ; |
---|
| 749 | delete in_MEMORY_IN_NUM_REG_RE ; |
---|
[71] | 750 | |
---|
| 751 | delete out_MEMORY_OUT_VAL ; |
---|
| 752 | delete in_MEMORY_OUT_ACK ; |
---|
| 753 | delete out_MEMORY_OUT_CONTEXT_ID; |
---|
| 754 | delete out_MEMORY_OUT_FRONT_END_ID; |
---|
| 755 | delete out_MEMORY_OUT_OOO_ENGINE_ID; |
---|
| 756 | delete out_MEMORY_OUT_PACKET_ID ; |
---|
[78] | 757 | // delete out_MEMORY_OUT_OPERATION ; |
---|
| 758 | delete out_MEMORY_OUT_TYPE ; |
---|
[71] | 759 | delete out_MEMORY_OUT_WRITE_RD ; |
---|
| 760 | delete out_MEMORY_OUT_NUM_REG_RD; |
---|
| 761 | delete out_MEMORY_OUT_DATA_RD ; |
---|
[78] | 762 | delete out_MEMORY_OUT_WRITE_RE ; |
---|
| 763 | delete out_MEMORY_OUT_NUM_REG_RE; |
---|
| 764 | delete out_MEMORY_OUT_DATA_RE ; |
---|
[71] | 765 | delete out_MEMORY_OUT_EXCEPTION ; |
---|
[78] | 766 | delete out_MEMORY_OUT_NO_SEQUENCE; |
---|
| 767 | delete out_MEMORY_OUT_ADDRESS ; |
---|
[71] | 768 | |
---|
| 769 | delete out_DCACHE_REQ_VAL ; |
---|
| 770 | delete in_DCACHE_REQ_ACK ; |
---|
| 771 | delete out_DCACHE_REQ_CONTEXT_ID; |
---|
| 772 | delete out_DCACHE_REQ_PACKET_ID ; |
---|
| 773 | delete out_DCACHE_REQ_ADDRESS ; |
---|
| 774 | delete out_DCACHE_REQ_TYPE ; |
---|
| 775 | delete out_DCACHE_REQ_WDATA ; |
---|
| 776 | |
---|
| 777 | delete in_DCACHE_RSP_VAL ; |
---|
| 778 | delete out_DCACHE_RSP_ACK ; |
---|
| 779 | delete in_DCACHE_RSP_CONTEXT_ID; |
---|
| 780 | delete in_DCACHE_RSP_PACKET_ID ; |
---|
| 781 | delete in_DCACHE_RSP_RDATA ; |
---|
| 782 | delete in_DCACHE_RSP_ERROR ; |
---|
| 783 | |
---|
| 784 | { |
---|
| 785 | delete [] out_BYPASS_MEMORY_VAL ; |
---|
| 786 | delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; |
---|
| 787 | delete [] out_BYPASS_MEMORY_NUM_REG ; |
---|
| 788 | delete [] out_BYPASS_MEMORY_DATA ; |
---|
| 789 | } |
---|
| 790 | #endif |
---|
| 791 | |
---|
| 792 | delete _Load_store_unit; |
---|
| 793 | delete _memory; |
---|
| 794 | delete _cache; |
---|
| 795 | #ifdef STATISTICS |
---|
| 796 | delete _parameters_statistics; |
---|
| 797 | #endif |
---|
| 798 | delete _param; |
---|
| 799 | } |
---|