[59] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Load_store_unit_function_speculative_load_commit_transition.cpp 118 2009-05-20 22:01:32Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_execute_loop { |
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| 15 | namespace execute_loop { |
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| 16 | namespace multi_execute_unit { |
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| 17 | namespace execute_unit { |
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| 18 | namespace load_store_unit { |
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| 19 | |
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[106] | 20 | template <typename T> |
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| 21 | T swapBytes (T data, uint32_t size_data, uint32_t size_access) |
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| 22 | { |
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| 23 | uint64_t x = static_cast<uint64_t>(data); |
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[59] | 24 | |
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[106] | 25 | // switch (size_data) |
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| 26 | // { |
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| 27 | // case 2 : // 16 bits |
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| 28 | // { |
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| 29 | // switch (size_access) |
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| 30 | // { |
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| 31 | // case 2 : |
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| 32 | // { |
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| 33 | // x = ((((x>> 8)&0xff) << 0) | |
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| 34 | // (((x>> 0)&0xff) << 8) ); |
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| 35 | // break; |
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| 36 | // } |
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| 37 | // default : |
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| 38 | // { |
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| 39 | // break; |
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| 40 | // } |
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| 41 | // } |
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| 42 | // break; |
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| 43 | // } |
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| 44 | // case 4 : // 32 bits |
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| 45 | // { |
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| 46 | // switch (size_access) |
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| 47 | // { |
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| 48 | // case 2 : |
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| 49 | // { |
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| 50 | // x = ((((x>> 8)&0xff) << 0) | |
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| 51 | // (((x>> 0)&0xff) << 8) | |
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| 52 | // (((x>>24)&0xff) << 16) | |
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| 53 | // (((x>>16)&0xff) << 24) ); |
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| 54 | // break; |
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| 55 | // } |
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| 56 | // case 4 : |
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| 57 | // { |
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| 58 | // x = ((((x>>24)&0xff) << 0) | |
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| 59 | // (((x>>16)&0xff) << 8) | |
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| 60 | // (((x>> 8)&0xff) << 16) | |
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| 61 | // (((x>> 0)&0xff) << 24) ); |
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| 62 | // break; |
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| 63 | // } |
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| 64 | // default : |
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| 65 | // { |
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| 66 | // break; |
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| 67 | // } |
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| 68 | // } |
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| 69 | // break; |
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| 70 | // } |
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| 71 | // case 8 : // 64 bits |
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| 72 | // { |
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| 73 | // switch (size_access) |
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| 74 | // { |
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| 75 | // case 2 : |
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| 76 | // { |
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| 77 | // x = ((((x>> 8)&0xff) << 0) | |
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| 78 | // (((x>> 0)&0xff) << 8) | |
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| 79 | // (((x>>24)&0xff) << 16) | |
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| 80 | // (((x>>16)&0xff) << 24) | |
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| 81 | // (((x>>40)&0xff) << 32) | |
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| 82 | // (((x>>32)&0xff) << 40) | |
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| 83 | // (((x>>56)&0xff) << 48) | |
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| 84 | // (((x>>48)&0xff) << 56) ); |
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| 85 | // break; |
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| 86 | // } |
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| 87 | // case 4 : |
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| 88 | // { |
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| 89 | // x = ((((x>>24)&0xff) << 0) | |
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| 90 | // (((x>>16)&0xff) << 8) | |
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| 91 | // (((x>> 8)&0xff) << 16) | |
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| 92 | // (((x>> 0)&0xff) << 24) | |
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| 93 | // (((x>>56)&0xff) << 32) | |
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| 94 | // (((x>>48)&0xff) << 40) | |
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| 95 | // (((x>>40)&0xff) << 48) | |
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| 96 | // (((x>>32)&0xff) << 56) ); |
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| 97 | // break; |
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| 98 | // } |
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| 99 | // case 8 : |
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| 100 | // { |
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| 101 | // x = ((((x>>56)&0xff) << 0) | |
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| 102 | // (((x>>48)&0xff) << 8) | |
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| 103 | // (((x>>40)&0xff) << 16) | |
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| 104 | // (((x>>32)&0xff) << 24) | |
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| 105 | // (((x>>24)&0xff) << 32) | |
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| 106 | // (((x>>16)&0xff) << 40) | |
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| 107 | // (((x>> 8)&0xff) << 48) | |
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| 108 | // (((x>> 0)&0xff) << 56) ); |
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| 109 | // break; |
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| 110 | // } |
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| 111 | // default : |
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| 112 | // { |
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| 113 | // break; |
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| 114 | // } |
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| 115 | // } |
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| 116 | // break; |
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| 117 | // } |
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| 118 | // default : |
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| 119 | // { |
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| 120 | // break; |
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| 121 | // } |
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| 122 | // } |
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| 123 | |
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| 124 | |
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| 125 | uint64_t y=0; |
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| 126 | |
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| 127 | for (uint32_t i=0; i<size_data; i+=size_access) |
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| 128 | { |
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| 129 | uint32_t offset = i<<3; |
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| 130 | |
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| 131 | switch (size_access) |
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| 132 | { |
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| 133 | case 1 : |
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| 134 | { |
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| 135 | y = x; |
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| 136 | break; |
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| 137 | } |
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| 138 | case 2 : |
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| 139 | { |
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| 140 | y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) | |
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| 141 | (((x>>( 0+offset))&0xff) << ( 8+offset)) ); |
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| 142 | break; |
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| 143 | } |
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| 144 | case 4 : |
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| 145 | { |
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| 146 | y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) | |
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| 147 | (((x>>(16+offset))&0xff) << ( 8+offset)) | |
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| 148 | (((x>>( 8+offset))&0xff) << (16+offset)) | |
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| 149 | (((x>>( 0+offset))&0xff) << (24+offset)) ); |
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| 150 | break; |
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| 151 | } |
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| 152 | case 8 : |
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| 153 | { |
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| 154 | y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) | |
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| 155 | (((x>>(48+offset))&0xff) << ( 8+offset)) | |
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| 156 | (((x>>(40+offset))&0xff) << (16+offset)) | |
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| 157 | (((x>>(32+offset))&0xff) << (24+offset)) | |
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| 158 | (((x>>(24+offset))&0xff) << (32+offset)) | |
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| 159 | (((x>>(16+offset))&0xff) << (40+offset)) | |
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| 160 | (((x>>( 8+offset))&0xff) << (48+offset)) | |
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| 161 | (((x>>( 0+offset))&0xff) << (56+offset)) ); |
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| 162 | break; |
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| 163 | } |
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| 164 | default : |
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| 165 | { |
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| 166 | break; |
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| 167 | } |
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| 168 | } |
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| 169 | } |
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| 170 | |
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| 171 | return static_cast<T>(y); |
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| 172 | } |
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| 173 | |
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| 174 | template <typename T> |
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| 175 | T swapBits (T data, uint32_t size_data, uint32_t size_access) |
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| 176 | { |
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| 177 | uint8_t x = static_cast<uint8_t>(data); |
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| 178 | |
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| 179 | uint8_t y=0; |
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| 180 | |
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| 181 | for (uint32_t i=0; i<size_data; i+=size_access) |
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| 182 | { |
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| 183 | uint32_t offset = i; |
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| 184 | |
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| 185 | switch (size_access) |
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| 186 | { |
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| 187 | case 1 : |
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| 188 | { |
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| 189 | y = x; |
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| 190 | break; |
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| 191 | } |
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| 192 | case 2 : |
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| 193 | { |
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| 194 | y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) | |
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| 195 | (((x>>( 0+offset))&0x1) << ( 1+offset)) ); |
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| 196 | break; |
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| 197 | } |
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| 198 | case 4 : |
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| 199 | { |
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| 200 | y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) | |
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| 201 | (((x>>( 2+offset))&0x1) << ( 1+offset)) | |
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| 202 | (((x>>( 1+offset))&0x1) << ( 2+offset)) | |
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| 203 | (((x>>( 0+offset))&0x1) << ( 3+offset)) ); |
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| 204 | break; |
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| 205 | } |
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| 206 | case 8 : |
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| 207 | { |
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| 208 | y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) | |
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| 209 | (((x>>( 6+offset))&0x1) << ( 1+offset)) | |
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| 210 | (((x>>( 5+offset))&0x1) << ( 2+offset)) | |
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| 211 | (((x>>( 4+offset))&0x1) << ( 3+offset)) | |
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| 212 | (((x>>( 3+offset))&0x1) << ( 4+offset)) | |
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| 213 | (((x>>( 2+offset))&0x1) << ( 5+offset)) | |
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| 214 | (((x>>( 1+offset))&0x1) << ( 6+offset)) | |
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| 215 | (((x>>( 0+offset))&0x1) << ( 7+offset)) ); |
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| 216 | break; |
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| 217 | } |
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| 218 | default : |
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| 219 | { |
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| 220 | break; |
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| 221 | } |
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| 222 | } |
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| 223 | } |
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| 224 | |
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| 225 | return static_cast<T>(y); |
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| 226 | } |
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| 227 | |
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[59] | 228 | #undef FUNCTION |
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| 229 | #define FUNCTION "Load_store_unit::function_speculative_load_commit_transition" |
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| 230 | void Load_store_unit::function_speculative_load_commit_transition (void) |
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| 231 | { |
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[97] | 232 | log_begin(Load_store_unit,FUNCTION); |
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| 233 | log_function(Load_store_unit,FUNCTION,_name.c_str()); |
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[59] | 234 | |
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| 235 | if (PORT_READ(in_NRESET) == 0) |
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| 236 | { |
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| 237 | // Reset : clear all queue |
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| 238 | _speculative_access_queue_control->clear(); |
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| 239 | |
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[71] | 240 | reg_STORE_QUEUE_PTR_READ = 0; |
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| 241 | reg_LOAD_QUEUE_CHECK_PRIORITY = 0; |
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| 242 | |
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[59] | 243 | for (uint32_t i=0; i< _param->_size_store_queue ; i++) |
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[117] | 244 | { |
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| 245 | reg_STORE_QUEUE_NB_CHECK [i] = 0; |
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[59] | 246 | _store_queue [i]._state = STORE_QUEUE_EMPTY; |
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[117] | 247 | } |
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[59] | 248 | |
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| 249 | for (uint32_t i=0; i< _param->_size_load_queue ; i++) |
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| 250 | _load_queue [i]._state = LOAD_QUEUE_EMPTY; |
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| 251 | |
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| 252 | for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++) |
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| 253 | _speculative_access_queue [i]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; |
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| 254 | } |
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| 255 | else |
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| 256 | { |
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| 257 | //================================================================ |
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[117] | 258 | // Interface "MEMORY_OUT" |
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| 259 | //================================================================ |
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| 260 | |
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| 261 | if (( internal_MEMORY_OUT_VAL == 1) and |
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| 262 | (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) |
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| 263 | { |
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| 264 | log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction"); |
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| 265 | |
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| 266 | switch (internal_MEMORY_OUT_SELECT_QUEUE) |
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| 267 | { |
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| 268 | case SELECT_STORE_QUEUE : |
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| 269 | { |
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| 270 | // ======================= |
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| 271 | // ===== STORE_QUEUE ===== |
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| 272 | // ======================= |
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| 273 | |
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| 274 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); |
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| 275 | |
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| 276 | // Entry flush and increase the read pointer |
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| 277 | _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY; |
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| 278 | |
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| 279 | reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; |
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| 280 | |
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| 281 | break; |
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| 282 | } |
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| 283 | case SELECT_LOAD_QUEUE : |
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| 284 | { |
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| 285 | // ====================== |
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| 286 | // ===== LOAD_QUEUE ===== |
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| 287 | // ====================== |
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| 288 | |
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| 289 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); |
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| 290 | |
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| 291 | // Entry flush and increase the read pointer |
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| 292 | |
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| 293 | _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY; |
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| 294 | |
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| 295 | // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue; |
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| 296 | |
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| 297 | break; |
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| 298 | } |
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| 299 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
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| 300 | { |
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| 301 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); |
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| 302 | |
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| 303 | // !!! WARNING !!! |
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| 304 | // !!! Test special case : |
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| 305 | // !!! in a cycle an instruction can check the last store AND commit instruction |
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| 306 | // !!! also the memory_out is before the port_check |
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| 307 | |
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| 308 | _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; |
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| 309 | // NOTE : a speculative load write in the register file. |
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| 310 | // if the speculation is a miss, write_rd is re set at 1. |
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| 311 | _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0; |
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| 312 | |
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| 313 | #ifdef STATISTICS |
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| 314 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 315 | (*_stat_nb_inst_load_commit_speculative) ++; |
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| 316 | #endif |
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| 317 | |
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| 318 | break; |
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| 319 | } |
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| 320 | |
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| 321 | break; |
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| 322 | } |
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| 323 | } |
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| 324 | |
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| 325 | //================================================================ |
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[71] | 326 | // Interface "PORT_CHECK" |
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| 327 | //================================================================ |
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| 328 | |
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| 329 | // Plusieurs moyens de faire la verification de dépendance entre les loads et les stores. |
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| 330 | // 1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue |
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| 331 | // 2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier. |
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| 332 | |
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| 333 | // solution 1) |
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[97] | 334 | log_printf(TRACE,Load_store_unit,FUNCTION," * CHECK"); |
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[71] | 335 | for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++) |
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| 336 | { |
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[104] | 337 | // Get an index from load queue |
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[71] | 338 | uint32_t index_load = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue; |
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[104] | 339 | |
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| 340 | // Test if this load must ckecked store queue |
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| 341 | if (((_load_queue[index_load]._state == LOAD_QUEUE_WAIT_CHECK) or |
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[71] | 342 | (_load_queue[index_load]._state == LOAD_QUEUE_COMMIT_CHECK) or |
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| 343 | (_load_queue[index_load]._state == LOAD_QUEUE_CHECK)) and |
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| 344 | is_operation_memory_load(_load_queue[index_load]._operation)) |
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| 345 | { |
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[97] | 346 | log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load); |
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[71] | 347 | |
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| 348 | nb_check++; // use one port |
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| 349 | |
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| 350 | // find a entry that it need a check |
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[117] | 351 | Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; |
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[118] | 352 | // Tlsq_ptr_t index_store_old = index_store; |
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[117] | 353 | |
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[104] | 354 | // Init variable |
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[71] | 355 | bool end_check = false; |
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| 356 | bool change_state = false; |
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| 357 | bool next = false; |
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| 358 | |
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| 359 | // At the first store queue empty, stop check. |
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| 360 | // Explication : |
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| 361 | // * rename logic keep a empty case in the store queue (also size_store_queue > 1) |
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| 362 | // * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load. |
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| 363 | |
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| 364 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); |
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[106] | 365 | log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); |
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| 366 | |
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[71] | 367 | if (index_store == reg_STORE_QUEUE_PTR_READ) |
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| 368 | { |
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| 369 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store == reg_STORE_QUEUE_PTR_READ"); |
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| 370 | end_check = true; |
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| 371 | change_state = true; |
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| 372 | } |
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| 373 | else |
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| 374 | { |
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| 375 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store != reg_STORE_QUEUE_PTR_READ"); |
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| 376 | |
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| 377 | index_store = (index_store-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming |
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| 378 | |
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| 379 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); |
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| 380 | |
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[104] | 381 | // switch on store_queue state |
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[71] | 382 | switch (_store_queue[index_store]._state) |
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| 383 | { |
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| 384 | case STORE_QUEUE_VALID_NO_SPECULATIVE : |
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| 385 | case STORE_QUEUE_COMMIT : |
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| 386 | case STORE_QUEUE_VALID_SPECULATIVE : |
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| 387 | { |
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| 388 | |
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| 389 | log_printf(TRACE,Load_store_unit,FUNCTION," * store have a valid entry"); |
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| 390 | |
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| 391 | // TODO : MMU - nous considérons que les adresses sont physique |
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| 392 | bool test_thread_id = true; |
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| 393 | |
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[104] | 394 | // Test thread id |
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[71] | 395 | if (_param->_have_port_context_id) |
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| 396 | test_thread_id &= (_load_queue[index_load]._context_id == _store_queue[index_store]._context_id); |
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| 397 | if (_param->_have_port_front_end_id) |
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| 398 | test_thread_id &= (_load_queue[index_load]._front_end_id == _store_queue[index_store]._front_end_id); |
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| 399 | if (_param->_have_port_ooo_engine_id) |
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| 400 | test_thread_id &= (_load_queue[index_load]._ooo_engine_id == _store_queue[index_store]._ooo_engine_id); |
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| 401 | |
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| 402 | if (test_thread_id) |
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| 403 | { |
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[104] | 404 | // the load and store are in the same thread. Now, we must test address. |
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| 405 | |
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[71] | 406 | log_printf(TRACE,Load_store_unit,FUNCTION," * load and store is the same thread."); |
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| 407 | Tdcache_address_t load_addr = _load_queue [index_load ]._address; |
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| 408 | Tdcache_address_t store_addr = _store_queue[index_store]._address; |
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| 409 | |
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| 410 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr : %.8x.",load_addr ); |
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| 411 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr : %.8x.",store_addr); |
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| 412 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr & mask_address_msb : %.8x.",load_addr & _param->_mask_address_msb); |
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| 413 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb); |
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[104] | 414 | // Test if the both address target the same "word" |
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[71] | 415 | if ((load_addr & _param->_mask_address_msb) == |
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| 416 | (store_addr & _param->_mask_address_msb)) |
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| 417 | { |
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| 418 | log_printf(TRACE,Load_store_unit,FUNCTION," * address_msb is the same."); |
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| 419 | // all case - [] : store, () : load |
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| 420 | // (1) store_max >= load_max and store_min <= load_min ...[...(...)...]... Ok - inclusion in store |
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| 421 | // (2) store_min > load_max ...[...]...(...)... Ok - no conflit |
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| 422 | // (3) store_max < load_min ...(...)...[...]... Ok - no conflit |
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| 423 | // (4) store_max < load_max and store_min > load_min ...(...[...]...)... Ko - inclusion in load |
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| 424 | // (5) store_max >= load_max and store_min > load_min ...[...(...]...)... Ko - conflit |
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| 425 | // (6) store_max < load_max and store_min <= load_min ...(...[...)...]... Ko - conflit |
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| 426 | // but : |
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| 427 | // load in the cache is a word ! |
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| 428 | // the mask can be make when the load is commited. Also, the rdata content a full word. |
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| 429 | // the only case is (4) |
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| 430 | |
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[104] | 431 | // Read data |
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[106] | 432 | bool is_big_endian = true; |
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[104] | 433 | |
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[106] | 434 | Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; |
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| 435 | Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; |
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| 436 | Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte; |
---|
| 437 | Tcontrol_t check_hit = _load_queue [index_load ]._check_hit; |
---|
| 438 | uint32_t load_size_access = memory_size(_load_queue [index_load ]._operation)>>3; |
---|
| 439 | uint32_t store_size_access = memory_size(_store_queue[index_store]._operation)>>3; |
---|
| 440 | |
---|
| 441 | log_printf(TRACE,Load_store_unit,FUNCTION," * is_big_endian : %d",is_big_endian); |
---|
| 442 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data : 0x%.8x",load_data); |
---|
| 443 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_data : 0x%.8x",store_data); |
---|
| 444 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); |
---|
| 445 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %d",check_hit); |
---|
| 446 | |
---|
| 447 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_size_access : %d",load_size_access ); |
---|
| 448 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_size_access : %d",store_size_access); |
---|
| 449 | |
---|
| 450 | if (is_big_endian) |
---|
| 451 | { |
---|
| 452 | // swap in little endian |
---|
| 453 | load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); |
---|
| 454 | store_data = swapBytes<Tgeneral_data_t >(store_data , _param->_size_general_data>>3,store_size_access); |
---|
| 455 | check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); |
---|
| 456 | |
---|
| 457 | |
---|
| 458 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 1) : 0x%.8x",load_data); |
---|
| 459 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (swap 1) : 0x%.8x",store_data); |
---|
| 460 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 1) : %x",check_hit_byte); |
---|
| 461 | } |
---|
| 462 | |
---|
[104] | 463 | uint32_t store_nb_byte = (1<<memory_access(_store_queue[index_store]._operation)); |
---|
| 464 | |
---|
| 465 | // Take interval to the store |
---|
[71] | 466 | uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb); |
---|
[104] | 467 | uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte; |
---|
| 468 | |
---|
[106] | 469 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); |
---|
| 470 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); |
---|
| 471 | |
---|
| 472 | // uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load]._operation)); |
---|
| 473 | |
---|
| 474 | // uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb); |
---|
| 475 | // uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte; |
---|
| 476 | |
---|
| 477 | // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_min : %d",load_num_byte_min); |
---|
| 478 | // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_max : %d",load_num_byte_max); |
---|
| 479 | |
---|
| 480 | // for (uint32_t num_load_byte=load_num_byte_min; num_load_byte<load_num_byte_max; num_load_byte ++) |
---|
| 481 | // { |
---|
| 482 | // // Make a mask |
---|
| 483 | // uint32_t num_store_byte = num_load_byte; |
---|
| 484 | |
---|
| 485 | |
---|
| 486 | |
---|
[71] | 487 | // The bypass is checked byte per byte |
---|
[104] | 488 | // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed. |
---|
| 489 | for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++) |
---|
[71] | 490 | { |
---|
[104] | 491 | // Make a mask |
---|
[106] | 492 | uint32_t num_load_byte = num_store_byte; |
---|
[104] | 493 | |
---|
[106] | 494 | // if (is_big_endian) |
---|
| 495 | // { |
---|
| 496 | // // sd 0 : 0 1 2 3 4 5 6 7 |
---|
| 497 | // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 |
---|
| 498 | // // lw 0 : 0 1 2 3 >> 0 -4 |
---|
| 499 | // // lw 4 : 4 5 6 7 >> 32 +4 |
---|
| 500 | // // lh 0 : 0 1 >> 0 -6 |
---|
| 501 | // // lh 2 : 2 3 >> 16 -2 |
---|
| 502 | // // lh 4 : 4 5 >> 32 +2 |
---|
| 503 | // // lh 6 : 6 7 >> 48 +6 |
---|
| 504 | // // lb 0 : 0 >> 0 -7 |
---|
| 505 | // // lb 1 : 1 >> 8 -5 |
---|
| 506 | // // lb 2 : 2 >> 16 -3 |
---|
| 507 | // // lb 3 : 3 >> 24 -1 |
---|
| 508 | // // lb 4 : 4 >> 32 +1 |
---|
| 509 | // // lb 5 : 5 >> 40 +3 |
---|
| 510 | // // lb 6 : 6 >> 48 +5 |
---|
| 511 | // // lb 7 : 7 >> 56 +7 |
---|
[104] | 512 | |
---|
[106] | 513 | // // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) |
---|
[104] | 514 | |
---|
[106] | 515 | // // store duplicate = all store access can be see as full size_data store |
---|
| 516 | // // uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation)); |
---|
[104] | 517 | |
---|
[106] | 518 | // // int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); |
---|
| 519 | |
---|
| 520 | // // num_load_byte =num_store_byte+diff; |
---|
| 521 | |
---|
| 522 | // // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); |
---|
| 523 | // // log_printf(TRACE,Load_store_unit,FUNCTION," * diff : %d",diff); |
---|
| 524 | |
---|
| 525 | |
---|
| 526 | // num_load_byte = num_store_byte; |
---|
| 527 | // } |
---|
| 528 | // else |
---|
| 529 | // { |
---|
| 530 | // // sd 0 : 0 1 2 3 4 5 6 7 |
---|
| 531 | // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 |
---|
| 532 | // // lw 0 : 4 5 6 7 >> 0 |
---|
| 533 | // // lw 4 : 0 1 2 3 >> 32 |
---|
| 534 | // // lh 0 : 6 7 >> 0 |
---|
| 535 | // // lh 2 : 4 5 >> 16 |
---|
| 536 | // // lh 4 : 2 3 >> 32 |
---|
| 537 | // // lh 6 : 0 1 >> 48 |
---|
| 538 | // // lb 0 : 7 >> 0 |
---|
| 539 | // // lb 1 : 6 >> 8 |
---|
| 540 | // // lb 2 : 5 >> 16 |
---|
| 541 | // // lb 3 : 4 >> 24 |
---|
| 542 | // // lb 4 : 3 >> 32 |
---|
| 543 | // // lb 5 : 2 >> 40 |
---|
| 544 | // // lb 6 : 1 >> 48 |
---|
| 545 | // // lb 7 : 0 >> 56 |
---|
[104] | 546 | |
---|
[106] | 547 | // num_load_byte = num_store_byte; |
---|
| 548 | // } |
---|
[104] | 549 | |
---|
| 550 | uint32_t mask = 1<<num_load_byte; |
---|
| 551 | |
---|
| 552 | log_printf(TRACE,Load_store_unit,FUNCTION," * num_store_byte : %d",num_store_byte); |
---|
| 553 | log_printf(TRACE,Load_store_unit,FUNCTION," * num_load_byte : %d",num_load_byte); |
---|
| 554 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %d",mask); |
---|
| 555 | |
---|
| 556 | // Accept the bypass if : |
---|
| 557 | // * they have not a previous bypass with an another store |
---|
| 558 | // * it's a valid request of load |
---|
[106] | 559 | if ((check_hit_byte&mask)==0) |
---|
[71] | 560 | { |
---|
[104] | 561 | // Note : Store is duplicate = all store access can be see as full size_data store |
---|
| 562 | |
---|
| 563 | uint32_t num_store_bit_min = num_store_byte<<3; //*8 |
---|
[106] | 564 | // uint32_t num_store_bit_max = num_store_bit_min+8-1; |
---|
[104] | 565 | uint32_t num_load_bit_min = num_load_byte <<3; //*8 |
---|
| 566 | uint32_t num_load_bit_max = num_load_bit_min+8-1; |
---|
| 567 | |
---|
[71] | 568 | log_printf(TRACE,Load_store_unit,FUNCTION," * bypass !!!"); |
---|
[104] | 569 | // log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min); |
---|
| 570 | log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [..:%d]",num_store_bit_min); |
---|
| 571 | log_printf(TRACE,Load_store_unit,FUNCTION," * interval load : [%d:%d]",num_load_bit_max,num_load_bit_min); |
---|
| 572 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_old : 0x%.8x", load_data); |
---|
| 573 | |
---|
| 574 | load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) | |
---|
| 575 | mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min)); |
---|
| 576 | |
---|
[106] | 577 | check_hit_byte |= mask; |
---|
| 578 | check_hit = 1; |
---|
[71] | 579 | change_state = true; |
---|
| 580 | |
---|
[104] | 581 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_new : 0x%.8x", load_data); |
---|
[71] | 582 | } |
---|
| 583 | } |
---|
| 584 | |
---|
[106] | 585 | if (is_big_endian) |
---|
| 586 | { |
---|
| 587 | // swap in little endian |
---|
| 588 | load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); |
---|
| 589 | check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); |
---|
| 590 | |
---|
| 591 | |
---|
| 592 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 2) : 0x%.8x",load_data); |
---|
| 593 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 2) : %x",check_hit_byte); |
---|
| 594 | } |
---|
| 595 | |
---|
| 596 | _load_queue[index_load]._rdata = load_data; |
---|
| 597 | _load_queue[index_load]._check_hit_byte = check_hit_byte; |
---|
| 598 | _load_queue[index_load]._check_hit = check_hit; |
---|
| 599 | |
---|
[104] | 600 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data); |
---|
[71] | 601 | |
---|
[106] | 602 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",check_hit); |
---|
| 603 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); |
---|
[71] | 604 | |
---|
| 605 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb)); |
---|
[104] | 606 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask_check_hit_byte: %x",_param->_mask_check_hit_byte); |
---|
[71] | 607 | // The check is finish if all bit is set |
---|
[104] | 608 | end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte); |
---|
[117] | 609 | |
---|
[71] | 610 | } |
---|
| 611 | } |
---|
| 612 | |
---|
| 613 | next = true; |
---|
| 614 | break; |
---|
| 615 | } |
---|
| 616 | case STORE_QUEUE_EMPTY : |
---|
| 617 | case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : |
---|
| 618 | { |
---|
| 619 | log_printf(TRACE,Load_store_unit,FUNCTION," * store have an invalid entry"); |
---|
| 620 | break; |
---|
| 621 | } |
---|
| 622 | } |
---|
| 623 | } |
---|
| 624 | |
---|
| 625 | if (next) |
---|
| 626 | { |
---|
| 627 | log_printf(TRACE,Load_store_unit,FUNCTION," * next"); |
---|
[106] | 628 | log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store); |
---|
[117] | 629 | |
---|
| 630 | log_printf(TRACE,Load_store_unit,FUNCTION," * update reg_STORE_QUEUE_NB_CHECK"); |
---|
| 631 | #ifdef DEBUG |
---|
| 632 | if (reg_STORE_QUEUE_NB_CHECK [index_store] == 0) |
---|
| 633 | throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); |
---|
| 634 | #endif |
---|
| 635 | reg_STORE_QUEUE_NB_CHECK [index_store] --; |
---|
| 636 | |
---|
[71] | 637 | // if (_load_queue[index_load]._store_queue_ptr_write == 0) |
---|
| 638 | // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; |
---|
| 639 | // else |
---|
| 640 | // _load_queue[index_load]._store_queue_ptr_write --; |
---|
| 641 | _load_queue[index_load]._store_queue_ptr_write = index_store; // because the index store have be decrease |
---|
| 642 | |
---|
| 643 | // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "reg_STORE_QUEUE_PTR_READ" |
---|
| 644 | if (index_store == reg_STORE_QUEUE_PTR_READ) |
---|
| 645 | { |
---|
| 646 | end_check = true; |
---|
| 647 | change_state = true; |
---|
| 648 | } |
---|
| 649 | } |
---|
| 650 | |
---|
| 651 | if (change_state) |
---|
| 652 | { |
---|
| 653 | log_printf(TRACE,Load_store_unit,FUNCTION," * change_state"); |
---|
[106] | 654 | log_printf(TRACE,Load_store_unit,FUNCTION," * end_check : %d",end_check); |
---|
[71] | 655 | |
---|
[106] | 656 | log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load]._state).c_str()); |
---|
| 657 | |
---|
[71] | 658 | switch (_load_queue[index_load]._state) |
---|
| 659 | { |
---|
[106] | 660 | case LOAD_QUEUE_WAIT_CHECK : |
---|
| 661 | { |
---|
| 662 | if (end_check) |
---|
| 663 | _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; |
---|
| 664 | break; |
---|
| 665 | } |
---|
[71] | 666 | case LOAD_QUEUE_COMMIT_CHECK : |
---|
| 667 | { |
---|
| 668 | if (end_check) |
---|
| 669 | _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; |
---|
| 670 | else |
---|
[106] | 671 | _load_queue[index_load]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end |
---|
[71] | 672 | break; |
---|
| 673 | } |
---|
| 674 | case LOAD_QUEUE_CHECK : |
---|
| 675 | { |
---|
| 676 | if (end_check) |
---|
| 677 | _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; |
---|
[106] | 678 | |
---|
[71] | 679 | // check find a bypass. A speculative load have been committed : report a speculation miss. |
---|
[112] | 680 | if ((_load_queue[index_load]._check_hit != 0) and |
---|
| 681 | (_load_queue[index_load]._write_rd == 0) // is commit |
---|
[106] | 682 | ) |
---|
[71] | 683 | { |
---|
| 684 | _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
---|
| 685 | _load_queue[index_load]._write_rd = 1; // write the good result |
---|
[110] | 686 | |
---|
| 687 | #ifdef STATISTICS |
---|
| 688 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 689 | (*_stat_nb_inst_load_commit_miss) ++; |
---|
| 690 | #endif |
---|
[71] | 691 | } |
---|
| 692 | |
---|
| 693 | break; |
---|
| 694 | } |
---|
| 695 | default : break; |
---|
| 696 | } |
---|
[106] | 697 | log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); |
---|
[71] | 698 | log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); |
---|
[117] | 699 | |
---|
| 700 | if (end_check) |
---|
| 701 | { |
---|
| 702 | log_printf(TRACE,Load_store_unit,FUNCTION," * end check, decrease all nb_check"); |
---|
| 703 | |
---|
| 704 | uint32_t i=index_store; |
---|
| 705 | while (i!=reg_STORE_QUEUE_PTR_READ) |
---|
| 706 | { |
---|
| 707 | i=((i==0)?_param->_size_store_queue:i)-1; |
---|
| 708 | |
---|
| 709 | #ifdef DEBUG |
---|
| 710 | if (reg_STORE_QUEUE_NB_CHECK [i] == 0) |
---|
| 711 | throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); |
---|
| 712 | #endif |
---|
| 713 | |
---|
| 714 | reg_STORE_QUEUE_NB_CHECK [i] --; |
---|
| 715 | //i=(i+1)%_param->_size_store_queue; |
---|
| 716 | } |
---|
| 717 | } |
---|
[71] | 718 | } |
---|
| 719 | } |
---|
| 720 | // else : don't use a port |
---|
| 721 | } |
---|
| 722 | |
---|
| 723 | //================================================================ |
---|
[59] | 724 | // Interface "MEMORY_IN" |
---|
| 725 | //================================================================ |
---|
[88] | 726 | |
---|
| 727 | if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and |
---|
[59] | 728 | ( internal_MEMORY_IN_ACK == 1)) |
---|
| 729 | { |
---|
[101] | 730 | log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_IN [%d]",internal_MEMORY_IN_PORT); |
---|
| 731 | |
---|
[59] | 732 | // Test operation : |
---|
| 733 | //~~~~~~~~~~~~~~~~~ |
---|
| 734 | // store in store_queue |
---|
| 735 | // load in speculation_access_queue |
---|
| 736 | // others in speculation_access_queue |
---|
| 737 | |
---|
[78] | 738 | #ifdef DEBUG_TEST |
---|
[88] | 739 | if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY) |
---|
[78] | 740 | throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'"); |
---|
| 741 | #endif |
---|
[88] | 742 | Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]); |
---|
| 743 | Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) + |
---|
| 744 | PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT])); |
---|
[62] | 745 | bool exception_alignement = (mask_memory_access(operation) & address) != 0; |
---|
[59] | 746 | |
---|
| 747 | if (is_operation_memory_store(operation) == true) |
---|
| 748 | { |
---|
| 749 | // ======================= |
---|
| 750 | // ===== STORE_QUEUE ===== |
---|
| 751 | // ======================= |
---|
| 752 | // There a two store request type : |
---|
| 753 | // - first is operation with address and data |
---|
| 754 | // - second is the information of re order buffer : the store become not speculative and can access at the data cache |
---|
| 755 | |
---|
[97] | 756 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue"); |
---|
| 757 | log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
---|
[59] | 758 | |
---|
| 759 | // Write pointer is define in rename stage : |
---|
[88] | 760 | Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
[97] | 761 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
---|
[59] | 762 | |
---|
| 763 | // Need read : state and exception. |
---|
| 764 | Tstore_queue_state_t old_state = _store_queue [index]._state; |
---|
| 765 | Tstore_queue_state_t new_state = old_state; |
---|
| 766 | bool update_info = false; |
---|
| 767 | |
---|
| 768 | Texception_t old_exception = _store_queue [index]._exception; |
---|
| 769 | Texception_t new_exception = old_exception; |
---|
| 770 | |
---|
| 771 | // Compute next state |
---|
| 772 | switch (old_state) |
---|
| 773 | { |
---|
| 774 | case STORE_QUEUE_EMPTY : |
---|
| 775 | { |
---|
| 776 | if (is_operation_memory_store_head(operation) == true) |
---|
| 777 | { |
---|
| 778 | new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE; |
---|
| 779 | |
---|
| 780 | // test if is a speculation |
---|
| 781 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
---|
| 782 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
---|
| 783 | else |
---|
| 784 | new_exception = EXCEPTION_MEMORY_NONE; |
---|
| 785 | } |
---|
| 786 | else |
---|
| 787 | { |
---|
| 788 | new_state = STORE_QUEUE_VALID_SPECULATIVE; |
---|
| 789 | |
---|
| 790 | // Test if have an exception |
---|
| 791 | if (exception_alignement == true) |
---|
| 792 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
---|
| 793 | else |
---|
| 794 | new_exception = EXCEPTION_MEMORY_NONE; |
---|
| 795 | |
---|
| 796 | update_info = true; |
---|
| 797 | } |
---|
| 798 | break; |
---|
| 799 | } |
---|
| 800 | case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : |
---|
| 801 | { |
---|
[71] | 802 | #ifdef DEBUG_TEST |
---|
| 803 | if (is_operation_memory_store_head(operation) == true) |
---|
[110] | 804 | throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head.")); |
---|
[71] | 805 | #endif |
---|
| 806 | // Test if have a new exception (priority : miss_speculation) |
---|
| 807 | if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE)) |
---|
| 808 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
---|
| 809 | |
---|
| 810 | if (new_exception != EXCEPTION_MEMORY_NONE) |
---|
| 811 | new_state = STORE_QUEUE_COMMIT; |
---|
| 812 | else |
---|
| 813 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
---|
| 814 | |
---|
| 815 | update_info = true; |
---|
| 816 | break; |
---|
[59] | 817 | } |
---|
| 818 | case STORE_QUEUE_VALID_SPECULATIVE : |
---|
| 819 | { |
---|
[71] | 820 | #ifdef DEBUG_TEST |
---|
| 821 | if (is_operation_memory_store_head(operation) == false) |
---|
[110] | 822 | throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head.")); |
---|
[71] | 823 | #endif |
---|
| 824 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
---|
| 825 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary |
---|
| 826 | |
---|
| 827 | if (new_exception != EXCEPTION_MEMORY_NONE) |
---|
| 828 | new_state = STORE_QUEUE_COMMIT; |
---|
| 829 | else |
---|
| 830 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
---|
| 831 | |
---|
| 832 | break; |
---|
[59] | 833 | } |
---|
| 834 | case STORE_QUEUE_VALID_NO_SPECULATIVE : |
---|
| 835 | case STORE_QUEUE_COMMIT : |
---|
| 836 | { |
---|
[110] | 837 | throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation"); |
---|
[59] | 838 | } |
---|
| 839 | } |
---|
| 840 | |
---|
| 841 | _store_queue [index]._state = new_state; |
---|
| 842 | _store_queue [index]._exception = new_exception; |
---|
| 843 | |
---|
| 844 | if (update_info == true) |
---|
| 845 | { |
---|
[97] | 846 | log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); |
---|
[59] | 847 | |
---|
[88] | 848 | _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); |
---|
| 849 | _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); |
---|
| 850 | _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); |
---|
| 851 | _store_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); |
---|
[71] | 852 | _store_queue [index]._operation = operation; |
---|
[88] | 853 | _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
[59] | 854 | _store_queue [index]._address = address; |
---|
[71] | 855 | |
---|
| 856 | // reordering data |
---|
[104] | 857 | _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); |
---|
[88] | 858 | // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); |
---|
[59] | 859 | } |
---|
| 860 | } |
---|
| 861 | else |
---|
| 862 | { |
---|
[71] | 863 | // ==================================== |
---|
| 864 | // ===== SPECULATIVE_ACCESS_QUEUE ===== |
---|
| 865 | // ==================================== |
---|
[59] | 866 | |
---|
[71] | 867 | // In speculative access queue, they are many type's request |
---|
[97] | 868 | log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); |
---|
| 869 | log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
---|
[59] | 870 | |
---|
[71] | 871 | // Write in reservation station |
---|
| 872 | uint32_t index = _speculative_access_queue_control->push(); |
---|
| 873 | |
---|
[97] | 874 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index); |
---|
[71] | 875 | |
---|
| 876 | Texception_t exception; |
---|
| 877 | |
---|
| 878 | if (exception_alignement == true) |
---|
| 879 | exception = EXCEPTION_MEMORY_ALIGNMENT; |
---|
| 880 | else |
---|
| 881 | exception = EXCEPTION_MEMORY_NONE; |
---|
| 882 | |
---|
| 883 | // if exception, don't access at the cache |
---|
| 884 | // NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits) |
---|
| 885 | _speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE; |
---|
[88] | 886 | _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); |
---|
| 887 | _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); |
---|
| 888 | _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); |
---|
| 889 | _speculative_access_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); |
---|
[71] | 890 | |
---|
| 891 | _speculative_access_queue [index]._operation = operation; |
---|
[88] | 892 | _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
| 893 | _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
[71] | 894 | _speculative_access_queue [index]._address = address; |
---|
| 895 | // NOTE : is operation is a load, then they are a result and must write in the register file |
---|
| 896 | _speculative_access_queue [index]._write_rd = is_operation_memory_load(operation); |
---|
[88] | 897 | _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); |
---|
[71] | 898 | |
---|
| 899 | _speculative_access_queue [index]._exception = exception; |
---|
[59] | 900 | |
---|
[97] | 901 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
---|
[59] | 902 | } |
---|
| 903 | } |
---|
| 904 | |
---|
| 905 | //================================================================ |
---|
[62] | 906 | // Interface "DCACHE_REQ" |
---|
| 907 | //================================================================ |
---|
[71] | 908 | bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE); |
---|
| 909 | |
---|
[62] | 910 | if (( internal_DCACHE_REQ_VAL == 1) and |
---|
[88] | 911 | (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) |
---|
[62] | 912 | { |
---|
[104] | 913 | log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ [0]"); |
---|
[71] | 914 | |
---|
[62] | 915 | switch (internal_DCACHE_REQ_SELECT_QUEUE) |
---|
| 916 | { |
---|
| 917 | case SELECT_STORE_QUEUE : |
---|
| 918 | { |
---|
| 919 | // ======================= |
---|
| 920 | // ===== STORE_QUEUE ===== |
---|
| 921 | // ======================= |
---|
| 922 | |
---|
| 923 | // Entry flush and increase the read pointer |
---|
| 924 | |
---|
[71] | 925 | _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT; |
---|
[62] | 926 | |
---|
| 927 | break; |
---|
| 928 | } |
---|
[71] | 929 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
---|
| 930 | { |
---|
| 931 | // ========================================= |
---|
| 932 | // ===== SELECT_LOAD_QUEUE_SPECULATIVE ===== |
---|
| 933 | // ========================================= |
---|
| 934 | |
---|
| 935 | load_queue_push = true; |
---|
| 936 | break; |
---|
| 937 | } |
---|
[62] | 938 | case SELECT_LOAD_QUEUE : |
---|
[71] | 939 | { |
---|
[110] | 940 | throw ERRORMORPHEO(FUNCTION,_("Invalid selection")); |
---|
[71] | 941 | break; |
---|
| 942 | } |
---|
| 943 | |
---|
[62] | 944 | break; |
---|
| 945 | } |
---|
| 946 | } |
---|
| 947 | |
---|
[71] | 948 | if (load_queue_push) |
---|
| 949 | { |
---|
| 950 | Tlsq_ptr_t ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write; |
---|
| 951 | Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation; |
---|
| 952 | Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception; |
---|
| 953 | bool have_exception = (exception != EXCEPTION_MEMORY_NONE); |
---|
| 954 | |
---|
| 955 | if (have_exception) |
---|
| 956 | _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT; |
---|
| 957 | else |
---|
| 958 | { |
---|
| 959 | if (have_dcache_rsp(operation)) |
---|
| 960 | { |
---|
| 961 | // load and synchronisation |
---|
| 962 | if (must_check(operation)) |
---|
| 963 | { |
---|
| 964 | // load |
---|
| 965 | _load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK; |
---|
| 966 | } |
---|
| 967 | else |
---|
| 968 | { |
---|
| 969 | // synchronisation |
---|
| 970 | _load_queue [ptr_write]._state = LOAD_QUEUE_WAIT; |
---|
| 971 | } |
---|
| 972 | } |
---|
| 973 | else |
---|
| 974 | { |
---|
| 975 | // lock, prefecth, flush and invalidate |
---|
| 976 | _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT; |
---|
| 977 | } |
---|
| 978 | } |
---|
| 979 | |
---|
| 980 | Tdcache_address_t address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address; |
---|
| 981 | Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb); |
---|
[104] | 982 | Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte; |
---|
[117] | 983 | Tlsq_ptr_t store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write; |
---|
[104] | 984 | |
---|
| 985 | log_printf(TRACE,Load_store_unit,FUNCTION," * address : 0x%.8x", address); |
---|
| 986 | log_printf(TRACE,Load_store_unit,FUNCTION," * address_lsb : 0x%.8x", address_lsb); |
---|
| 987 | log_printf(TRACE,Load_store_unit,FUNCTION," * operation : %d", operation); |
---|
| 988 | log_printf(TRACE,Load_store_unit,FUNCTION," * memory_size : %d", memory_size(operation)); |
---|
| 989 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x", check_hit_byte); |
---|
| 990 | |
---|
| 991 | _load_queue [ptr_write]._context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id; |
---|
| 992 | _load_queue [ptr_write]._front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id; |
---|
| 993 | _load_queue [ptr_write]._ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id; |
---|
| 994 | _load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id; |
---|
| 995 | _load_queue [ptr_write]._operation = operation; |
---|
[117] | 996 | _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write; |
---|
[104] | 997 | _load_queue [ptr_write]._address = address; |
---|
| 998 | _load_queue [ptr_write]._check_hit_byte = check_hit_byte; |
---|
| 999 | _load_queue [ptr_write]._check_hit = 0; |
---|
| 1000 | _load_queue [ptr_write]._shift = address_lsb<<3;// *8 |
---|
| 1001 | _load_queue [ptr_write]._is_load_signed = is_operation_memory_load_signed(operation); |
---|
| 1002 | _load_queue [ptr_write]._access_size = memory_size(operation); |
---|
[71] | 1003 | // NOTE : if have an exception, must write in register, because a depend instruction wait the load data. |
---|
[104] | 1004 | _load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ; |
---|
| 1005 | _load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ; |
---|
| 1006 | _load_queue [ptr_write]._exception = exception; |
---|
| 1007 | _load_queue [ptr_write]._rdata = address; // to the exception |
---|
[71] | 1008 | |
---|
[97] | 1009 | log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); |
---|
| 1010 | log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]); |
---|
[71] | 1011 | |
---|
| 1012 | _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; |
---|
| 1013 | |
---|
| 1014 | _speculative_access_queue_control->pop(); |
---|
| 1015 | |
---|
[110] | 1016 | #ifdef STATISTICS |
---|
| 1017 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 1018 | (*_stat_nb_inst_load) ++; |
---|
| 1019 | #endif |
---|
[117] | 1020 | |
---|
| 1021 | // Only load need check |
---|
| 1022 | if (is_operation_memory_load(_load_queue [ptr_write]._operation)) |
---|
| 1023 | { |
---|
| 1024 | log_printf(TRACE,Load_store_unit,FUNCTION," * update nb_check"); |
---|
| 1025 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write); |
---|
| 1026 | log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ); |
---|
| 1027 | |
---|
| 1028 | uint32_t i=store_queue_ptr_write; |
---|
| 1029 | while (i!=reg_STORE_QUEUE_PTR_READ) |
---|
| 1030 | { |
---|
| 1031 | i=((i==0)?_param->_size_store_queue:i)-1; |
---|
| 1032 | |
---|
| 1033 | log_printf(TRACE,Load_store_unit,FUNCTION," * i : %d",i); |
---|
| 1034 | |
---|
| 1035 | reg_STORE_QUEUE_NB_CHECK [i] ++; |
---|
| 1036 | } |
---|
| 1037 | } |
---|
[110] | 1038 | } |
---|
| 1039 | |
---|
[71] | 1040 | //================================================================ |
---|
| 1041 | // Interface "DCACHE_RSP" |
---|
| 1042 | //================================================================ |
---|
[88] | 1043 | if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and |
---|
[71] | 1044 | ( internal_DCACHE_RSP_ACK == 1)) |
---|
| 1045 | { |
---|
[101] | 1046 | log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP [0]"); |
---|
[71] | 1047 | |
---|
| 1048 | // don't use context_id : because there are one queue for all thread |
---|
[88] | 1049 | //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); |
---|
| 1050 | Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]); |
---|
| 1051 | Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA [0]); |
---|
| 1052 | Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); |
---|
[71] | 1053 | |
---|
[101] | 1054 | log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); |
---|
[106] | 1055 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet_id : %d" , packet_id>>1); |
---|
[101] | 1056 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); |
---|
| 1057 | log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); |
---|
[71] | 1058 | |
---|
| 1059 | if (DCACHE_RSP_IS_LOAD(packet_id) == 1) |
---|
| 1060 | { |
---|
| 1061 | packet_id >>= 1; |
---|
| 1062 | |
---|
[106] | 1063 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD"); |
---|
[71] | 1064 | |
---|
| 1065 | #ifdef DEBUG_TEST |
---|
| 1066 | if (not have_dcache_rsp(_load_queue [packet_id]._operation)) |
---|
[110] | 1067 | throw ERRORMORPHEO(FUNCTION,_("Receive of respons, but the corresponding operation don't wait a respons.")); |
---|
[71] | 1068 | #endif |
---|
[101] | 1069 | |
---|
[104] | 1070 | Tdcache_data_t data = _load_queue [packet_id]._rdata; |
---|
| 1071 | |
---|
| 1072 | log_printf(TRACE,Load_store_unit,FUNCTION," * data construction"); |
---|
| 1073 | log_printf(TRACE,Load_store_unit,FUNCTION," * data from cache : 0x%.8x",rdata); |
---|
| 1074 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (before) : 0x%.8x", data); |
---|
| 1075 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x" ,_load_queue [packet_id]._check_hit_byte); |
---|
| 1076 | for (uint32_t i=0;i<(_param->_size_general_data>>3)/*8*/; ++i) |
---|
| 1077 | // Test if this byte has been checked |
---|
| 1078 | if ((_load_queue [packet_id]._check_hit_byte & (1<<i)) == 0) |
---|
| 1079 | { |
---|
| 1080 | log_printf(TRACE,Load_store_unit,FUNCTION," * no previous check ]%d:%d]",(i+1)<<3,i<<3); |
---|
| 1081 | data = insert<Tdcache_data_t>(data,rdata,((i+1)<<3)-1,i<<3); |
---|
| 1082 | } |
---|
| 1083 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (after) : 0x%.8x", data); |
---|
| 1084 | |
---|
| 1085 | _load_queue [packet_id]._rdata = data; |
---|
[71] | 1086 | |
---|
[72] | 1087 | if (error != DCACHE_ERROR_NONE) |
---|
[71] | 1088 | { |
---|
[97] | 1089 | log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!"); |
---|
[71] | 1090 | |
---|
| 1091 | _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR; |
---|
| 1092 | _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT; |
---|
[118] | 1093 | |
---|
| 1094 | |
---|
| 1095 | uint32_t i=_load_queue[packet_id]._store_queue_ptr_write; |
---|
| 1096 | while (i!=reg_STORE_QUEUE_PTR_READ) |
---|
| 1097 | { |
---|
| 1098 | i=((i==0)?_param->_size_store_queue:i)-1; |
---|
| 1099 | |
---|
| 1100 | #ifdef DEBUG |
---|
| 1101 | if (reg_STORE_QUEUE_NB_CHECK [i] == 0) |
---|
| 1102 | throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); |
---|
| 1103 | #endif |
---|
| 1104 | |
---|
| 1105 | reg_STORE_QUEUE_NB_CHECK [i] --; |
---|
| 1106 | //i=(i+1)%_param->_size_store_queue; |
---|
| 1107 | } |
---|
[71] | 1108 | } |
---|
| 1109 | else |
---|
| 1110 | { |
---|
[97] | 1111 | log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); |
---|
[106] | 1112 | log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %s",toString(_load_queue [packet_id]._state).c_str()); |
---|
[71] | 1113 | |
---|
| 1114 | // FIXME : convention : if bus error, the cache return the fautive address ! |
---|
| 1115 | // But, the load's address is aligned ! |
---|
[101] | 1116 | |
---|
[71] | 1117 | switch (_load_queue [packet_id]._state) |
---|
| 1118 | { |
---|
| 1119 | case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break; |
---|
| 1120 | case LOAD_QUEUE_WAIT : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT ; break; |
---|
[110] | 1121 | default : throw ERRORMORPHEO(FUNCTION,_("Illegal state (dcache_rsp).")); break; |
---|
[71] | 1122 | } |
---|
| 1123 | } |
---|
| 1124 | } |
---|
| 1125 | else |
---|
| 1126 | { |
---|
[97] | 1127 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE"); |
---|
[71] | 1128 | |
---|
| 1129 | // TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!! |
---|
| 1130 | throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)")); |
---|
| 1131 | } |
---|
| 1132 | |
---|
| 1133 | } |
---|
| 1134 | |
---|
| 1135 | // this register is to manage the priority of check -> Round robin |
---|
| 1136 | reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue; |
---|
| 1137 | |
---|
| 1138 | |
---|
[88] | 1139 | #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) |
---|
[62] | 1140 | // ***** dump store queue |
---|
[97] | 1141 | log_printf(TRACE,Load_store_unit,FUNCTION," * Dump STORE_QUEUE"); |
---|
| 1142 | log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); |
---|
[62] | 1143 | |
---|
| 1144 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
| 1145 | { |
---|
[71] | 1146 | uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; |
---|
[97] | 1147 | |
---|
[117] | 1148 | log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %.2d %s", |
---|
[97] | 1149 | j, |
---|
| 1150 | _store_queue[j]._context_id , |
---|
| 1151 | _store_queue[j]._front_end_id , |
---|
| 1152 | _store_queue[j]._ooo_engine_id , |
---|
| 1153 | _store_queue[j]._packet_id , |
---|
| 1154 | _store_queue[j]._operation , |
---|
| 1155 | _store_queue[j]._load_queue_ptr_write, |
---|
| 1156 | _store_queue[j]._address , |
---|
| 1157 | _store_queue[j]._wdata , |
---|
| 1158 | //_store_queue[j]._write_rd , |
---|
| 1159 | //_store_queue[j]._num_reg_rd , |
---|
| 1160 | _store_queue[j]._exception , |
---|
[117] | 1161 | reg_STORE_QUEUE_NB_CHECK [j] , |
---|
[97] | 1162 | toString(_store_queue[j]._state).c_str()); |
---|
[62] | 1163 | } |
---|
[71] | 1164 | |
---|
| 1165 | // ***** dump speculative_access queue |
---|
[97] | 1166 | log_printf(TRACE,Load_store_unit,FUNCTION," * Dump SPECULATIVE_ACCESS_QUEUE"); |
---|
[71] | 1167 | |
---|
| 1168 | for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) |
---|
| 1169 | { |
---|
| 1170 | uint32_t j = (*_speculative_access_queue_control)[i]; |
---|
[97] | 1171 | |
---|
[101] | 1172 | log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s", |
---|
[97] | 1173 | j, |
---|
| 1174 | _speculative_access_queue[j]._context_id , |
---|
| 1175 | _speculative_access_queue[j]._front_end_id , |
---|
| 1176 | _speculative_access_queue[j]._ooo_engine_id , |
---|
| 1177 | _speculative_access_queue[j]._packet_id , |
---|
| 1178 | _speculative_access_queue[j]._operation , |
---|
| 1179 | _speculative_access_queue[j]._load_queue_ptr_write, |
---|
| 1180 | _speculative_access_queue[j]._store_queue_ptr_write, |
---|
| 1181 | _speculative_access_queue[j]._address , |
---|
| 1182 | _speculative_access_queue[j]._write_rd , |
---|
| 1183 | _speculative_access_queue[j]._num_reg_rd , |
---|
| 1184 | _speculative_access_queue[j]._exception , |
---|
| 1185 | toString(_speculative_access_queue[j]._state).c_str()); |
---|
[71] | 1186 | } |
---|
| 1187 | |
---|
| 1188 | // ***** dump load queue |
---|
[97] | 1189 | log_printf(TRACE,Load_store_unit,FUNCTION," * Dump LOAD_QUEUE"); |
---|
| 1190 | log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY); |
---|
[71] | 1191 | |
---|
| 1192 | for (uint32_t i=0; i<_param->_size_load_queue; i++) |
---|
| 1193 | { |
---|
| 1194 | uint32_t j = i; |
---|
[97] | 1195 | |
---|
[101] | 1196 | log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s", |
---|
[97] | 1197 | j, |
---|
| 1198 | _load_queue[j]._context_id , |
---|
| 1199 | _load_queue[j]._front_end_id , |
---|
| 1200 | _load_queue[j]._ooo_engine_id , |
---|
| 1201 | _load_queue[j]._packet_id , |
---|
| 1202 | _load_queue[j]._operation , |
---|
| 1203 | _load_queue[j]._store_queue_ptr_write, |
---|
| 1204 | _load_queue[j]._address , |
---|
| 1205 | _load_queue[j]._check_hit_byte , |
---|
| 1206 | _load_queue[j]._check_hit , |
---|
| 1207 | _load_queue[j]._shift , |
---|
| 1208 | _load_queue[j]._is_load_signed , |
---|
| 1209 | _load_queue[j]._access_size , |
---|
| 1210 | _load_queue[j]._rdata , |
---|
| 1211 | _load_queue[j]._write_rd , |
---|
| 1212 | _load_queue[j]._num_reg_rd , |
---|
| 1213 | _load_queue[j]._exception , |
---|
| 1214 | toString(_load_queue[j]._state).c_str()); |
---|
[71] | 1215 | } |
---|
[62] | 1216 | #endif |
---|
[71] | 1217 | |
---|
| 1218 | #ifdef STATISTICS |
---|
[88] | 1219 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 1220 | { |
---|
| 1221 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
| 1222 | if (_store_queue[i]._state != STORE_QUEUE_EMPTY) |
---|
| 1223 | (*_stat_use_store_queue) ++; |
---|
| 1224 | for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) |
---|
| 1225 | if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) |
---|
| 1226 | (*_stat_use_speculative_access_queue) ++; |
---|
| 1227 | for (uint32_t i=0; i<_param->_size_load_queue; i++) |
---|
| 1228 | if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) |
---|
| 1229 | (*_stat_use_load_queue) ++; |
---|
| 1230 | } |
---|
[71] | 1231 | #endif |
---|
[59] | 1232 | } |
---|
| 1233 | |
---|
[97] | 1234 | log_end(Load_store_unit,FUNCTION); |
---|
[59] | 1235 | }; |
---|
| 1236 | |
---|
| 1237 | }; // end namespace load_store_unit |
---|
| 1238 | }; // end namespace execute_unit |
---|
| 1239 | }; // end namespace multi_execute_unit |
---|
| 1240 | }; // end namespace execute_loop |
---|
| 1241 | }; // end namespace multi_execute_loop |
---|
| 1242 | }; // end namespace core |
---|
| 1243 | |
---|
| 1244 | }; // end namespace behavioural |
---|
| 1245 | }; // end namespace morpheo |
---|
| 1246 | #endif |
---|