[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_transition.cpp 101 2009-01-15 17:19:08Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Context_State::transition" |
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| 21 | void Context_State::transition (void) |
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| 22 | { |
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| 23 | log_begin(Context_State,FUNCTION); |
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[88] | 24 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[88] | 28 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 29 | { |
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| 30 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 31 | reg_INTERRUPT_ENABLE [i] = 0; |
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| 32 | } |
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[83] | 33 | } |
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| 34 | else |
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| 35 | { |
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[88] | 36 | // ------------------------------------------------------------------- |
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[101] | 37 | // -----[ next state ]------------------------------------------------ |
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| 38 | // ------------------------------------------------------------------- |
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| 39 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 40 | { |
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| 41 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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| 42 | |
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| 43 | Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 44 | // Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 45 | |
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| 46 | context_state_t state = reg_STATE [i]; |
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| 47 | |
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| 48 | switch (state) |
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| 49 | { |
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| 50 | case CONTEXT_STATE_OK : |
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| 51 | { |
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| 52 | // nothing, wait an event |
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| 53 | break; |
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| 54 | } |
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| 55 | case CONTEXT_STATE_KO_EXCEP : |
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| 56 | { |
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| 57 | // Wait end of all instruction |
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| 58 | if (inst_all == 0) |
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| 59 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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| 60 | break; |
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| 61 | } |
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| 62 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 63 | { |
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| 64 | // nothing, wait the update of internal register (pc) |
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| 65 | break; |
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| 66 | } |
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| 67 | case CONTEXT_STATE_KO_MISS_WAITEND : |
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| 68 | { |
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| 69 | // Wait end of all instruction |
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| 70 | if (inst_all == 0) |
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| 71 | |
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| 72 | // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) |
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| 73 | state = CONTEXT_STATE_KO_MISS_ADDR; |
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| 74 | break; |
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| 75 | } |
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| 76 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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| 77 | { |
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| 78 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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| 79 | break; |
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| 80 | } |
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| 81 | case CONTEXT_STATE_KO_MISS_ADDR : |
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| 82 | { |
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| 83 | // nothing, wait the update of internal register (pc) |
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| 84 | break; |
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| 85 | } |
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| 86 | // case CONTEXT_STATE_KO_PSYNC : |
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| 87 | // { |
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| 88 | // // Wait end of all instruction |
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| 89 | // if (inst_all == 0) |
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| 90 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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| 91 | // break; |
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| 92 | // } |
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| 93 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 94 | { |
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| 95 | // nothing, wait end of flush (ifetch) |
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| 96 | if (inst_all == 0) |
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| 97 | // state = CONTEXT_STATE_KO_PSYNC_ADDR; |
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| 98 | state = CONTEXT_STATE_OK; |
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| 99 | |
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| 100 | break; |
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| 101 | } |
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| 102 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 103 | { |
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| 104 | // nothing, wait the pc write |
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| 105 | break; |
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| 106 | } |
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| 107 | // case CONTEXT_STATE_KO_CSYNC : |
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| 108 | // { |
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| 109 | // // Wait end of all instruction |
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| 110 | // if (inst_all == 0) |
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| 111 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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| 112 | // break; |
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| 113 | // } |
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| 114 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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| 115 | { |
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| 116 | // nothing, wait end of flush (all internal structure) |
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| 117 | if (inst_all == 0) |
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| 118 | state = CONTEXT_STATE_KO_CSYNC_ADDR; |
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| 119 | break; |
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| 120 | } |
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| 121 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 122 | { |
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| 123 | // nothing, wait the pc write |
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| 124 | break; |
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| 125 | } |
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| 126 | // case CONTEXT_STATE_KO_MSYNC : |
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| 127 | // { |
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| 128 | // // Wait end of memory instruction |
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| 129 | // if (inst_mem == 0) |
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| 130 | // state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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| 131 | // break; |
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| 132 | // } |
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| 133 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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| 134 | // { |
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| 135 | // // Wait the msync issue |
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| 136 | // if (inst_mem != 0) |
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| 137 | // state = CONTEXT_STATE_KO_MSYNC_EXEC; |
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| 138 | // break; |
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| 139 | // } |
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| 140 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
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| 141 | { |
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| 142 | // Wait the end of msync |
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| 143 | if (inst_all == 0) |
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| 144 | state = CONTEXT_STATE_OK; |
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| 145 | break; |
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| 146 | } |
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| 147 | // case CONTEXT_STATE_KO_SPR : |
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| 148 | // { |
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| 149 | // // Wait end of all instruction |
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| 150 | // if (inst_all == 0) |
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| 151 | // state = CONTEXT_STATE_KO_SPR_ISSUE; |
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| 152 | // break; |
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| 153 | // } |
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| 154 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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| 155 | // { |
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| 156 | // // Wait the spr_access issue |
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| 157 | // if (inst_all != 0) |
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| 158 | // state = CONTEXT_STATE_KO_SPR_EXEC; |
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| 159 | // break; |
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| 160 | // } |
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| 161 | case CONTEXT_STATE_KO_SPR_EXEC : |
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| 162 | { |
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| 163 | // Wait the spr_access execution |
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| 164 | if (inst_all == 0) |
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| 165 | state = CONTEXT_STATE_OK; |
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| 166 | break; |
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| 167 | } |
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| 168 | |
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| 169 | default : |
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| 170 | { |
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| 171 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
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| 172 | } |
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| 173 | } |
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| 174 | reg_STATE [i] = state; |
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| 175 | } |
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| 176 | |
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| 177 | // ------------------------------------------------------------------- |
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[88] | 178 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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| 179 | // ------------------------------------------------------------------- |
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| 180 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 181 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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| 182 | { |
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[98] | 183 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); |
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| 184 | |
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[88] | 185 | // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); |
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[83] | 186 | |
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[88] | 187 | context_state_t state = reg_STATE [i]; |
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[83] | 188 | |
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[98] | 189 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; |
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[88] | 190 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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| 191 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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| 192 | Tdepth_t depth_max = _param->_array_size_depth [i]; |
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| 193 | |
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| 194 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 195 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 196 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 197 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 198 | |
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[88] | 199 | // priority : miss > excep > spr/sync |
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[101] | 200 | uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); |
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[88] | 201 | uint8_t priority1 = 2; // miss |
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[83] | 202 | |
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[88] | 203 | // is_valid = can modify local information |
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| 204 | // if context_state_ok : yes |
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[98] | 205 | // if context_state_ko : test the depth, and the priority of event |
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[83] | 206 | |
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[88] | 207 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 208 | (depth1< depth0) or |
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[98] | 209 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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[83] | 210 | |
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[88] | 211 | if (is_valid) |
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| 212 | { |
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[95] | 213 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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[101] | 214 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_ADDR; |
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| 215 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
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[95] | 216 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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| 217 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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| 218 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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[88] | 219 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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| 220 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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[98] | 221 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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[95] | 222 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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[88] | 223 | reg_EVENT_DEPTH [i] = depth; |
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| 224 | } |
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| 225 | } |
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| 226 | |
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| 227 | // ------------------------------------------------------------------- |
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| 228 | // -----[ DECOD_EVENT ]----------------------------------------------- |
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| 229 | // ------------------------------------------------------------------- |
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[83] | 230 | |
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[88] | 231 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
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| 232 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
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| 233 | { |
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[98] | 234 | log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); |
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| 235 | |
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[88] | 236 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
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| 237 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
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| 238 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 239 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 240 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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| 241 | |
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| 242 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 243 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 244 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 245 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 246 | |
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[88] | 247 | context_state_t state = reg_STATE [context]; |
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| 248 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
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| 249 | |
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| 250 | // miss > excep > spr/sync |
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[101] | 251 | uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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[88] | 252 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; |
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[83] | 253 | |
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[88] | 254 | // is_valid = can modify local information |
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| 255 | // if context_state_ok : yes |
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| 256 | // if context_state_ko : test the depth, and the priority of envent |
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[83] | 257 | |
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[88] | 258 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 259 | (depth1< depth0) or |
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| 260 | ((depth1==depth0) and (priority1>priority0))); |
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[83] | 261 | |
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[88] | 262 | if (is_valid) |
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| 263 | { |
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[101] | 264 | log_printf(TRACE,Context_State,FUNCTION," * is_valid"); |
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| 265 | |
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[88] | 266 | // decod : |
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| 267 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
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| 268 | context_state_t state_next = state; |
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| 269 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
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| 270 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
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[83] | 271 | |
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[88] | 272 | switch (type) |
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| 273 | { |
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| 274 | case EVENT_TYPE_EXCEPTION : |
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| 275 | { |
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[101] | 276 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); |
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| 277 | |
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[88] | 278 | state_next = CONTEXT_STATE_KO_EXCEP; |
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[83] | 279 | |
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[88] | 280 | break; |
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| 281 | } |
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| 282 | case EVENT_TYPE_SPR_ACCESS : |
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| 283 | { |
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[101] | 284 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); |
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| 285 | |
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| 286 | // state_next = CONTEXT_STATE_KO_SPR ; |
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| 287 | state_next = CONTEXT_STATE_KO_SPR_EXEC; |
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[88] | 288 | address++; // take next address |
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[101] | 289 | // if (is_delay_slot) |
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| 290 | // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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[88] | 291 | break; |
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| 292 | } |
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| 293 | case EVENT_TYPE_MSYNC : |
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| 294 | { |
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[101] | 295 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); |
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| 296 | |
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| 297 | // state_next = CONTEXT_STATE_KO_MSYNC; |
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| 298 | state_next = CONTEXT_STATE_KO_MSYNC_EXEC; |
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[88] | 299 | address++; // take next address |
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[101] | 300 | // if (is_delay_slot) |
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| 301 | // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); |
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[88] | 302 | break; |
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| 303 | } |
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| 304 | case EVENT_TYPE_PSYNC : |
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| 305 | { |
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[101] | 306 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); |
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| 307 | |
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| 308 | // state_next = CONTEXT_STATE_KO_PSYNC; |
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| 309 | state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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[88] | 310 | address++; // take next address |
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| 311 | if (is_delay_slot) |
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[101] | 312 | throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); |
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[88] | 313 | break; |
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| 314 | } |
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| 315 | case EVENT_TYPE_CSYNC : |
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| 316 | { |
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[101] | 317 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); |
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| 318 | |
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| 319 | // state_next = CONTEXT_STATE_KO_CSYNC; |
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| 320 | state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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[88] | 321 | address++; // take next address |
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| 322 | if (is_delay_slot) |
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[101] | 323 | throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); |
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[88] | 324 | break; |
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| 325 | } |
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| 326 | case EVENT_TYPE_NONE : |
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| 327 | case EVENT_TYPE_MISS_SPECULATION : |
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| 328 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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| 329 | default : |
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| 330 | { |
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| 331 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
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| 332 | } |
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| 333 | } |
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[83] | 334 | |
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[88] | 335 | reg_STATE [context] = state_next; |
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| 336 | reg_EVENT_ADDRESS [context] = address; |
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| 337 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
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| 338 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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| 339 | //reg_EVENT_ADDRESS_EEAR [context] |
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| 340 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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| 341 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
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| 342 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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| 343 | reg_EVENT_DEPTH [context] = depth; |
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| 344 | } |
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| 345 | } |
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[83] | 346 | |
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[88] | 347 | // ------------------------------------------------------------------- |
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| 348 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
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| 349 | // ------------------------------------------------------------------- |
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[83] | 350 | |
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[88] | 351 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
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| 352 | { |
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[98] | 353 | log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); |
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| 354 | |
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[88] | 355 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
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| 356 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
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| 357 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 358 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 359 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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| 360 | |
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| 361 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 362 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 363 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 364 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 365 | |
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[88] | 366 | context_state_t state = reg_STATE [context]; |
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| 367 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
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| 368 | |
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| 369 | // miss > excep > spr/sync |
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[101] | 370 | uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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[88] | 371 | uint8_t priority1 = 1; // exception |
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| 372 | |
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| 373 | // is_valid = can modify local information |
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| 374 | // if context_state_ok : yes |
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| 375 | // if context_state_ko : test the depth, and the priority of envent |
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| 376 | |
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| 377 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 378 | (depth1< depth0) or |
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| 379 | ((depth1==depth0) and (priority1>priority0))); |
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| 380 | |
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| 381 | if (is_valid) |
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| 382 | { |
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| 383 | // commit |
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| 384 | // type : exception |
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| 385 | context_state_t state_next = state; |
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| 386 | switch (type) |
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| 387 | { |
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| 388 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
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| 389 | case EVENT_TYPE_SPR_ACCESS : |
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| 390 | case EVENT_TYPE_MSYNC : |
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| 391 | case EVENT_TYPE_PSYNC : |
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| 392 | case EVENT_TYPE_CSYNC : |
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| 393 | case EVENT_TYPE_NONE : |
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| 394 | case EVENT_TYPE_MISS_SPECULATION : |
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| 395 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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| 396 | default : |
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| 397 | { |
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| 398 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
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| 399 | } |
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| 400 | } |
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| 401 | reg_STATE [context] = state_next; |
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| 402 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
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| 403 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
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| 404 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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| 405 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
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| 406 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
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| 407 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
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| 408 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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| 409 | reg_EVENT_DEPTH [context] = depth; |
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| 410 | } |
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| 411 | } |
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| 412 | |
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| 413 | // ------------------------------------------------------------------- |
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| 414 | // -----[ BRANCH_COMPLETE ]------------------------------------------- |
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| 415 | // ------------------------------------------------------------------- |
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| 416 | |
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[98] | 417 | // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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| 418 | // if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) |
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| 419 | // { |
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| 420 | // log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
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| 421 | // if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
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| 422 | // { |
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| 423 | // Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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| 424 | // Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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| 425 | // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 426 | // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 427 | // Tdepth_t depth_max = _param->_array_size_depth [context]; |
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[88] | 428 | |
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[98] | 429 | // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 430 | // // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 431 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 432 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[88] | 433 | |
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[98] | 434 | // context_state_t state = reg_STATE [context]; |
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[88] | 435 | |
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[98] | 436 | // // miss > excep > spr/sync |
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[101] | 437 | // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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[98] | 438 | // uint8_t priority1 = 2; // miss |
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[88] | 439 | |
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[98] | 440 | // // is_valid = can modify local information |
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| 441 | // // if context_state_ok : yes |
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| 442 | // // if context_state_ko : test the depth, and the priority of envent |
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[88] | 443 | |
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[98] | 444 | // bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 445 | // (depth1< depth0) or |
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| 446 | // ((depth1==depth0) and (priority1>priority0))); |
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[88] | 447 | |
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[98] | 448 | // if (is_valid) |
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| 449 | // { |
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| 450 | // // commit |
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| 451 | // Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); |
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| 452 | // reg_STATE [context] = CONTEXT_STATE_KO_MISS; |
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| 453 | // reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT |
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| 454 | // reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); |
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| 455 | // reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence |
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| 456 | // //reg_EVENT_ADDRESS_EEAR [context]; |
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| 457 | // reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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| 458 | // reg_EVENT_IS_DELAY_SLOT [context] = take; |
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| 459 | // reg_EVENT_IS_DS_TAKE [context] = take; |
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| 460 | // reg_EVENT_DEPTH [context] = depth; |
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| 461 | // } |
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| 462 | // } |
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| 463 | // } |
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[88] | 464 | |
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| 465 | // ------------------------------------------------------------------- |
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| 466 | // -----[ EVENT ]----------------------------------------------------- |
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| 467 | // ------------------------------------------------------------------- |
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| 468 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 469 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
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| 470 | { |
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[98] | 471 | log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); |
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[88] | 472 | // Write pc |
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| 473 | context_state_t state = reg_STATE [i]; |
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| 474 | |
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| 475 | switch (state) |
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| 476 | { |
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| 477 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 478 | { |
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| 479 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
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| 480 | break; |
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| 481 | } |
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| 482 | case CONTEXT_STATE_KO_MISS_ADDR : |
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[101] | 483 | // { |
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| 484 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
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| 485 | // break; |
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| 486 | // } |
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[88] | 487 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 488 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 489 | { |
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| 490 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 491 | break; |
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| 492 | } |
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| 493 | default : |
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| 494 | { |
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[83] | 495 | #ifdef DEBUG_TEST |
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[88] | 496 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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[83] | 497 | #endif |
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[88] | 498 | break; |
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| 499 | } |
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| 500 | } |
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| 501 | } |
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[83] | 502 | |
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[88] | 503 | // ------------------------------------------------------------------- |
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| 504 | // -----[ SPR_EVENT ]------------------------------------------------- |
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| 505 | // ------------------------------------------------------------------- |
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| 506 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 507 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
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| 508 | { |
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[98] | 509 | log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); |
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| 510 | |
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[88] | 511 | // Write spr |
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[83] | 512 | #ifdef DEBUG_TEST |
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[88] | 513 | context_state_t state = reg_STATE [i]; |
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| 514 | |
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| 515 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
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| 516 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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[83] | 517 | #endif |
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[88] | 518 | |
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| 519 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 520 | } |
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[83] | 521 | |
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[88] | 522 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 523 | { |
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| 524 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
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| 525 | |
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| 526 | if (reg_INTERRUPT_ENABLE [i]) |
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| 527 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
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| 528 | } |
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[83] | 529 | } |
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| 530 | |
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| 531 | #if DEBUG >= DEBUG_TRACE |
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| 532 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 533 | { |
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[88] | 534 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
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| 535 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
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| 536 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
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| 537 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
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| 538 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
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| 539 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
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| 540 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
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| 541 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
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| 542 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
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| 543 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
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[83] | 544 | } |
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| 545 | #endif |
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| 546 | |
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| 547 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 548 | end_cycle (); |
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| 549 | #endif |
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| 550 | |
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| 551 | log_end(Context_State,FUNCTION); |
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| 552 | }; |
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| 553 | |
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| 554 | }; // end namespace context_state |
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| 555 | }; // end namespace front_end |
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| 556 | }; // end namespace multi_front_end |
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| 557 | }; // end namespace core |
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| 558 | |
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| 559 | }; // end namespace behavioural |
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| 560 | }; // end namespace morpheo |
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| 561 | #endif |
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