[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_transition.cpp 123 2009-06-08 20:43:30Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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[123] | 18 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_ALL |
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| 19 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_DECODE |
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| 20 | #define MANAGE_EVENT MANAGE_EVENT_NO_WAIT |
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[83] | 21 | |
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[111] | 22 | #define get_priority(x) \ |
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| 23 | (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or \ |
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[123] | 24 | (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or \ |
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[111] | 25 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or \ |
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| 26 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND ) or \ |
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| 27 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?3: \ |
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| 28 | (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \ |
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| 29 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \ |
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| 30 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?2: \ |
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| 31 | ((state == EVENT_TYPE_EXCEPTION)?1: \ |
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| 32 | 0))) |
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| 33 | |
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[83] | 34 | #undef FUNCTION |
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| 35 | #define FUNCTION "Context_State::transition" |
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| 36 | void Context_State::transition (void) |
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| 37 | { |
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| 38 | log_begin(Context_State,FUNCTION); |
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[88] | 39 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 40 | |
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| 41 | if (PORT_READ(in_NRESET) == 0) |
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| 42 | { |
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[88] | 43 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 44 | { |
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| 45 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 46 | reg_INTERRUPT_ENABLE [i] = 0; |
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[123] | 47 | reg_EVENT_DEPTH [i] = 0; // unacessary |
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[88] | 48 | } |
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[83] | 49 | } |
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| 50 | else |
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| 51 | { |
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[88] | 52 | // ------------------------------------------------------------------- |
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[101] | 53 | // -----[ next state ]------------------------------------------------ |
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| 54 | // ------------------------------------------------------------------- |
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| 55 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 56 | { |
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| 57 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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| 58 | |
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[122] | 59 | Tcounter_t inst_commit_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]); |
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| 60 | // Tcounter_t inst_commit_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]); |
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| 61 | Tcounter_t inst_decod_all = PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 62 | Tcounter_t inst_all = inst_commit_all + inst_decod_all; |
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| 63 | // Tcounter_t inst_mem = inst_commit_mem + inst_decod_all; |
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[123] | 64 | bool condition = ( (MANAGE_EVENT == MANAGE_EVENT_WAIT_ALL )?(inst_all == 0): |
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| 65 | ((MANAGE_EVENT == MANAGE_EVENT_WAIT_DECODE)?(inst_decod_all == 0): |
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| 66 | true)); |
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[101] | 67 | |
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| 68 | context_state_t state = reg_STATE [i]; |
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| 69 | |
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| 70 | switch (state) |
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| 71 | { |
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| 72 | case CONTEXT_STATE_OK : |
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| 73 | { |
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| 74 | // nothing, wait an event |
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| 75 | break; |
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| 76 | } |
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| 77 | case CONTEXT_STATE_KO_EXCEP : |
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| 78 | { |
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| 79 | // Wait end of all instruction |
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| 80 | if (inst_all == 0) |
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[122] | 81 | // if (inst_decod_all == 0) |
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[101] | 82 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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| 83 | break; |
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| 84 | } |
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| 85 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 86 | { |
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| 87 | // nothing, wait the update of internal register (pc) |
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| 88 | break; |
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| 89 | } |
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[111] | 90 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
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| 91 | { |
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| 92 | // nothing : wait end of update upt |
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| 93 | break; |
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| 94 | } |
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[105] | 95 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
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[101] | 96 | { |
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[123] | 97 | if (condition) |
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[122] | 98 | // state = CONTEXT_STATE_OK; |
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[105] | 99 | state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[101] | 100 | break; |
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| 101 | } |
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[105] | 102 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : |
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| 103 | { |
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| 104 | // Wait end of all instruction |
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[123] | 105 | if (condition) |
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[105] | 106 | state = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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| 107 | |
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| 108 | break; |
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| 109 | } |
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[101] | 110 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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| 111 | { |
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| 112 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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| 113 | break; |
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| 114 | } |
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[105] | 115 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
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[101] | 116 | { |
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| 117 | // nothing, wait the update of internal register (pc) |
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| 118 | break; |
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| 119 | } |
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[105] | 120 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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| 121 | { |
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| 122 | // nothing, wait the update of internal register (pc) |
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| 123 | break; |
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| 124 | } |
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[111] | 125 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : |
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[108] | 126 | { |
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[111] | 127 | // nothing : wait end of update upt |
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| 128 | break; |
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| 129 | } |
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| 130 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
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| 131 | { |
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[108] | 132 | // nothing, wait the update of internal register (pc) |
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| 133 | break; |
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| 134 | } |
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[111] | 135 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
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| 136 | { |
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| 137 | // Wait end of all instruction |
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[123] | 138 | if (condition) |
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[111] | 139 | // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) |
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| 140 | state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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| 141 | break; |
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| 142 | } |
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[101] | 143 | // case CONTEXT_STATE_KO_PSYNC : |
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| 144 | // { |
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| 145 | // // Wait end of all instruction |
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| 146 | // if (inst_all == 0) |
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| 147 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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| 148 | // break; |
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| 149 | // } |
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| 150 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 151 | { |
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| 152 | // nothing, wait end of flush (ifetch) |
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| 153 | if (inst_all == 0) |
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| 154 | // state = CONTEXT_STATE_KO_PSYNC_ADDR; |
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| 155 | state = CONTEXT_STATE_OK; |
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| 156 | |
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| 157 | break; |
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| 158 | } |
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| 159 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 160 | { |
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| 161 | // nothing, wait the pc write |
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| 162 | break; |
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| 163 | } |
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| 164 | // case CONTEXT_STATE_KO_CSYNC : |
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| 165 | // { |
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| 166 | // // Wait end of all instruction |
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| 167 | // if (inst_all == 0) |
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| 168 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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| 169 | // break; |
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| 170 | // } |
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| 171 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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| 172 | { |
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| 173 | // nothing, wait end of flush (all internal structure) |
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| 174 | if (inst_all == 0) |
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| 175 | state = CONTEXT_STATE_KO_CSYNC_ADDR; |
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| 176 | break; |
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| 177 | } |
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| 178 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 179 | { |
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| 180 | // nothing, wait the pc write |
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| 181 | break; |
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| 182 | } |
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| 183 | // case CONTEXT_STATE_KO_MSYNC : |
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| 184 | // { |
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| 185 | // // Wait end of memory instruction |
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| 186 | // if (inst_mem == 0) |
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| 187 | // state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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| 188 | // break; |
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| 189 | // } |
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| 190 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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| 191 | // { |
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| 192 | // // Wait the msync issue |
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| 193 | // if (inst_mem != 0) |
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| 194 | // state = CONTEXT_STATE_KO_MSYNC_EXEC; |
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| 195 | // break; |
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| 196 | // } |
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| 197 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
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| 198 | { |
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| 199 | // Wait the end of msync |
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| 200 | if (inst_all == 0) |
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| 201 | state = CONTEXT_STATE_OK; |
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| 202 | break; |
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| 203 | } |
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| 204 | // case CONTEXT_STATE_KO_SPR : |
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| 205 | // { |
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| 206 | // // Wait end of all instruction |
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| 207 | // if (inst_all == 0) |
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| 208 | // state = CONTEXT_STATE_KO_SPR_ISSUE; |
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| 209 | // break; |
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| 210 | // } |
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| 211 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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| 212 | // { |
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| 213 | // // Wait the spr_access issue |
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| 214 | // if (inst_all != 0) |
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| 215 | // state = CONTEXT_STATE_KO_SPR_EXEC; |
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| 216 | // break; |
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| 217 | // } |
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| 218 | case CONTEXT_STATE_KO_SPR_EXEC : |
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| 219 | { |
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| 220 | // Wait the spr_access execution |
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| 221 | if (inst_all == 0) |
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| 222 | state = CONTEXT_STATE_OK; |
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| 223 | break; |
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| 224 | } |
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| 225 | |
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| 226 | default : |
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| 227 | { |
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| 228 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
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| 229 | } |
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| 230 | } |
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| 231 | reg_STATE [i] = state; |
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| 232 | } |
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| 233 | |
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| 234 | // ------------------------------------------------------------------- |
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[111] | 235 | // -----[ EVENT ]----------------------------------------------------- |
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| 236 | // ------------------------------------------------------------------- |
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| 237 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 238 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
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| 239 | { |
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| 240 | log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); |
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| 241 | // Write pc |
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| 242 | context_state_t state = reg_STATE [i]; |
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| 243 | |
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| 244 | switch (state) |
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| 245 | { |
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| 246 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 247 | { |
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| 248 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
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| 249 | break; |
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| 250 | } |
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| 251 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: |
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| 252 | |
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| 253 | // { |
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| 254 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
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| 255 | // break; |
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| 256 | // } |
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| 257 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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| 258 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 259 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 260 | { |
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| 261 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 262 | break; |
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| 263 | } |
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| 264 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: |
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| 265 | { |
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| 266 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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| 267 | break; |
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| 268 | } |
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| 269 | default : |
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| 270 | { |
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| 271 | #ifdef DEBUG_TEST |
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| 272 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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| 273 | #endif |
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| 274 | break; |
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| 275 | } |
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| 276 | } |
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| 277 | } |
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| 278 | |
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| 279 | // ------------------------------------------------------------------- |
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[88] | 280 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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| 281 | // ------------------------------------------------------------------- |
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| 282 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 283 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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| 284 | { |
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[98] | 285 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); |
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| 286 | |
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[88] | 287 | context_state_t state = reg_STATE [i]; |
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[83] | 288 | |
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[98] | 289 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; |
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[88] | 290 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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| 291 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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[106] | 292 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; |
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[88] | 293 | |
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[106] | 294 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 295 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 296 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 297 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 298 | |
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[111] | 299 | // priority : miss_load > miss_branch > excep > spr/sync |
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| 300 | uint8_t priority0 = get_priority(state); |
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[88] | 301 | uint8_t priority1 = 2; // miss |
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[83] | 302 | |
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[88] | 303 | // is_valid = can modify local information |
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| 304 | // if context_state_ok : yes |
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[98] | 305 | // if context_state_ko : test the depth, and the priority of event |
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[88] | 306 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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[111] | 307 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or |
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| 308 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or |
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[88] | 309 | (depth1< depth0) or |
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[98] | 310 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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[83] | 311 | |
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[111] | 312 | #ifdef DEBUG_TEST |
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| 313 | if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and |
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| 314 | (depth0 != depth1)) |
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| 315 | throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); |
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| 316 | #endif |
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| 317 | |
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[123] | 318 | log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str()); |
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[106] | 319 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 320 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 321 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 322 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 323 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 324 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 325 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 326 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 327 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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| 328 | |
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[88] | 329 | if (is_valid) |
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| 330 | { |
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[105] | 331 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[111] | 332 | |
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| 333 | if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) |
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| 334 | { |
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| 335 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
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| 336 | } |
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| 337 | else |
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| 338 | { |
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[119] | 339 | Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]); |
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| 340 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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[111] | 341 | |
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[119] | 342 | log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val ); |
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| 343 | log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue); |
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| 344 | |
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| 345 | if (can_continue) |
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| 346 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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| 347 | else |
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| 348 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; |
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| 349 | |
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| 350 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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| 351 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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| 352 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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| 353 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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| 354 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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| 355 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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| 356 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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| 357 | reg_EVENT_DEPTH [i] = depth; |
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| 358 | reg_EVENT_FLUSH_ONLY [i] = can_continue; |
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[111] | 359 | } |
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| 360 | } |
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| 361 | } |
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| 362 | |
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| 363 | // ------------------------------------------------------------------- |
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| 364 | // -----[ BRANCH_COMPLETE ]---------------------------------------------- |
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| 365 | // ------------------------------------------------------------------- |
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| 366 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 367 | if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i] |
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| 368 | and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
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| 369 | { |
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| 370 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
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| 371 | |
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[117] | 372 | Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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[111] | 373 | |
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[117] | 374 | context_state_t state = reg_STATE [context_id]; |
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| 375 | |
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[111] | 376 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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[117] | 377 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context_id]; |
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| 378 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context_id]):0; |
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| 379 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context_id]; |
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[111] | 380 | |
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| 381 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 382 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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[119] | 383 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 384 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[111] | 385 | |
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| 386 | // priority : miss_load > miss_branch > excep > spr/sync |
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| 387 | uint8_t priority0 = get_priority(state); |
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| 388 | uint8_t priority1 = 2; // miss |
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| 389 | |
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| 390 | // is_valid = can modify local information |
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| 391 | // if context_state_ok : yes |
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| 392 | // if context_state_ko : test the depth, and the priority of event |
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| 393 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 394 | (depth1< depth0) or |
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| 395 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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| 396 | |
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[117] | 397 | log_printf(TRACE,Context_State,FUNCTION," * context_id: %d",context_id); |
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[111] | 398 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 399 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 400 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 401 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 402 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 403 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 404 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 405 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 406 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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| 407 | |
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| 408 | if (is_valid) |
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| 409 | { |
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[119] | 410 | // reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
---|
| 411 | reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE; |
---|
| 412 | reg_EVENT_DEPTH [context_id] = depth; |
---|
| 413 | reg_EVENT_FLUSH_ONLY [context_id] = false; |
---|
[88] | 414 | } |
---|
| 415 | } |
---|
| 416 | |
---|
| 417 | // ------------------------------------------------------------------- |
---|
| 418 | // -----[ DECOD_EVENT ]----------------------------------------------- |
---|
| 419 | // ------------------------------------------------------------------- |
---|
[83] | 420 | |
---|
[88] | 421 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
---|
| 422 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
---|
| 423 | { |
---|
[98] | 424 | log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); |
---|
| 425 | |
---|
[88] | 426 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
---|
| 427 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
---|
| 428 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
---|
| 429 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
---|
[106] | 430 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
---|
[88] | 431 | |
---|
[106] | 432 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 433 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
| 434 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
| 435 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
[83] | 436 | |
---|
[88] | 437 | context_state_t state = reg_STATE [context]; |
---|
| 438 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
---|
| 439 | |
---|
[111] | 440 | // miss_load > miss_branch > excep > spr/sync |
---|
| 441 | uint8_t priority0 = get_priority(state); |
---|
[88] | 442 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; |
---|
[83] | 443 | |
---|
[88] | 444 | // is_valid = can modify local information |
---|
| 445 | // if context_state_ok : yes |
---|
| 446 | // if context_state_ko : test the depth, and the priority of envent |
---|
[83] | 447 | |
---|
[88] | 448 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
| 449 | (depth1< depth0) or |
---|
[105] | 450 | ((depth1==depth0) and (priority1>=priority0))); |
---|
[83] | 451 | |
---|
[106] | 452 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
| 453 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 454 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 455 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 456 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 457 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 458 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 459 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
| 460 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 461 | |
---|
[88] | 462 | if (is_valid) |
---|
| 463 | { |
---|
[101] | 464 | log_printf(TRACE,Context_State,FUNCTION," * is_valid"); |
---|
| 465 | |
---|
[88] | 466 | // decod : |
---|
| 467 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
---|
| 468 | context_state_t state_next = state; |
---|
| 469 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
---|
| 470 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
---|
[83] | 471 | |
---|
[88] | 472 | switch (type) |
---|
| 473 | { |
---|
| 474 | case EVENT_TYPE_EXCEPTION : |
---|
| 475 | { |
---|
[101] | 476 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); |
---|
| 477 | |
---|
[88] | 478 | state_next = CONTEXT_STATE_KO_EXCEP; |
---|
[83] | 479 | |
---|
[88] | 480 | break; |
---|
| 481 | } |
---|
| 482 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 483 | { |
---|
[101] | 484 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); |
---|
| 485 | |
---|
| 486 | // state_next = CONTEXT_STATE_KO_SPR ; |
---|
| 487 | state_next = CONTEXT_STATE_KO_SPR_EXEC; |
---|
[88] | 488 | address++; // take next address |
---|
[101] | 489 | // if (is_delay_slot) |
---|
| 490 | // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
---|
[88] | 491 | break; |
---|
| 492 | } |
---|
| 493 | case EVENT_TYPE_MSYNC : |
---|
| 494 | { |
---|
[101] | 495 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); |
---|
| 496 | |
---|
| 497 | // state_next = CONTEXT_STATE_KO_MSYNC; |
---|
| 498 | state_next = CONTEXT_STATE_KO_MSYNC_EXEC; |
---|
[88] | 499 | address++; // take next address |
---|
[101] | 500 | // if (is_delay_slot) |
---|
| 501 | // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); |
---|
[88] | 502 | break; |
---|
| 503 | } |
---|
| 504 | case EVENT_TYPE_PSYNC : |
---|
| 505 | { |
---|
[101] | 506 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); |
---|
| 507 | |
---|
| 508 | // state_next = CONTEXT_STATE_KO_PSYNC; |
---|
| 509 | state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; |
---|
[88] | 510 | address++; // take next address |
---|
| 511 | if (is_delay_slot) |
---|
[101] | 512 | throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); |
---|
[88] | 513 | break; |
---|
| 514 | } |
---|
| 515 | case EVENT_TYPE_CSYNC : |
---|
| 516 | { |
---|
[101] | 517 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); |
---|
| 518 | |
---|
| 519 | // state_next = CONTEXT_STATE_KO_CSYNC; |
---|
| 520 | state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; |
---|
[88] | 521 | address++; // take next address |
---|
| 522 | if (is_delay_slot) |
---|
[101] | 523 | throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); |
---|
[88] | 524 | break; |
---|
| 525 | } |
---|
| 526 | case EVENT_TYPE_NONE : |
---|
[105] | 527 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 528 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 529 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 530 | default : |
---|
| 531 | { |
---|
| 532 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
---|
| 533 | } |
---|
| 534 | } |
---|
[83] | 535 | |
---|
[88] | 536 | reg_STATE [context] = state_next; |
---|
| 537 | reg_EVENT_ADDRESS [context] = address; |
---|
| 538 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
---|
| 539 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
---|
| 540 | //reg_EVENT_ADDRESS_EEAR [context] |
---|
| 541 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
---|
| 542 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
---|
| 543 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
| 544 | reg_EVENT_DEPTH [context] = depth; |
---|
[119] | 545 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
[88] | 546 | } |
---|
| 547 | } |
---|
[83] | 548 | |
---|
[88] | 549 | // ------------------------------------------------------------------- |
---|
| 550 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
---|
| 551 | // ------------------------------------------------------------------- |
---|
[83] | 552 | |
---|
[88] | 553 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
---|
| 554 | { |
---|
[98] | 555 | log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); |
---|
| 556 | |
---|
[88] | 557 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
---|
| 558 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
---|
[111] | 559 | // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
---|
| 560 | // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
---|
| 561 | // Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
---|
[88] | 562 | |
---|
[111] | 563 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 564 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
| 565 | // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
| 566 | // // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
[83] | 567 | |
---|
[88] | 568 | context_state_t state = reg_STATE [context]; |
---|
| 569 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
---|
| 570 | |
---|
[111] | 571 | // // miss > excep > spr/sync |
---|
| 572 | // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or |
---|
| 573 | // (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or |
---|
| 574 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or |
---|
| 575 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or |
---|
| 576 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ) or |
---|
| 577 | // (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or |
---|
| 578 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
---|
| 579 | // uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) |
---|
[88] | 580 | |
---|
[111] | 581 | // // is_valid = can modify local information |
---|
| 582 | // // if context_state_ok : yes |
---|
| 583 | // // if context_state_ko : test the depth, and the priority of envent |
---|
[88] | 584 | |
---|
[111] | 585 | // bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
| 586 | // (depth1< depth0) or |
---|
| 587 | // ((depth1==depth0) and (priority1>=priority0))); |
---|
[88] | 588 | |
---|
[111] | 589 | // if commit send an event, also they have not yet event previous this instruction |
---|
| 590 | bool is_valid = true; |
---|
| 591 | |
---|
[106] | 592 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
[111] | 593 | // log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 594 | // log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 595 | // log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 596 | // log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 597 | // log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 598 | // log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 599 | // log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
[106] | 600 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 601 | |
---|
[88] | 602 | if (is_valid) |
---|
| 603 | { |
---|
| 604 | // commit |
---|
| 605 | // type : exception |
---|
| 606 | context_state_t state_next = state; |
---|
| 607 | switch (type) |
---|
| 608 | { |
---|
[105] | 609 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
---|
[108] | 610 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 611 | { |
---|
| 612 | // Test if previous branch occure |
---|
[111] | 613 | switch (state) |
---|
| 614 | { |
---|
| 615 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
| 616 | { |
---|
| 617 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE; |
---|
| 618 | break; |
---|
| 619 | } |
---|
| 620 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
| 621 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
---|
| 622 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
| 623 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
---|
| 624 | { |
---|
| 625 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
---|
| 626 | break; |
---|
| 627 | } |
---|
| 628 | default : |
---|
| 629 | { |
---|
| 630 | state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; |
---|
| 631 | break; |
---|
| 632 | } |
---|
| 633 | } |
---|
[123] | 634 | |
---|
| 635 | depth = (depth+1)%_param->_nb_inst_branch_speculated[context]; |
---|
| 636 | |
---|
[108] | 637 | break; |
---|
| 638 | } |
---|
[105] | 639 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 640 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 641 | case EVENT_TYPE_MSYNC : |
---|
| 642 | case EVENT_TYPE_PSYNC : |
---|
| 643 | case EVENT_TYPE_CSYNC : |
---|
| 644 | case EVENT_TYPE_NONE : |
---|
| 645 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 646 | default : |
---|
| 647 | { |
---|
| 648 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
---|
| 649 | } |
---|
| 650 | } |
---|
| 651 | reg_STATE [context] = state_next; |
---|
| 652 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
---|
| 653 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
---|
[105] | 654 | reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); |
---|
[88] | 655 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
---|
| 656 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
---|
| 657 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
---|
[105] | 658 | reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
[88] | 659 | reg_EVENT_DEPTH [context] = depth; |
---|
[119] | 660 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
[88] | 661 | } |
---|
| 662 | } |
---|
| 663 | |
---|
| 664 | // ------------------------------------------------------------------- |
---|
| 665 | // -----[ SPR_EVENT ]------------------------------------------------- |
---|
| 666 | // ------------------------------------------------------------------- |
---|
| 667 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 668 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
---|
| 669 | { |
---|
[98] | 670 | log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); |
---|
| 671 | |
---|
[88] | 672 | // Write spr |
---|
[83] | 673 | #ifdef DEBUG_TEST |
---|
[88] | 674 | context_state_t state = reg_STATE [i]; |
---|
| 675 | |
---|
| 676 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
---|
| 677 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
---|
[83] | 678 | #endif |
---|
[88] | 679 | |
---|
| 680 | reg_STATE [i] = CONTEXT_STATE_OK; |
---|
| 681 | } |
---|
[83] | 682 | |
---|
[88] | 683 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 684 | { |
---|
| 685 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
| 686 | |
---|
| 687 | if (reg_INTERRUPT_ENABLE [i]) |
---|
| 688 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
| 689 | } |
---|
[83] | 690 | } |
---|
| 691 | |
---|
[120] | 692 | |
---|
| 693 | #ifdef STATISTICS |
---|
| 694 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 695 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 696 | switch(reg_STATE[i]) |
---|
| 697 | { |
---|
| 698 | case CONTEXT_STATE_OK : (*_stat_nb_cycle_state_ok [i])++; break; |
---|
| 699 | |
---|
| 700 | case CONTEXT_STATE_KO_EXCEP : |
---|
| 701 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
---|
| 702 | case CONTEXT_STATE_KO_EXCEP_SPR : (*_stat_nb_cycle_state_ko_excep [i])++; break; |
---|
| 703 | |
---|
| 704 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
| 705 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
| 706 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_branch [i])++; break; |
---|
| 707 | |
---|
| 708 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
---|
| 709 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : (*_stat_nb_cycle_state_ko_miss_load [i])++; break; |
---|
| 710 | |
---|
| 711 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE: |
---|
| 712 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
| 713 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_load_and_branch [i])++; break; |
---|
| 714 | |
---|
| 715 | // case CONTEXT_STATE_KO_MSYNC : |
---|
| 716 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
---|
| 717 | case CONTEXT_STATE_KO_MSYNC_EXEC : (*_stat_nb_cycle_state_ko_msync [i])++; break; |
---|
| 718 | |
---|
| 719 | // case CONTEXT_STATE_KO_PSYNC : |
---|
| 720 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
---|
| 721 | case CONTEXT_STATE_KO_PSYNC_ADDR : (*_stat_nb_cycle_state_ko_psync [i])++; break; |
---|
| 722 | |
---|
| 723 | // case CONTEXT_STATE_KO_CSYNC : |
---|
| 724 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
---|
| 725 | case CONTEXT_STATE_KO_CSYNC_ADDR : (*_stat_nb_cycle_state_ko_csync [i])++; break; |
---|
| 726 | |
---|
| 727 | // case CONTEXT_STATE_KO_SPR : |
---|
| 728 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
---|
| 729 | case CONTEXT_STATE_KO_SPR_EXEC : (*_stat_nb_cycle_state_ko_spr [i])++; break; |
---|
| 730 | } |
---|
| 731 | #endif |
---|
| 732 | |
---|
| 733 | |
---|
| 734 | |
---|
[83] | 735 | #if DEBUG >= DEBUG_TRACE |
---|
| 736 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 737 | { |
---|
[88] | 738 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
---|
| 739 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
---|
| 740 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
---|
| 741 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
---|
| 742 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
---|
| 743 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
---|
| 744 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
---|
| 745 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
---|
| 746 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
---|
| 747 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
---|
[119] | 748 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_FLUSH_ONLY : %d" ,reg_EVENT_FLUSH_ONLY [i]); |
---|
[83] | 749 | } |
---|
| 750 | #endif |
---|
| 751 | |
---|
| 752 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 753 | end_cycle (); |
---|
| 754 | #endif |
---|
| 755 | |
---|
| 756 | log_end(Context_State,FUNCTION); |
---|
| 757 | }; |
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| 758 | |
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| 759 | }; // end namespace context_state |
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| 760 | }; // end namespace front_end |
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| 761 | }; // end namespace multi_front_end |
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| 762 | }; // end namespace core |
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| 763 | |
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| 764 | }; // end namespace behavioural |
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| 765 | }; // end namespace morpheo |
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| 766 | #endif |
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