[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_transition.cpp 124 2009-06-17 12:11:25Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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[123] | 18 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_ALL |
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| 19 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_DECODE |
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| 20 | #define MANAGE_EVENT MANAGE_EVENT_NO_WAIT |
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[83] | 21 | |
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[124] | 22 | #define PRIORITY_MISS_LOAD 3 |
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| 23 | #define PRIORITY_MISS_BRANCH 2 |
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| 24 | #define PRIORITY_EXCEPTION 1 |
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| 25 | #define PRIORITY_NONE 0 |
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| 26 | |
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[111] | 27 | #define get_priority(x) \ |
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| 28 | (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or \ |
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[123] | 29 | (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or \ |
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[111] | 30 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or \ |
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| 31 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND ) or \ |
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[124] | 32 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?PRIORITY_MISS_LOAD: \ |
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[111] | 33 | (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \ |
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| 34 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \ |
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[124] | 35 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?PRIORITY_MISS_BRANCH: \ |
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| 36 | ((state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION: \ |
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[111] | 37 | 0))) |
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| 38 | |
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[83] | 39 | #undef FUNCTION |
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| 40 | #define FUNCTION "Context_State::transition" |
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| 41 | void Context_State::transition (void) |
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| 42 | { |
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| 43 | log_begin(Context_State,FUNCTION); |
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[88] | 44 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 45 | |
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| 46 | if (PORT_READ(in_NRESET) == 0) |
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| 47 | { |
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[88] | 48 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 49 | { |
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| 50 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 51 | reg_INTERRUPT_ENABLE [i] = 0; |
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[123] | 52 | reg_EVENT_DEPTH [i] = 0; // unacessary |
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[88] | 53 | } |
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[83] | 54 | } |
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| 55 | else |
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| 56 | { |
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[88] | 57 | // ------------------------------------------------------------------- |
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[101] | 58 | // -----[ next state ]------------------------------------------------ |
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| 59 | // ------------------------------------------------------------------- |
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| 60 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 61 | { |
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| 62 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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| 63 | |
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[122] | 64 | Tcounter_t inst_commit_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]); |
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| 65 | // Tcounter_t inst_commit_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]); |
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| 66 | Tcounter_t inst_decod_all = PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 67 | Tcounter_t inst_all = inst_commit_all + inst_decod_all; |
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| 68 | // Tcounter_t inst_mem = inst_commit_mem + inst_decod_all; |
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[123] | 69 | bool condition = ( (MANAGE_EVENT == MANAGE_EVENT_WAIT_ALL )?(inst_all == 0): |
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| 70 | ((MANAGE_EVENT == MANAGE_EVENT_WAIT_DECODE)?(inst_decod_all == 0): |
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| 71 | true)); |
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[101] | 72 | |
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| 73 | context_state_t state = reg_STATE [i]; |
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| 74 | |
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| 75 | switch (state) |
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| 76 | { |
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| 77 | case CONTEXT_STATE_OK : |
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| 78 | { |
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| 79 | // nothing, wait an event |
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| 80 | break; |
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| 81 | } |
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| 82 | case CONTEXT_STATE_KO_EXCEP : |
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| 83 | { |
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| 84 | // Wait end of all instruction |
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| 85 | if (inst_all == 0) |
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[122] | 86 | // if (inst_decod_all == 0) |
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[101] | 87 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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| 88 | break; |
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| 89 | } |
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| 90 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 91 | { |
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| 92 | // nothing, wait the update of internal register (pc) |
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| 93 | break; |
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| 94 | } |
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[111] | 95 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
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| 96 | { |
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| 97 | // nothing : wait end of update upt |
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| 98 | break; |
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| 99 | } |
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[105] | 100 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
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[101] | 101 | { |
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[123] | 102 | if (condition) |
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[122] | 103 | // state = CONTEXT_STATE_OK; |
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[105] | 104 | state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[101] | 105 | break; |
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| 106 | } |
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[105] | 107 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : |
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| 108 | { |
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| 109 | // Wait end of all instruction |
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[123] | 110 | if (condition) |
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[105] | 111 | state = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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| 112 | |
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| 113 | break; |
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| 114 | } |
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[101] | 115 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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| 116 | { |
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| 117 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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| 118 | break; |
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| 119 | } |
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[105] | 120 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
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[101] | 121 | { |
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| 122 | // nothing, wait the update of internal register (pc) |
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| 123 | break; |
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| 124 | } |
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[105] | 125 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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| 126 | { |
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| 127 | // nothing, wait the update of internal register (pc) |
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| 128 | break; |
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| 129 | } |
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[111] | 130 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : |
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[108] | 131 | { |
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[111] | 132 | // nothing : wait end of update upt |
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| 133 | break; |
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| 134 | } |
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| 135 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
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| 136 | { |
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[108] | 137 | // nothing, wait the update of internal register (pc) |
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| 138 | break; |
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| 139 | } |
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[111] | 140 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
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| 141 | { |
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| 142 | // Wait end of all instruction |
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[123] | 143 | if (condition) |
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[111] | 144 | // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) |
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| 145 | state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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| 146 | break; |
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| 147 | } |
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[101] | 148 | // case CONTEXT_STATE_KO_PSYNC : |
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| 149 | // { |
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| 150 | // // Wait end of all instruction |
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| 151 | // if (inst_all == 0) |
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| 152 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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| 153 | // break; |
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| 154 | // } |
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| 155 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 156 | { |
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| 157 | // nothing, wait end of flush (ifetch) |
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| 158 | if (inst_all == 0) |
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| 159 | // state = CONTEXT_STATE_KO_PSYNC_ADDR; |
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| 160 | state = CONTEXT_STATE_OK; |
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| 161 | |
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| 162 | break; |
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| 163 | } |
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| 164 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 165 | { |
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| 166 | // nothing, wait the pc write |
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| 167 | break; |
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| 168 | } |
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| 169 | // case CONTEXT_STATE_KO_CSYNC : |
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| 170 | // { |
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| 171 | // // Wait end of all instruction |
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| 172 | // if (inst_all == 0) |
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| 173 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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| 174 | // break; |
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| 175 | // } |
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| 176 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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| 177 | { |
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| 178 | // nothing, wait end of flush (all internal structure) |
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| 179 | if (inst_all == 0) |
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| 180 | state = CONTEXT_STATE_KO_CSYNC_ADDR; |
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| 181 | break; |
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| 182 | } |
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| 183 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 184 | { |
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| 185 | // nothing, wait the pc write |
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| 186 | break; |
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| 187 | } |
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| 188 | // case CONTEXT_STATE_KO_MSYNC : |
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| 189 | // { |
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| 190 | // // Wait end of memory instruction |
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| 191 | // if (inst_mem == 0) |
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| 192 | // state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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| 193 | // break; |
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| 194 | // } |
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| 195 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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| 196 | // { |
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| 197 | // // Wait the msync issue |
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| 198 | // if (inst_mem != 0) |
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| 199 | // state = CONTEXT_STATE_KO_MSYNC_EXEC; |
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| 200 | // break; |
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| 201 | // } |
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| 202 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
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| 203 | { |
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| 204 | // Wait the end of msync |
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| 205 | if (inst_all == 0) |
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| 206 | state = CONTEXT_STATE_OK; |
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| 207 | break; |
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| 208 | } |
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| 209 | // case CONTEXT_STATE_KO_SPR : |
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| 210 | // { |
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| 211 | // // Wait end of all instruction |
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| 212 | // if (inst_all == 0) |
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| 213 | // state = CONTEXT_STATE_KO_SPR_ISSUE; |
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| 214 | // break; |
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| 215 | // } |
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| 216 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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| 217 | // { |
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| 218 | // // Wait the spr_access issue |
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| 219 | // if (inst_all != 0) |
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| 220 | // state = CONTEXT_STATE_KO_SPR_EXEC; |
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| 221 | // break; |
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| 222 | // } |
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| 223 | case CONTEXT_STATE_KO_SPR_EXEC : |
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| 224 | { |
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| 225 | // Wait the spr_access execution |
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| 226 | if (inst_all == 0) |
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| 227 | state = CONTEXT_STATE_OK; |
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| 228 | break; |
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| 229 | } |
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| 230 | |
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| 231 | default : |
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| 232 | { |
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| 233 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
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| 234 | } |
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| 235 | } |
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| 236 | reg_STATE [i] = state; |
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| 237 | } |
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| 238 | |
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| 239 | // ------------------------------------------------------------------- |
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[111] | 240 | // -----[ EVENT ]----------------------------------------------------- |
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| 241 | // ------------------------------------------------------------------- |
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| 242 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 243 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
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| 244 | { |
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| 245 | log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); |
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| 246 | // Write pc |
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| 247 | context_state_t state = reg_STATE [i]; |
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| 248 | |
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| 249 | switch (state) |
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| 250 | { |
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| 251 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 252 | { |
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| 253 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
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| 254 | break; |
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| 255 | } |
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| 256 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: |
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| 257 | |
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| 258 | // { |
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| 259 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
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| 260 | // break; |
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| 261 | // } |
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| 262 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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| 263 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 264 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 265 | { |
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| 266 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 267 | break; |
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| 268 | } |
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| 269 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: |
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| 270 | { |
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| 271 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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| 272 | break; |
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| 273 | } |
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| 274 | default : |
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| 275 | { |
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| 276 | #ifdef DEBUG_TEST |
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| 277 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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| 278 | #endif |
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| 279 | break; |
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| 280 | } |
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| 281 | } |
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| 282 | } |
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| 283 | |
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| 284 | // ------------------------------------------------------------------- |
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[88] | 285 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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| 286 | // ------------------------------------------------------------------- |
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| 287 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 288 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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| 289 | { |
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[98] | 290 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); |
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| 291 | |
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[88] | 292 | context_state_t state = reg_STATE [i]; |
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[83] | 293 | |
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[98] | 294 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; |
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[88] | 295 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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| 296 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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[106] | 297 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; |
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[88] | 298 | |
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[106] | 299 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 300 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 301 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 302 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 303 | |
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[111] | 304 | // priority : miss_load > miss_branch > excep > spr/sync |
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| 305 | uint8_t priority0 = get_priority(state); |
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[124] | 306 | uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss |
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[83] | 307 | |
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[88] | 308 | // is_valid = can modify local information |
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| 309 | // if context_state_ok : yes |
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[98] | 310 | // if context_state_ko : test the depth, and the priority of event |
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[88] | 311 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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[111] | 312 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or |
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[124] | 313 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or |
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[88] | 314 | (depth1< depth0) or |
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[98] | 315 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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[83] | 316 | |
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[124] | 317 | bool is_invalid = priority0 == PRIORITY_MISS_LOAD; |
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| 318 | |
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[111] | 319 | #ifdef DEBUG_TEST |
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| 320 | if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and |
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| 321 | (depth0 != depth1)) |
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| 322 | throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); |
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| 323 | #endif |
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| 324 | |
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[123] | 325 | log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str()); |
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[106] | 326 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 327 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 328 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 329 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 330 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 331 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 332 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 333 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 334 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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| 335 | |
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[124] | 336 | if (is_valid and not is_invalid) |
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[88] | 337 | { |
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[105] | 338 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[111] | 339 | |
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| 340 | if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) |
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| 341 | { |
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[124] | 342 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
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| 343 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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| 344 | // #else |
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[111] | 345 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
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[124] | 346 | // #endif |
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[111] | 347 | } |
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| 348 | else |
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| 349 | { |
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[119] | 350 | Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]); |
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| 351 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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[111] | 352 | |
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[119] | 353 | log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val ); |
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| 354 | log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue); |
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| 355 | |
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| 356 | if (can_continue) |
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| 357 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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| 358 | else |
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[124] | 359 | { |
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| 360 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
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| 361 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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| 362 | // #else |
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| 363 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; |
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| 364 | // #endif |
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| 365 | } |
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[119] | 366 | |
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| 367 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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| 368 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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| 369 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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| 370 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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| 371 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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| 372 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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| 373 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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| 374 | reg_EVENT_DEPTH [i] = depth; |
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| 375 | reg_EVENT_FLUSH_ONLY [i] = can_continue; |
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[111] | 376 | } |
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| 377 | } |
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| 378 | } |
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| 379 | |
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| 380 | // ------------------------------------------------------------------- |
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| 381 | // -----[ BRANCH_COMPLETE ]---------------------------------------------- |
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| 382 | // ------------------------------------------------------------------- |
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| 383 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 384 | if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i] |
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| 385 | and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
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| 386 | { |
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| 387 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
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| 388 | |
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[117] | 389 | Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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[111] | 390 | |
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[117] | 391 | context_state_t state = reg_STATE [context_id]; |
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| 392 | |
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[111] | 393 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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[117] | 394 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context_id]; |
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| 395 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context_id]):0; |
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| 396 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context_id]; |
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[111] | 397 | |
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| 398 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 399 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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[119] | 400 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 401 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[111] | 402 | |
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| 403 | // priority : miss_load > miss_branch > excep > spr/sync |
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| 404 | uint8_t priority0 = get_priority(state); |
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[124] | 405 | uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss |
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[111] | 406 | |
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| 407 | // is_valid = can modify local information |
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| 408 | // if context_state_ok : yes |
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| 409 | // if context_state_ko : test the depth, and the priority of event |
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| 410 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 411 | (depth1< depth0) or |
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| 412 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
---|
| 413 | |
---|
[117] | 414 | log_printf(TRACE,Context_State,FUNCTION," * context_id: %d",context_id); |
---|
[111] | 415 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
| 416 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 417 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 418 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 419 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 420 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 421 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 422 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
| 423 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 424 | |
---|
| 425 | if (is_valid) |
---|
| 426 | { |
---|
[119] | 427 | // reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
---|
| 428 | reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE; |
---|
| 429 | reg_EVENT_DEPTH [context_id] = depth; |
---|
| 430 | reg_EVENT_FLUSH_ONLY [context_id] = false; |
---|
[88] | 431 | } |
---|
| 432 | } |
---|
| 433 | |
---|
| 434 | // ------------------------------------------------------------------- |
---|
| 435 | // -----[ DECOD_EVENT ]----------------------------------------------- |
---|
| 436 | // ------------------------------------------------------------------- |
---|
[83] | 437 | |
---|
[88] | 438 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
---|
| 439 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
---|
| 440 | { |
---|
[98] | 441 | log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); |
---|
| 442 | |
---|
[88] | 443 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
---|
| 444 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
---|
| 445 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
---|
| 446 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
---|
[106] | 447 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
---|
[88] | 448 | |
---|
[106] | 449 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 450 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
| 451 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
| 452 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
[83] | 453 | |
---|
[88] | 454 | context_state_t state = reg_STATE [context]; |
---|
| 455 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
---|
| 456 | |
---|
[111] | 457 | // miss_load > miss_branch > excep > spr/sync |
---|
| 458 | uint8_t priority0 = get_priority(state); |
---|
[124] | 459 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE; |
---|
[83] | 460 | |
---|
[88] | 461 | // is_valid = can modify local information |
---|
| 462 | // if context_state_ok : yes |
---|
| 463 | // if context_state_ko : test the depth, and the priority of envent |
---|
[83] | 464 | |
---|
[88] | 465 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
| 466 | (depth1< depth0) or |
---|
[105] | 467 | ((depth1==depth0) and (priority1>=priority0))); |
---|
[83] | 468 | |
---|
[106] | 469 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
| 470 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 471 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 472 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 473 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 474 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 475 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 476 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
| 477 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 478 | |
---|
[88] | 479 | if (is_valid) |
---|
| 480 | { |
---|
[101] | 481 | log_printf(TRACE,Context_State,FUNCTION," * is_valid"); |
---|
| 482 | |
---|
[88] | 483 | // decod : |
---|
| 484 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
---|
| 485 | context_state_t state_next = state; |
---|
| 486 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
---|
| 487 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
---|
[83] | 488 | |
---|
[88] | 489 | switch (type) |
---|
| 490 | { |
---|
| 491 | case EVENT_TYPE_EXCEPTION : |
---|
| 492 | { |
---|
[101] | 493 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); |
---|
| 494 | |
---|
[88] | 495 | state_next = CONTEXT_STATE_KO_EXCEP; |
---|
[83] | 496 | |
---|
[88] | 497 | break; |
---|
| 498 | } |
---|
| 499 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 500 | { |
---|
[101] | 501 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); |
---|
| 502 | |
---|
| 503 | // state_next = CONTEXT_STATE_KO_SPR ; |
---|
| 504 | state_next = CONTEXT_STATE_KO_SPR_EXEC; |
---|
[88] | 505 | address++; // take next address |
---|
[101] | 506 | // if (is_delay_slot) |
---|
| 507 | // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
---|
[88] | 508 | break; |
---|
| 509 | } |
---|
| 510 | case EVENT_TYPE_MSYNC : |
---|
| 511 | { |
---|
[101] | 512 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); |
---|
| 513 | |
---|
| 514 | // state_next = CONTEXT_STATE_KO_MSYNC; |
---|
| 515 | state_next = CONTEXT_STATE_KO_MSYNC_EXEC; |
---|
[88] | 516 | address++; // take next address |
---|
[101] | 517 | // if (is_delay_slot) |
---|
| 518 | // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); |
---|
[88] | 519 | break; |
---|
| 520 | } |
---|
| 521 | case EVENT_TYPE_PSYNC : |
---|
| 522 | { |
---|
[101] | 523 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); |
---|
| 524 | |
---|
| 525 | // state_next = CONTEXT_STATE_KO_PSYNC; |
---|
| 526 | state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; |
---|
[88] | 527 | address++; // take next address |
---|
| 528 | if (is_delay_slot) |
---|
[101] | 529 | throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); |
---|
[88] | 530 | break; |
---|
| 531 | } |
---|
| 532 | case EVENT_TYPE_CSYNC : |
---|
| 533 | { |
---|
[101] | 534 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); |
---|
| 535 | |
---|
| 536 | // state_next = CONTEXT_STATE_KO_CSYNC; |
---|
| 537 | state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; |
---|
[88] | 538 | address++; // take next address |
---|
| 539 | if (is_delay_slot) |
---|
[101] | 540 | throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); |
---|
[88] | 541 | break; |
---|
| 542 | } |
---|
| 543 | case EVENT_TYPE_NONE : |
---|
[105] | 544 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 545 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 546 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 547 | default : |
---|
| 548 | { |
---|
| 549 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
---|
| 550 | } |
---|
| 551 | } |
---|
[83] | 552 | |
---|
[88] | 553 | reg_STATE [context] = state_next; |
---|
| 554 | reg_EVENT_ADDRESS [context] = address; |
---|
| 555 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
---|
| 556 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
---|
| 557 | //reg_EVENT_ADDRESS_EEAR [context] |
---|
| 558 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
---|
| 559 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
---|
| 560 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
| 561 | reg_EVENT_DEPTH [context] = depth; |
---|
[119] | 562 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
[88] | 563 | } |
---|
| 564 | } |
---|
[83] | 565 | |
---|
[88] | 566 | // ------------------------------------------------------------------- |
---|
| 567 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
---|
| 568 | // ------------------------------------------------------------------- |
---|
[83] | 569 | |
---|
[88] | 570 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
---|
| 571 | { |
---|
[98] | 572 | log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); |
---|
| 573 | |
---|
[88] | 574 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
---|
| 575 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
---|
[111] | 576 | // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
---|
| 577 | // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
---|
| 578 | // Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
---|
[88] | 579 | |
---|
[111] | 580 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 581 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
| 582 | // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
| 583 | // // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
[83] | 584 | |
---|
[88] | 585 | context_state_t state = reg_STATE [context]; |
---|
| 586 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
---|
| 587 | |
---|
[111] | 588 | // // miss > excep > spr/sync |
---|
| 589 | // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or |
---|
| 590 | // (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or |
---|
| 591 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or |
---|
| 592 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or |
---|
| 593 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ) or |
---|
| 594 | // (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or |
---|
| 595 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
---|
| 596 | // uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) |
---|
[88] | 597 | |
---|
[111] | 598 | // // is_valid = can modify local information |
---|
| 599 | // // if context_state_ok : yes |
---|
| 600 | // // if context_state_ko : test the depth, and the priority of envent |
---|
[88] | 601 | |
---|
[111] | 602 | // bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
| 603 | // (depth1< depth0) or |
---|
| 604 | // ((depth1==depth0) and (priority1>=priority0))); |
---|
[88] | 605 | |
---|
[111] | 606 | // if commit send an event, also they have not yet event previous this instruction |
---|
| 607 | bool is_valid = true; |
---|
| 608 | |
---|
[106] | 609 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
[111] | 610 | // log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 611 | // log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 612 | // log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 613 | // log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 614 | // log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 615 | // log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 616 | // log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
[106] | 617 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 618 | |
---|
[88] | 619 | if (is_valid) |
---|
| 620 | { |
---|
| 621 | // commit |
---|
| 622 | // type : exception |
---|
| 623 | context_state_t state_next = state; |
---|
| 624 | switch (type) |
---|
| 625 | { |
---|
[105] | 626 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
---|
[108] | 627 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 628 | { |
---|
| 629 | // Test if previous branch occure |
---|
[111] | 630 | switch (state) |
---|
| 631 | { |
---|
| 632 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
| 633 | { |
---|
| 634 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE; |
---|
| 635 | break; |
---|
| 636 | } |
---|
| 637 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
| 638 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
---|
| 639 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
| 640 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
---|
| 641 | { |
---|
[124] | 642 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
| 643 | // state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
---|
| 644 | // #else |
---|
[111] | 645 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
---|
[124] | 646 | // #endif |
---|
[111] | 647 | break; |
---|
| 648 | } |
---|
| 649 | default : |
---|
| 650 | { |
---|
[124] | 651 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
| 652 | // state_next = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
---|
| 653 | // #else |
---|
[111] | 654 | state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; |
---|
[124] | 655 | // #endif |
---|
[111] | 656 | break; |
---|
| 657 | } |
---|
| 658 | } |
---|
[123] | 659 | |
---|
| 660 | depth = (depth+1)%_param->_nb_inst_branch_speculated[context]; |
---|
| 661 | |
---|
[108] | 662 | break; |
---|
| 663 | } |
---|
[105] | 664 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 665 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 666 | case EVENT_TYPE_MSYNC : |
---|
| 667 | case EVENT_TYPE_PSYNC : |
---|
| 668 | case EVENT_TYPE_CSYNC : |
---|
| 669 | case EVENT_TYPE_NONE : |
---|
| 670 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 671 | default : |
---|
| 672 | { |
---|
| 673 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
---|
| 674 | } |
---|
| 675 | } |
---|
| 676 | reg_STATE [context] = state_next; |
---|
| 677 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
---|
| 678 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
---|
[105] | 679 | reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); |
---|
[88] | 680 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
---|
| 681 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
---|
| 682 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
---|
[105] | 683 | reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
[88] | 684 | reg_EVENT_DEPTH [context] = depth; |
---|
[119] | 685 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
[88] | 686 | } |
---|
| 687 | } |
---|
| 688 | |
---|
| 689 | // ------------------------------------------------------------------- |
---|
| 690 | // -----[ SPR_EVENT ]------------------------------------------------- |
---|
| 691 | // ------------------------------------------------------------------- |
---|
| 692 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 693 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
---|
| 694 | { |
---|
[98] | 695 | log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); |
---|
| 696 | |
---|
[88] | 697 | // Write spr |
---|
[83] | 698 | #ifdef DEBUG_TEST |
---|
[88] | 699 | context_state_t state = reg_STATE [i]; |
---|
| 700 | |
---|
| 701 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
---|
| 702 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
---|
[83] | 703 | #endif |
---|
[88] | 704 | |
---|
| 705 | reg_STATE [i] = CONTEXT_STATE_OK; |
---|
| 706 | } |
---|
[83] | 707 | |
---|
[88] | 708 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 709 | { |
---|
| 710 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
| 711 | |
---|
| 712 | if (reg_INTERRUPT_ENABLE [i]) |
---|
| 713 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
| 714 | } |
---|
[124] | 715 | |
---|
| 716 | |
---|
| 717 | #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
| 718 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 719 | switch (reg_STATE [i]) |
---|
| 720 | { |
---|
| 721 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR ; break; |
---|
| 722 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR ; break; |
---|
| 723 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; break; |
---|
| 724 | default : break; |
---|
| 725 | } |
---|
| 726 | #endif |
---|
[83] | 727 | } |
---|
| 728 | |
---|
[120] | 729 | |
---|
| 730 | #ifdef STATISTICS |
---|
| 731 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 732 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 733 | switch(reg_STATE[i]) |
---|
| 734 | { |
---|
| 735 | case CONTEXT_STATE_OK : (*_stat_nb_cycle_state_ok [i])++; break; |
---|
| 736 | |
---|
| 737 | case CONTEXT_STATE_KO_EXCEP : |
---|
| 738 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
---|
| 739 | case CONTEXT_STATE_KO_EXCEP_SPR : (*_stat_nb_cycle_state_ko_excep [i])++; break; |
---|
| 740 | |
---|
| 741 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
| 742 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
| 743 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_branch [i])++; break; |
---|
| 744 | |
---|
| 745 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
---|
| 746 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : (*_stat_nb_cycle_state_ko_miss_load [i])++; break; |
---|
| 747 | |
---|
| 748 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE: |
---|
| 749 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
| 750 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_load_and_branch [i])++; break; |
---|
| 751 | |
---|
| 752 | // case CONTEXT_STATE_KO_MSYNC : |
---|
| 753 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
---|
| 754 | case CONTEXT_STATE_KO_MSYNC_EXEC : (*_stat_nb_cycle_state_ko_msync [i])++; break; |
---|
| 755 | |
---|
| 756 | // case CONTEXT_STATE_KO_PSYNC : |
---|
| 757 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
---|
| 758 | case CONTEXT_STATE_KO_PSYNC_ADDR : (*_stat_nb_cycle_state_ko_psync [i])++; break; |
---|
| 759 | |
---|
| 760 | // case CONTEXT_STATE_KO_CSYNC : |
---|
| 761 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
---|
| 762 | case CONTEXT_STATE_KO_CSYNC_ADDR : (*_stat_nb_cycle_state_ko_csync [i])++; break; |
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| 763 | |
---|
| 764 | // case CONTEXT_STATE_KO_SPR : |
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| 765 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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| 766 | case CONTEXT_STATE_KO_SPR_EXEC : (*_stat_nb_cycle_state_ko_spr [i])++; break; |
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| 767 | } |
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| 768 | #endif |
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| 769 | |
---|
| 770 | |
---|
| 771 | |
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[83] | 772 | #if DEBUG >= DEBUG_TRACE |
---|
| 773 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 774 | { |
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[88] | 775 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
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| 776 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
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| 777 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
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| 778 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
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| 779 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
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| 780 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
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| 781 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
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| 782 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
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| 783 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
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| 784 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
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[119] | 785 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_FLUSH_ONLY : %d" ,reg_EVENT_FLUSH_ONLY [i]); |
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[83] | 786 | } |
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| 787 | #endif |
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| 788 | |
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| 789 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 790 | end_cycle (); |
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| 791 | #endif |
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| 792 | |
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| 793 | log_end(Context_State,FUNCTION); |
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| 794 | }; |
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| 795 | |
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| 796 | }; // end namespace context_state |
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| 797 | }; // end namespace front_end |
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| 798 | }; // end namespace multi_front_end |
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| 799 | }; // end namespace core |
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| 800 | |
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| 801 | }; // end namespace behavioural |
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| 802 | }; // end namespace morpheo |
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| 803 | #endif |
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