[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Address_management_transition.cpp 107 2009-02-10 23:03:25Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace ifetch_unit { |
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| 17 | namespace address_management { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Address_management::transition" |
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| 22 | void Address_management::transition (void) |
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| 23 | { |
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[88] | 24 | log_begin(Address_management,FUNCTION); |
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| 25 | log_function(Address_management,FUNCTION,_name.c_str()); |
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[78] | 26 | |
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| 27 | if (PORT_READ(in_NRESET) == 0) |
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| 28 | { |
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[84] | 29 | // nothing is valid |
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[101] | 30 | reg_PC_ACCESS_VAL = 0; |
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| 31 | |
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[84] | 32 | reg_PC_CURRENT_VAL = 0; |
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[88] | 33 | |
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| 34 | reg_PC_NEXT_VAL = 1; |
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| 35 | reg_PC_NEXT = 0x100>>2; |
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[101] | 36 | reg_PC_NEXT_IS_DS_TAKE = 0; |
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[107] | 37 | uint32_t index = reg_PC_NEXT % _param->_nb_instruction; |
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| 38 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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[101] | 39 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; |
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[107] | 40 | reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; |
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[101] | 41 | reg_PC_NEXT_INST_IFETCH_PTR = 0; |
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| 42 | reg_PC_NEXT_BRANCH_STATE = 0; |
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| 43 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; |
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[88] | 44 | |
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[101] | 45 | |
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[84] | 46 | reg_PC_NEXT_NEXT_VAL = 0; |
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[78] | 47 | } |
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| 48 | else |
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| 49 | { |
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| 50 | // ========================================= |
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[84] | 51 | // ===== PREDICT =========================== |
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| 52 | // ========================================= |
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| 53 | if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL) |
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| 54 | { |
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[101] | 55 | bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE; |
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| 56 | if (branch_is_current) |
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| 57 | { |
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| 58 | if (_param->_have_port_inst_ifetch_ptr) |
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| 59 | reg_PC_CURRENT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); |
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| 60 | reg_PC_CURRENT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); |
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| 61 | if (_param->_have_port_depth) |
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| 62 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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| 63 | } |
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| 64 | else |
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| 65 | { |
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| 66 | if (_param->_have_port_inst_ifetch_ptr) |
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| 67 | reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); |
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| 68 | reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); |
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| 69 | if (_param->_have_port_depth) |
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| 70 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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| 71 | } |
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| 72 | |
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[84] | 73 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 74 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); |
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| 75 | |
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| 76 | reg_PC_NEXT_NEXT_VAL = 1; // address is valid |
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| 77 | reg_PC_NEXT_NEXT = PORT_READ(in_PREDICT_PC_NEXT ); |
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| 78 | reg_PC_NEXT_NEXT_IS_DS_TAKE = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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| 79 | |
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| 80 | #ifdef STATISTICS |
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[88] | 81 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 82 | (*_stat_nb_transaction_predict) ++; |
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[84] | 83 | #endif |
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| 84 | } |
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| 85 | |
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| 86 | // ========================================= |
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[78] | 87 | // ===== ADDRESS =========================== |
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| 88 | // ========================================= |
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| 89 | // transaction with icache |
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[101] | 90 | if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) |
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| 91 | { |
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| 92 | reg_PC_ACCESS_VAL = 0; |
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[84] | 93 | #ifdef STATISTICS |
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[88] | 94 | if (usage_is_set(_usage,USE_STATISTICS)) |
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[101] | 95 | { |
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[88] | 96 | (*_stat_nb_transaction_address) ++; |
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| 97 | |
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| 98 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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[101] | 99 | if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true) |
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[88] | 100 | (*_stat_sum_packet_size) ++; |
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| 101 | } |
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[84] | 102 | #endif |
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[101] | 103 | } |
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| 104 | |
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| 105 | // Shift register |
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[78] | 106 | |
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[101] | 107 | if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL) |
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| 108 | { |
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| 109 | reg_PC_ACCESS_VAL = 1; // new request |
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| 110 | reg_PC_CURRENT_VAL = 0; // invalid current |
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| 111 | |
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| 112 | reg_PC_ACCESS = reg_PC_CURRENT ; |
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| 113 | reg_PC_ACCESS_IS_DS_TAKE = reg_PC_CURRENT_IS_DS_TAKE ; |
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| 114 | reg_PC_ACCESS_INST_IFETCH_PTR = reg_PC_CURRENT_INST_IFETCH_PTR ; |
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| 115 | reg_PC_ACCESS_BRANCH_STATE = reg_PC_CURRENT_BRANCH_STATE ; |
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| 116 | reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID; |
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| 117 | |
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| 118 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 119 | reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i]; |
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| 120 | } |
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| 121 | |
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| 122 | if (not reg_PC_CURRENT_VAL) |
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| 123 | { |
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| 124 | bool val = reg_PC_NEXT_VAL; |
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| 125 | reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid |
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| 126 | reg_PC_NEXT_VAL = 0; // invalid next |
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[78] | 127 | |
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[101] | 128 | if (val) |
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| 129 | { |
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| 130 | reg_PC_CURRENT = reg_PC_NEXT ; |
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| 131 | reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; |
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| 132 | reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; |
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| 133 | reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; |
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| 134 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; |
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| 135 | |
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| 136 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 137 | reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; |
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| 138 | } |
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| 139 | } |
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[78] | 140 | |
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[101] | 141 | if (not reg_PC_NEXT_VAL) |
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| 142 | { |
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| 143 | bool val = reg_PC_NEXT_NEXT_VAL; |
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| 144 | reg_PC_NEXT_VAL = val; // new PC_NEXT if PC_NEXT_NEXT is valid |
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| 145 | reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next |
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| 146 | |
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| 147 | if (val) |
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| 148 | { |
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| 149 | reg_PC_NEXT = reg_PC_NEXT_NEXT ; |
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| 150 | reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE ; |
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| 151 | // reg_PC_NEXT_INST_IFETCH_PTR = reg_PC_NEXT_NEXT_INST_IFETCH_PTR ; |
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| 152 | // reg_PC_NEXT_BRANCH_STATE = reg_PC_NEXT_NEXT_BRANCH_STATE ; |
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| 153 | // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID; |
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| 154 | |
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| 155 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 156 | // reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i]; |
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| 157 | } |
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| 158 | } |
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[78] | 159 | |
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| 160 | // ========================================= |
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| 161 | // ===== EVENT ============================= |
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| 162 | // ========================================= |
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| 163 | if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK) |
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| 164 | { |
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[88] | 165 | log_printf(TRACE,Address_management,FUNCTION," * EVENT : Transaction"); |
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| 166 | log_printf(TRACE,Address_management,FUNCTION," * IS_DS_TAKE : %d" ,PORT_READ(in_EVENT_IS_DS_TAKE )); |
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| 167 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS ),PORT_READ(in_EVENT_ADDRESS )<<2); |
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| 168 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT ),PORT_READ(in_EVENT_ADDRESS_NEXT )<<2); |
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| 169 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT_VAL : %d" ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL)); |
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[101] | 170 | |
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| 171 | reg_PC_ACCESS_VAL = 0; |
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[84] | 172 | reg_PC_CURRENT_VAL = 0; |
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| 173 | reg_PC_NEXT_VAL = 1; |
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| 174 | reg_PC_NEXT = PORT_READ(in_EVENT_ADDRESS); |
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[78] | 175 | // Event is never is ds_take : |
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| 176 | // * branch miss speculation : can't be place a branch in delay slot |
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| 177 | // * load miss speculation : the load is execute, the event_address is the next address (also the destination of branch) |
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| 178 | // * exception : goto the first instruction of exception handler (also is not in delay slot). |
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[88] | 179 | |
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| 180 | reg_PC_NEXT_IS_DS_TAKE = PORT_READ(in_EVENT_IS_DS_TAKE); |
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[84] | 181 | // reg_PC_NEXT_INST_IFETCH_PTR = 0; |
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| 182 | // reg_PC_NEXT_BRANCH_STATE = BRANCH_STATE_NONE; |
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| 183 | // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; |
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[78] | 184 | |
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[107] | 185 | // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. |
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| 186 | uint32_t index = reg_PC_NEXT % _param->_nb_instruction; |
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| 187 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 188 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; |
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| 189 | reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; |
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[78] | 190 | |
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[88] | 191 | reg_PC_NEXT_NEXT_VAL = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL); |
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| 192 | reg_PC_NEXT_NEXT = PORT_READ(in_EVENT_ADDRESS_NEXT); |
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| 193 | reg_PC_NEXT_NEXT_IS_DS_TAKE = 0;//?? |
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[84] | 194 | |
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[88] | 195 | // Note : is_ds_take = address_next_val |
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| 196 | // Because, is not ds take, can continue in sequence |
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| 197 | |
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[98] | 198 | // #ifdef DEBUG_TEST |
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| 199 | // if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE)) |
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| 200 | // throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take")); |
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| 201 | // #endif |
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[88] | 202 | |
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[84] | 203 | #ifdef STATISTICS |
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[88] | 204 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 205 | (*_stat_nb_transaction_event) ++; |
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[84] | 206 | #endif |
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[78] | 207 | } |
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| 208 | } |
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| 209 | |
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[101] | 210 | #if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE) |
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[88] | 211 | log_printf(TRACE,Address_management,FUNCTION," * Dump PC"); |
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[101] | 212 | { |
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| 213 | std::string instruction_enable; |
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| 214 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 215 | instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " "; |
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| 216 | |
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| 217 | log_printf(TRACE,Address_management,FUNCTION," * Access : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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| 218 | reg_PC_ACCESS_VAL, |
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| 219 | reg_PC_ACCESS_IS_DS_TAKE, |
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| 220 | reg_PC_ACCESS, |
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| 221 | reg_PC_ACCESS<<2, |
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| 222 | reg_PC_ACCESS_BRANCH_STATE, |
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| 223 | reg_PC_ACCESS_INST_IFETCH_PTR, |
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| 224 | reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID, |
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| 225 | instruction_enable.c_str() |
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| 226 | ); |
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| 227 | } |
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| 228 | { |
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| 229 | std::string instruction_enable; |
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| 230 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 231 | instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " "; |
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| 232 | |
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| 233 | log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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| 234 | reg_PC_CURRENT_VAL, |
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| 235 | reg_PC_CURRENT_IS_DS_TAKE, |
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| 236 | reg_PC_CURRENT, |
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| 237 | reg_PC_CURRENT<<2, |
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| 238 | reg_PC_CURRENT_BRANCH_STATE, |
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| 239 | reg_PC_CURRENT_INST_IFETCH_PTR, |
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| 240 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID, |
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| 241 | instruction_enable.c_str() |
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| 242 | ); |
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| 243 | } |
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| 244 | { |
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| 245 | std::string instruction_enable; |
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| 246 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 247 | instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " "; |
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| 248 | |
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| 249 | log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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| 250 | reg_PC_NEXT_VAL, |
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| 251 | reg_PC_NEXT_IS_DS_TAKE, |
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| 252 | reg_PC_NEXT, |
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| 253 | reg_PC_NEXT<<2, |
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| 254 | reg_PC_NEXT_BRANCH_STATE, |
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| 255 | reg_PC_NEXT_INST_IFETCH_PTR, |
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| 256 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID, |
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| 257 | instruction_enable.c_str()); |
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| 258 | } |
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| 259 | log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)", |
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| 260 | reg_PC_NEXT_NEXT_VAL, |
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| 261 | reg_PC_NEXT_NEXT_IS_DS_TAKE, |
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| 262 | reg_PC_NEXT_NEXT, |
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| 263 | reg_PC_NEXT_NEXT<<2); |
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[84] | 264 | #endif |
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| 265 | |
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[78] | 266 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 267 | end_cycle (); |
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| 268 | #endif |
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[88] | 269 | |
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| 270 | log_end(Address_management,FUNCTION); |
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[78] | 271 | }; |
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| 272 | |
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| 273 | }; // end namespace address_management |
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| 274 | }; // end namespace ifetch_unit |
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| 275 | }; // end namespace front_end |
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| 276 | }; // end namespace multi_front_end |
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| 277 | }; // end namespace core |
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| 278 | |
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| 279 | }; // end namespace behavioural |
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| 280 | }; // end namespace morpheo |
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| 281 | #endif |
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