[78] | 1 | /* |
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| 2 | * $Id: test.cpp 85 2008-05-14 13:09:48Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[85] | 9 | #define NB_ITERATION 128 |
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[82] | 10 | #define CYCLE_MAX (128*NB_ITERATION) |
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| 11 | |
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[78] | 12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/include/test.h" |
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[85] | 13 | #include "../../../../../../../../Environment/Queue/include/Sort_Queue.h" |
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[78] | 14 | #include "Common/include/Test.h" |
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| 15 | #include "Behavioural/include/Allocation.h" |
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| 16 | |
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[85] | 17 | //using namespace environment; |
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| 18 | using namespace environment::queue; |
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| 19 | |
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| 20 | class cache_req_t |
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| 21 | { |
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| 22 | public : Tpacket_t packet; |
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| 23 | public : Taddress_t address; |
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| 24 | |
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| 25 | public : cache_req_t (Tpacket_t packet, |
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| 26 | Taddress_t address) |
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| 27 | { |
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| 28 | this->packet = packet ; |
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| 29 | this->address = address; |
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| 30 | } |
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| 31 | }; |
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| 32 | |
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[78] | 33 | void test (string name, |
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| 34 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters * _param) |
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| 35 | { |
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| 36 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 37 | |
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| 38 | #ifdef STATISTICS |
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[85] | 39 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1024); |
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[78] | 40 | #endif |
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| 41 | |
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[82] | 42 | Ifetch_unit * _Ifetch_unit = new Ifetch_unit |
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| 43 | (name.c_str(), |
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[78] | 44 | #ifdef STATISTICS |
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[82] | 45 | _parameters_statistics, |
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[78] | 46 | #endif |
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[82] | 47 | _param, |
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| 48 | USE_ALL); |
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[78] | 49 | |
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| 50 | #ifdef SYSTEMC |
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| 51 | /********************************************************************* |
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| 52 | * Déclarations des signaux |
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| 53 | *********************************************************************/ |
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| 54 | string rename; |
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| 55 | |
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| 56 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 57 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 58 | |
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| 59 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ); |
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| 60 | ALLOC_SC_SIGNAL ( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ); |
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| 61 | //ALLOC_SC_SIGNAL (out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ); |
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| 62 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ); |
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| 63 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t); |
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| 64 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ); |
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| 65 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); |
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| 66 | ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); |
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| 67 | //ALLOC_SC_SIGNAL ( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ); |
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| 68 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); |
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| 69 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction); |
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| 70 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); |
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| 71 | ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); |
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| 72 | ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); |
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| 73 | ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t ); |
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| 74 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t ); |
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| 75 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); |
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| 76 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t ); |
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| 77 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); |
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| 78 | ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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| 79 | ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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| 80 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); |
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| 81 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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| 82 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction); |
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| 83 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction); |
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| 84 | ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction); |
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| 85 | //ALLOC_SC_SIGNAL (out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ); |
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| 86 | ALLOC_SC_SIGNAL (out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); |
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| 87 | ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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| 88 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); |
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| 89 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); |
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| 90 | ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ); |
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| 91 | ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); |
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| 92 | ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); |
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| 93 | ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t ); |
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| 94 | |
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| 95 | /******************************************************** |
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| 96 | * Instanciation |
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| 97 | ********************************************************/ |
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| 98 | |
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| 99 | msg(_("<%s> : Instanciation of _Ifetch_unit.\n"),name.c_str()); |
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| 100 | |
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| 101 | (*(_Ifetch_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 102 | (*(_Ifetch_unit->in_NRESET)) (*(in_NRESET)); |
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| 103 | |
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| 104 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_VAL ); |
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| 105 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_REQ_ACK ); |
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| 106 | //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_THREAD_ID ); |
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| 107 | if (_param->_have_port_queue_ptr) |
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| 108 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_PACKET_ID ); |
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| 109 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_ADDRESS ); |
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| 110 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_TYPE ); |
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| 111 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_VAL ); |
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| 112 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_RSP_ACK ); |
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| 113 | //INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_THREAD_ID ); |
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| 114 | if (_param->_have_port_queue_ptr) |
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| 115 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_PACKET_ID ); |
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| 116 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); |
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| 117 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_ERROR ); |
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| 118 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_VAL ); |
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| 119 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_ACK ); |
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| 120 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_PREVIOUS ); |
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| 121 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT ); |
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| 122 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); |
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| 123 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT ); |
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| 124 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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| 125 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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| 126 | if (_param->_have_port_instruction_ptr) |
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| 127 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR ); |
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| 128 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_STATE ); |
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| 129 | if (_param->_have_port_branch_update_prediction_id) |
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| 130 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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| 131 | INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_VAL ,_param->_nb_instruction); |
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| 132 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_DECOD_ACK ,_param->_nb_instruction); |
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| 133 | INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_INSTRUCTION ,_param->_nb_instruction); |
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| 134 | //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_CONTEXT_ID ); |
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| 135 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_ADDRESS ); |
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| 136 | if (_param->_have_port_instruction_ptr) |
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| 137 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_INST_IFETCH_PTR ); |
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| 138 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_STATE ); |
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| 139 | if (_param->_have_port_branch_update_prediction_id) |
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| 140 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); |
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| 141 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_EXCEPTION ); |
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| 142 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_VAL ); |
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| 143 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_EVENT_ACK ); |
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| 144 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS ); |
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| 145 | |
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| 146 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 147 | |
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| 148 | Time * _time = new Time(); |
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| 149 | |
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| 150 | /******************************************************** |
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| 151 | * Simulation - Begin |
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| 152 | ********************************************************/ |
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| 153 | |
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| 154 | // Initialisation |
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| 155 | |
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| 156 | const uint32_t seed = 0; |
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| 157 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 158 | |
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| 159 | srand(seed); |
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| 160 | |
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[85] | 161 | const int32_t percent_transaction_icache_req = 75; |
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| 162 | const int32_t percent_transaction_icache_rsp = 75; |
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| 163 | const int32_t percent_transaction_predict = 75; |
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| 164 | const int32_t percent_transaction_event = 5; |
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| 165 | const int32_t percent_hit = 90; |
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| 166 | const uint32_t delay_miss_min = 5; |
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| 167 | const uint32_t delay_miss_max = 10; |
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| 168 | |
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[78] | 169 | SC_START(0); |
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| 170 | LABEL("Initialisation"); |
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| 171 | |
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[85] | 172 | uint32_t jump = 7 ;// packet |
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| 173 | uint32_t nb_packet_in = 1; |
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| 174 | uint32_t nb_packet_out = 1; |
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| 175 | |
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| 176 | Tcontrol_t c_val = false; |
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| 177 | Tcontrol_t n_val = false; |
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| 178 | Tcontrol_t nn_val = false; |
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| 179 | |
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| 180 | Tgeneral_data_t c_addr = 0x100; |
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| 181 | Tgeneral_data_t n_addr = 0x100; |
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| 182 | Tgeneral_data_t nn_addr = 0x100; |
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| 183 | |
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| 184 | Tcontrol_t c_enable [_param->_nb_instruction]; |
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| 185 | Tcontrol_t n_enable [_param->_nb_instruction]; |
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| 186 | |
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| 187 | Tcontrol_t c_is_ds_take = 0; |
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| 188 | Tcontrol_t n_is_ds_take = 0; |
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| 189 | Tcontrol_t nn_is_ds_take = 0; |
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| 190 | |
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| 191 | bool slot_use [_param->_size_queue]; |
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| 192 | |
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| 193 | environment::queue::Parameters * param_cache = new environment::queue::Parameters(_param->_size_queue); |
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| 194 | Sort_Queue<cache_req_t*> * cache = new Sort_Queue<cache_req_t*> ("cache",param_cache); |
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| 195 | |
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| 196 | cache->reset(); |
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| 197 | |
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| 198 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 199 | slot_use [i] = false; |
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| 200 | |
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| 201 | c_enable [0] = 1; |
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| 202 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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| 203 | c_enable [i] = 0; |
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| 204 | |
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[78] | 205 | LABEL("Reset"); |
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| 206 | in_NRESET->write(0); |
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| 207 | SC_START(5); |
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| 208 | in_NRESET->write(1); |
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| 209 | |
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[85] | 210 | LABEL("Test no out val/ack"); |
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| 211 | |
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| 212 | TEST(Tcontrol_t,out_ICACHE_REQ_VAL->read(), 0); |
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| 213 | TEST(Tcontrol_t,out_ICACHE_RSP_ACK->read(), 1); |
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| 214 | TEST(Tcontrol_t,out_PREDICT_VAL ->read(), 1); |
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| 215 | TEST(Tcontrol_t,out_EVENT_ACK ->read(), 1); |
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| 216 | |
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| 217 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 218 | TEST(Tcontrol_t,out_DECOD_VAL [i]->read(), 0); |
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| 219 | |
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| 220 | LABEL("Send Reset"); |
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| 221 | do |
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| 222 | { |
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| 223 | in_EVENT_VAL ->write(1); |
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| 224 | in_EVENT_ADDRESS->write(n_addr); |
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| 225 | SC_START(1); |
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| 226 | } while (out_EVENT_ACK->read() == false); |
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| 227 | in_EVENT_VAL ->write(0); |
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| 228 | |
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| 229 | n_val = 1; |
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| 230 | |
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[78] | 231 | LABEL("Loop of Test"); |
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| 232 | |
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| 233 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 234 | { |
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| 235 | LABEL("Iteration %d",iteration); |
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| 236 | |
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[85] | 237 | // PREDICT |
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| 238 | { |
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| 239 | in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); |
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| 240 | |
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| 241 | SC_START(0); |
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| 242 | |
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| 243 | Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); |
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| 244 | |
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| 245 | uint32_t begin = addr%_param->_nb_instruction; |
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| 246 | uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); |
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| 247 | Tcontrol_t take = (nb_packet_in%jump)==0; |
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| 248 | |
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| 249 | if (take) |
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| 250 | addr += 0x100; |
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| 251 | else |
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| 252 | addr += end-begin+1; |
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| 253 | |
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| 254 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 255 | in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); |
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| 256 | in_PREDICT_PC_NEXT ->write(addr); |
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| 257 | in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); |
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| 258 | in_PREDICT_INST_IFETCH_PTR ->write(0); |
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| 259 | in_PREDICT_BRANCH_STATE ->write(0); |
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| 260 | in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); |
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| 261 | } |
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| 262 | |
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| 263 | // DECOD |
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| 264 | { |
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| 265 | uint32_t nb_decod = (rand()%_param->_nb_instruction); |
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| 266 | |
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| 267 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 268 | in_DECOD_ACK [i]->write(i<=nb_decod); |
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| 269 | } |
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| 270 | |
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| 271 | // EVENT |
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| 272 | in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); |
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| 273 | in_EVENT_ADDRESS->write(0x100); |
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| 274 | |
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| 275 | // ICACHE_REQ |
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| 276 | in_ICACHE_REQ_ACK->write((rand()%100)<percent_transaction_icache_req); |
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| 277 | |
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| 278 | // ICACHE_RSP |
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| 279 | { |
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| 280 | Tcontrol_t val = false; |
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| 281 | if (not cache->empty()) |
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| 282 | { |
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| 283 | slot_t<cache_req_t *> cache_rsp = cache->read(); |
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| 284 | |
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| 285 | val = (cache_rsp._delay == 0); |
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| 286 | |
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| 287 | Tpacket_t packet = cache_rsp._data->packet ; |
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| 288 | Taddress_t address = cache_rsp._data->address; |
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| 289 | |
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| 290 | in_ICACHE_RSP_PACKET_ID ->write(packet); |
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| 291 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 292 | in_ICACHE_RSP_INSTRUCTION [i]->write(address+i); |
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| 293 | in_ICACHE_RSP_ERROR ->write(0); |
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| 294 | } |
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| 295 | |
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| 296 | in_ICACHE_RSP_VAL->write(val); |
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| 297 | } |
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| 298 | |
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| 299 | //------------------------------------------------- |
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| 300 | SC_START(0); |
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| 301 | //------------------------------------------------- |
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| 302 | |
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| 303 | if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read()) |
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| 304 | { |
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| 305 | LABEL("ICACHE_REQ : Transaction accepted"); |
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| 306 | |
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| 307 | Tpacket_t packet = (_param->_have_port_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0; |
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| 308 | Taddress_t address = out_ICACHE_REQ_ADDRESS->read(); |
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| 309 | |
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| 310 | TEST(bool ,slot_use[packet], false); |
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| 311 | TEST(Taddress_t,address ,c_addr); |
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| 312 | |
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| 313 | slot_use[packet] = true; |
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| 314 | |
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| 315 | uint32_t delay; |
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| 316 | if ((rand()%100)<percent_hit) |
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| 317 | delay = 1; |
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| 318 | else |
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| 319 | delay = delay_miss_min + (rand()%(delay_miss_max-delay_miss_min+1)); |
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| 320 | |
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| 321 | cache_req_t * cache_req = new cache_req_t(packet,address); |
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| 322 | cache->push(delay,cache_req); |
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| 323 | |
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| 324 | c_val = 0; |
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| 325 | nb_packet_in ++; |
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| 326 | } |
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| 327 | |
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| 328 | { |
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| 329 | bool find=false; |
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| 330 | |
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| 331 | Taddress_t addr=out_DECOD_ADDRESS->read(); |
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| 332 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 333 | if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read()) |
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| 334 | { |
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| 335 | Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read(); |
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| 336 | LABEL("DECOD [%d] : Transaction accepted",i); |
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| 337 | LABEL(" address : 0x%x",addr); |
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| 338 | LABEL(" instruction : 0x%x",inst); |
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| 339 | |
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| 340 | find = true; |
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| 341 | TEST(Tinstruction_t,inst,addr+i); |
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| 342 | } |
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| 343 | |
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| 344 | if (find) |
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| 345 | { |
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| 346 | if (_param->_have_port_instruction_ptr) |
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| 347 | TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR ->read(), 0); |
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| 348 | TEST(Tbranch_state_t , out_DECOD_BRANCH_STATE ->read(), 0); |
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| 349 | if (_param->_have_port_branch_update_prediction_id) |
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| 350 | TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0); |
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| 351 | TEST(Texception_t , out_DECOD_EXCEPTION ->read(), 0); |
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| 352 | } |
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| 353 | } |
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| 354 | |
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| 355 | if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read()) |
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| 356 | { |
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| 357 | LABEL("ICACHE_RSP : Transaction accepted"); |
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| 358 | |
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| 359 | slot_use[cache->read()._data->packet] = false; |
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| 360 | |
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| 361 | cache->pop(); |
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| 362 | } |
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| 363 | |
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| 364 | if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) |
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| 365 | { |
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| 366 | LABEL("PREDICT : Transaction accepted"); |
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| 367 | |
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| 368 | if (c_val) |
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| 369 | TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); |
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| 370 | TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); |
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| 371 | TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); |
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| 372 | |
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| 373 | nn_val = true; |
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| 374 | nn_addr = in_PREDICT_PC_NEXT ->read(); |
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| 375 | nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); |
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| 376 | |
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| 377 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 378 | n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); |
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| 379 | } |
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| 380 | |
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| 381 | if (not c_val) |
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| 382 | { |
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| 383 | if (n_val and nn_val) |
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| 384 | { |
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| 385 | c_val = 1; |
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| 386 | c_addr = n_addr; |
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| 387 | c_is_ds_take = n_is_ds_take; |
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| 388 | |
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| 389 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 390 | c_enable [i] = n_enable [i]; |
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| 391 | |
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| 392 | n_val = 1; |
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| 393 | n_addr = nn_addr; |
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| 394 | n_is_ds_take = nn_is_ds_take; |
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| 395 | |
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| 396 | nn_val = 0; |
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| 397 | } |
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| 398 | } |
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| 399 | |
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| 400 | if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) |
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| 401 | { |
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| 402 | LABEL("EVENT : Transaction accepted"); |
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| 403 | |
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| 404 | c_val = false; |
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| 405 | n_val = true; |
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| 406 | nn_val = false; |
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| 407 | |
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| 408 | n_addr = in_EVENT_ADDRESS->read(); |
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| 409 | n_is_ds_take = 0; |
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| 410 | |
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| 411 | n_enable [0] = 1; |
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| 412 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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| 413 | n_enable [i] = 0; |
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| 414 | } |
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| 415 | |
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| 416 | |
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| 417 | { |
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| 418 | string str_c_enable = ""; |
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| 419 | string str_n_enable = ""; |
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| 420 | |
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| 421 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 422 | { |
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| 423 | str_c_enable += " " + toString(c_enable [i]); |
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| 424 | str_n_enable += " " + toString(n_enable [i]); |
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| 425 | } |
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| 426 | |
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| 427 | LABEL("-----------------------------------"); |
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| 428 | LABEL(" * nb_packet_in : %d",nb_packet_in); |
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| 429 | LABEL(" * nb_packet_out : %d",nb_packet_out); |
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| 430 | LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); |
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| 431 | if (nn_val) |
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| 432 | { |
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| 433 | LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); |
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| 434 | } |
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| 435 | else |
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| 436 | { |
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| 437 | LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); |
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| 438 | } |
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| 439 | LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); |
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| 440 | LABEL("-----------------------------------"); |
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| 441 | } |
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| 442 | |
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| 443 | SC_START(1); |
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| 444 | cache->transition(); |
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[78] | 445 | } |
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| 446 | |
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| 447 | /******************************************************** |
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| 448 | * Simulation - End |
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| 449 | ********************************************************/ |
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| 450 | |
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| 451 | TEST_OK ("End of Simulation"); |
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| 452 | delete _time; |
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| 453 | |
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| 454 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 455 | |
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| 456 | delete in_CLOCK; |
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| 457 | delete in_NRESET; |
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| 458 | |
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| 459 | delete out_ICACHE_REQ_VAL ; |
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| 460 | delete in_ICACHE_REQ_ACK ; |
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| 461 | //delete out_ICACHE_REQ_THREAD_ID ; |
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| 462 | delete out_ICACHE_REQ_PACKET_ID ; |
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| 463 | delete out_ICACHE_REQ_ADDRESS ; |
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| 464 | delete out_ICACHE_REQ_TYPE ; |
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| 465 | |
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| 466 | delete in_ICACHE_RSP_VAL ; |
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| 467 | delete out_ICACHE_RSP_ACK ; |
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| 468 | //delete in_ICACHE_RSP_THREAD_ID ; |
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| 469 | delete in_ICACHE_RSP_PACKET_ID ; |
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| 470 | delete [] in_ICACHE_RSP_INSTRUCTION ; |
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| 471 | delete in_ICACHE_RSP_ERROR ; |
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| 472 | |
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| 473 | delete out_PREDICT_VAL ; |
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| 474 | delete in_PREDICT_ACK ; |
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| 475 | delete out_PREDICT_PC_PREVIOUS ; |
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| 476 | delete out_PREDICT_PC_CURRENT ; |
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| 477 | delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
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| 478 | delete in_PREDICT_PC_NEXT ; |
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| 479 | delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
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| 480 | delete [] in_PREDICT_INSTRUCTION_ENABLE ; |
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| 481 | delete in_PREDICT_INST_IFETCH_PTR ; |
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| 482 | delete in_PREDICT_BRANCH_STATE ; |
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| 483 | delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; |
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| 484 | |
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| 485 | delete [] out_DECOD_VAL ; |
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| 486 | delete [] in_DECOD_ACK ; |
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| 487 | delete [] out_DECOD_INSTRUCTION ; |
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| 488 | //delete out_DECOD_CONTEXT_ID ; |
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| 489 | delete out_DECOD_ADDRESS ; |
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| 490 | delete out_DECOD_INST_IFETCH_PTR ; |
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| 491 | delete out_DECOD_BRANCH_STATE ; |
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| 492 | delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; |
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| 493 | delete out_DECOD_EXCEPTION ; |
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| 494 | |
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| 495 | delete in_EVENT_VAL ; |
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| 496 | delete out_EVENT_ACK ; |
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| 497 | delete in_EVENT_ADDRESS ; |
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[85] | 498 | |
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| 499 | delete param_cache; |
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| 500 | delete cache; |
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[78] | 501 | #endif |
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| 502 | |
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| 503 | delete _Ifetch_unit; |
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| 504 | #ifdef STATISTICS |
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| 505 | delete _parameters_statistics; |
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| 506 | #endif |
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| 507 | } |
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