Changeset 85 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp
- Timestamp:
- May 14, 2008, 3:09:48 PM (16 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp
r82 r85 7 7 */ 8 8 9 #define NB_ITERATION 1 9 #define NB_ITERATION 128 10 10 #define CYCLE_MAX (128*NB_ITERATION) 11 11 12 12 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/include/test.h" 13 #include "../../../../../../../../Environment/Queue/include/Sort_Queue.h" 13 14 #include "Common/include/Test.h" 14 15 #include "Behavioural/include/Allocation.h" 16 17 //using namespace environment; 18 using namespace environment::queue; 19 20 class cache_req_t 21 { 22 public : Tpacket_t packet; 23 public : Taddress_t address; 24 25 public : cache_req_t (Tpacket_t packet, 26 Taddress_t address) 27 { 28 this->packet = packet ; 29 this->address = address; 30 } 31 }; 15 32 16 33 void test (string name, … … 20 37 21 38 #ifdef STATISTICS 22 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5, 50);39 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1024); 23 40 #endif 24 41 … … 142 159 srand(seed); 143 160 161 const int32_t percent_transaction_icache_req = 75; 162 const int32_t percent_transaction_icache_rsp = 75; 163 const int32_t percent_transaction_predict = 75; 164 const int32_t percent_transaction_event = 5; 165 const int32_t percent_hit = 90; 166 const uint32_t delay_miss_min = 5; 167 const uint32_t delay_miss_max = 10; 168 144 169 SC_START(0); 145 170 LABEL("Initialisation"); 171 172 uint32_t jump = 7 ;// packet 173 uint32_t nb_packet_in = 1; 174 uint32_t nb_packet_out = 1; 175 176 Tcontrol_t c_val = false; 177 Tcontrol_t n_val = false; 178 Tcontrol_t nn_val = false; 179 180 Tgeneral_data_t c_addr = 0x100; 181 Tgeneral_data_t n_addr = 0x100; 182 Tgeneral_data_t nn_addr = 0x100; 183 184 Tcontrol_t c_enable [_param->_nb_instruction]; 185 Tcontrol_t n_enable [_param->_nb_instruction]; 186 187 Tcontrol_t c_is_ds_take = 0; 188 Tcontrol_t n_is_ds_take = 0; 189 Tcontrol_t nn_is_ds_take = 0; 190 191 bool slot_use [_param->_size_queue]; 192 193 environment::queue::Parameters * param_cache = new environment::queue::Parameters(_param->_size_queue); 194 Sort_Queue<cache_req_t*> * cache = new Sort_Queue<cache_req_t*> ("cache",param_cache); 195 196 cache->reset(); 197 198 for (uint32_t i=0; i<_param->_size_queue; i++) 199 slot_use [i] = false; 200 201 c_enable [0] = 1; 202 for (uint32_t i=1; i<_param->_nb_instruction; i++) 203 c_enable [i] = 0; 146 204 147 205 LABEL("Reset"); … … 150 208 in_NRESET->write(1); 151 209 210 LABEL("Test no out val/ack"); 211 212 TEST(Tcontrol_t,out_ICACHE_REQ_VAL->read(), 0); 213 TEST(Tcontrol_t,out_ICACHE_RSP_ACK->read(), 1); 214 TEST(Tcontrol_t,out_PREDICT_VAL ->read(), 1); 215 TEST(Tcontrol_t,out_EVENT_ACK ->read(), 1); 216 217 for (uint32_t i=0; i<_param->_nb_instruction; i++) 218 TEST(Tcontrol_t,out_DECOD_VAL [i]->read(), 0); 219 220 LABEL("Send Reset"); 221 do 222 { 223 in_EVENT_VAL ->write(1); 224 in_EVENT_ADDRESS->write(n_addr); 225 SC_START(1); 226 } while (out_EVENT_ACK->read() == false); 227 in_EVENT_VAL ->write(0); 228 229 n_val = 1; 230 152 231 LABEL("Loop of Test"); 153 232 … … 156 235 LABEL("Iteration %d",iteration); 157 236 158 SC_START(100); 237 // PREDICT 238 { 239 in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); 240 241 SC_START(0); 242 243 Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); 244 245 uint32_t begin = addr%_param->_nb_instruction; 246 uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); 247 Tcontrol_t take = (nb_packet_in%jump)==0; 248 249 if (take) 250 addr += 0x100; 251 else 252 addr += end-begin+1; 253 254 for (uint32_t i=0; i<_param->_nb_instruction; i++) 255 in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); 256 in_PREDICT_PC_NEXT ->write(addr); 257 in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); 258 in_PREDICT_INST_IFETCH_PTR ->write(0); 259 in_PREDICT_BRANCH_STATE ->write(0); 260 in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); 261 } 262 263 // DECOD 264 { 265 uint32_t nb_decod = (rand()%_param->_nb_instruction); 266 267 for (uint32_t i=0; i<_param->_nb_instruction; i++) 268 in_DECOD_ACK [i]->write(i<=nb_decod); 269 } 270 271 // EVENT 272 in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); 273 in_EVENT_ADDRESS->write(0x100); 274 275 // ICACHE_REQ 276 in_ICACHE_REQ_ACK->write((rand()%100)<percent_transaction_icache_req); 277 278 // ICACHE_RSP 279 { 280 Tcontrol_t val = false; 281 if (not cache->empty()) 282 { 283 slot_t<cache_req_t *> cache_rsp = cache->read(); 284 285 val = (cache_rsp._delay == 0); 286 287 Tpacket_t packet = cache_rsp._data->packet ; 288 Taddress_t address = cache_rsp._data->address; 289 290 in_ICACHE_RSP_PACKET_ID ->write(packet); 291 for (uint32_t i=0; i<_param->_nb_instruction; i++) 292 in_ICACHE_RSP_INSTRUCTION [i]->write(address+i); 293 in_ICACHE_RSP_ERROR ->write(0); 294 } 295 296 in_ICACHE_RSP_VAL->write(val); 297 } 298 299 //------------------------------------------------- 300 SC_START(0); 301 //------------------------------------------------- 302 303 if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read()) 304 { 305 LABEL("ICACHE_REQ : Transaction accepted"); 306 307 Tpacket_t packet = (_param->_have_port_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0; 308 Taddress_t address = out_ICACHE_REQ_ADDRESS->read(); 309 310 TEST(bool ,slot_use[packet], false); 311 TEST(Taddress_t,address ,c_addr); 312 313 slot_use[packet] = true; 314 315 uint32_t delay; 316 if ((rand()%100)<percent_hit) 317 delay = 1; 318 else 319 delay = delay_miss_min + (rand()%(delay_miss_max-delay_miss_min+1)); 320 321 cache_req_t * cache_req = new cache_req_t(packet,address); 322 cache->push(delay,cache_req); 323 324 c_val = 0; 325 nb_packet_in ++; 326 } 327 328 { 329 bool find=false; 330 331 Taddress_t addr=out_DECOD_ADDRESS->read(); 332 for (uint32_t i=0; i<_param->_nb_instruction; i++) 333 if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read()) 334 { 335 Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read(); 336 LABEL("DECOD [%d] : Transaction accepted",i); 337 LABEL(" address : 0x%x",addr); 338 LABEL(" instruction : 0x%x",inst); 339 340 find = true; 341 TEST(Tinstruction_t,inst,addr+i); 342 } 343 344 if (find) 345 { 346 if (_param->_have_port_instruction_ptr) 347 TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR ->read(), 0); 348 TEST(Tbranch_state_t , out_DECOD_BRANCH_STATE ->read(), 0); 349 if (_param->_have_port_branch_update_prediction_id) 350 TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0); 351 TEST(Texception_t , out_DECOD_EXCEPTION ->read(), 0); 352 } 353 } 354 355 if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read()) 356 { 357 LABEL("ICACHE_RSP : Transaction accepted"); 358 359 slot_use[cache->read()._data->packet] = false; 360 361 cache->pop(); 362 } 363 364 if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) 365 { 366 LABEL("PREDICT : Transaction accepted"); 367 368 if (c_val) 369 TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); 370 TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); 371 TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); 372 373 nn_val = true; 374 nn_addr = in_PREDICT_PC_NEXT ->read(); 375 nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); 376 377 for (uint32_t i=0; i<_param->_nb_instruction; i++) 378 n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); 379 } 380 381 if (not c_val) 382 { 383 if (n_val and nn_val) 384 { 385 c_val = 1; 386 c_addr = n_addr; 387 c_is_ds_take = n_is_ds_take; 388 389 for (uint32_t i=0; i<_param->_nb_instruction; i++) 390 c_enable [i] = n_enable [i]; 391 392 n_val = 1; 393 n_addr = nn_addr; 394 n_is_ds_take = nn_is_ds_take; 395 396 nn_val = 0; 397 } 398 } 399 400 if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) 401 { 402 LABEL("EVENT : Transaction accepted"); 403 404 c_val = false; 405 n_val = true; 406 nn_val = false; 407 408 n_addr = in_EVENT_ADDRESS->read(); 409 n_is_ds_take = 0; 410 411 n_enable [0] = 1; 412 for (uint32_t i=1; i<_param->_nb_instruction; i++) 413 n_enable [i] = 0; 414 } 415 416 417 { 418 string str_c_enable = ""; 419 string str_n_enable = ""; 420 421 for (uint32_t i=0; i<_param->_nb_instruction; i++) 422 { 423 str_c_enable += " " + toString(c_enable [i]); 424 str_n_enable += " " + toString(n_enable [i]); 425 } 426 427 LABEL("-----------------------------------"); 428 LABEL(" * nb_packet_in : %d",nb_packet_in); 429 LABEL(" * nb_packet_out : %d",nb_packet_out); 430 LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); 431 if (nn_val) 432 { 433 LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); 434 } 435 else 436 { 437 LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); 438 } 439 LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); 440 LABEL("-----------------------------------"); 441 } 442 443 SC_START(1); 444 cache->transition(); 159 445 } 160 446 … … 210 496 delete out_EVENT_ACK ; 211 497 delete in_EVENT_ADDRESS ; 498 499 delete param_cache; 500 delete cache; 212 501 #endif 213 502
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