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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 106

Last change on this file since 106 was 106, checked in by rosiere, 15 years ago
1) RAT : Fix bug when update and event in same cycle 2) Context State : Compute depth 3) Load Store Unit : In check logic, translate all access in little endian. More easy to check 4) UFPT : End Event
Property svn:keywords set to `Id`
File size: 141.0 KB

Rev	Line
[78]	1	/*
[88]	2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
[78]	3	*
	4	* [ Description ]
	5	*
	6	* Test
	7	*/
	8
[95]	9	#define NB_ITERATION 16
	10	#define CYCLE_MAX (1024*NB_ITERATION)
[81]	11
[78]	12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
	13	#include "Common/include/Test.h"
	14	#include "Behavioural/include/Allocation.h"
	15
[88]	16	typedef struct
	17	{
	18	uint32_t ufpt_ptr ;
	19	uint32_t upt_ptr ;
	20
	21	Tcontext_t context ;
	22	Taddress_t address_src ;
	23	Taddress_t address_dest;
	24	Taddress_t address_good;
	25	Tbranch_condition_t condition ;
	26	Tcontrol_t take ;
	27	Tcontrol_t take_good ;
	28	Tcontrol_t flag ;
[98]	29	Tcontrol_t no_sequence ;
[88]	30	Tcontrol_t is_accurate ;
	31	Thistory_t history ;
	32	Taddress_t ras_address ;
	33	Tptr_t ras_index ;
	34	Tcontrol_t miss_ifetch ;
	35	Tcontrol_t miss_decod ;
	36	Tcontrol_t miss_commit ;
	37	} request_t;
	38
[78]	39	void test (string name,
	40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
	41	{
	42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
	43
	44	#ifdef STATISTICS
[97]	45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
[78]	46	#endif
	47
[81]	48	Tusage_t _usage = USE_ALL;
	49
	50	// _usage = usage_unset(_usage,USE_SYSTEMC );
	51	// _usage = usage_unset(_usage,USE_VHDL );
	52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
	53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
	54	// _usage = usage_unset(_usage,USE_POSITION );
	55	// _usage = usage_unset(_usage,USE_STATISTICS );
	56	// _usage = usage_unset(_usage,USE_INFORMATION );
	57
	58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
	59	(name.c_str(),
[78]	60	#ifdef STATISTICS
[81]	61	_parameters_statistics,
[78]	62	#endif
[81]	63	_param,
	64	_usage);
[78]	65
	66	#ifdef SYSTEMC
	67	/*********************************************************************
	68	* Déclarations des signaux
	69	*********************************************************************/
	70	string rename;
	71
	72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
	73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
[81]	74
	75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
	76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
	77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
	78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
	79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
	80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
	81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
	82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
	83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
	84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
	85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
[88]	86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
[81]	87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
	88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
	89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
	90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
	91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
	92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
	93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
	94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
	95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
[82]	96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
	97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
[81]	98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
	99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
[88]	100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
[82]	101
[81]	102	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
	103	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
	104	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
	105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
	106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
[98]	107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
[81]	108	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
	109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
	110	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
	111	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
[82]	112
	113	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
	114	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
[98]	115	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
	116	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
[82]	117	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
	118	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
[94]	119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
[82]	120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
	121
[81]	122	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
	123	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
	124	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
	125	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
	126	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
	127	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
	128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
	129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
	130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
	131	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
	132	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
	133	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
[94]	134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
[82]	135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
[81]	136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
	137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
	138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
[95]	139
[97]	140	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
	141	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
[95]	142	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
	143	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
	144
[101]	145	ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
[88]	146	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
	147	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
	148	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
[101]	149	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
[78]	150
	151	/********************************************************
	152	* Instanciation
	153	********************************************************/
	154
	155	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
	156
	157	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
	158	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
	159
[81]	160	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
	161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
	162	if (_param->_have_port_context_id)
	163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
	164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
	165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
	166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
	167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
	168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
	169	if (_param->_have_port_history)
	170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
	171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
	172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
[88]	173	if (_param->_have_port_depth)
	174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
[81]	175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
	176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
	177	if (_param->_have_port_context_id)
	178	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
	179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
	180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
	181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
	182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
	183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
	184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
[82]	185	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
	186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
[88]	187	if (_param->_have_port_depth)
[81]	188	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
	189	//if (_param->_have_port_depth)
	190	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
[88]	191	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
[81]	192	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
	193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
	194	if (_param->_have_port_context_id)
	195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
[88]	196	if (_param->_have_port_depth)
[81]	197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
	198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
[98]	199	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
[81]	200	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
	201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
	202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
	203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
[82]	204
	205	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
	206	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
[98]	207	//if (_param->_have_port_context_id)
	208	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
	209	if (_param->_have_port_depth)
	210	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
	211	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
[82]	212	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
[94]	213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
[82]	214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
	215
[81]	216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
	217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
	218	if (_param->_have_port_context_id)
	219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
	220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
	221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
	222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
	223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
	224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
	225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
	226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
	227	if (_param->_have_port_history)
	228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
	229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
[94]	230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
[82]	231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
[81]	232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
	233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
	234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
[97]	235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
	236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
[95]	237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
[88]	238	if (_param->_have_port_depth)
[82]	239	{
[95]	240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
[88]	241	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
	242	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
[101]	243	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
[82]	244	}
[101]	245	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context);
	246	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context);
[78]	247
	248	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
	249
	250	Time * _time = new Time();
	251
	252	/********************************************************
	253	* Simulation - Begin
	254	********************************************************/
	255
	256	// Initialisation
	257
	258	const uint32_t seed = 0;
	259	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
	260
	261	srand(seed);
	262
[81]	263	const int32_t percent_transaction_predict = 75;
	264	const int32_t percent_transaction_decod = 75;
	265	const int32_t percent_transaction_branch_complete = 75;
	266	const int32_t percent_transaction_update = 75;
[94]	267	const int32_t percent_transaction_branch_event = 75;
[105]	268	const int32_t percent_transaction_event = 75;
[81]	269
[95]	270	const bool test1 = true;
	271	const bool test2 = true;
	272	const bool test3 = true;
[94]	273	const bool test4 = true;
[105]	274	const bool test5 = true;
[88]	275
	276	std::list<request_t> ufpt;
	277	std::list<request_t> upt;
[94]	278	request_t event;
[88]	279
[78]	280	SC_START(0);
	281	LABEL("Initialisation");
	282
	283	LABEL("Reset");
	284	in_NRESET->write(0);
	285	SC_START(5);
	286	in_NRESET->write(1);
	287
[95]	288	Tdepth_t ufpt_bottom [_param->_nb_context];
	289	Tdepth_t ufpt_top [_param->_nb_context];
	290
	291	Tdepth_t upt_bottom [_param->_nb_context];
	292	Tdepth_t upt_top [_param->_nb_context];
	293	Tdepth_t upt_top_event[_param->_nb_context];
[88]	294
	295	for (uint32_t i=0; i<_param->_nb_context; ++i)
[82]	296	{
[95]	297	ufpt_bottom [i] = 0;
	298	ufpt_top [i] = 0;
	299	upt_bottom [i] = 0;
	300	upt_top [i] = 0;
	301	upt_top_event[i] = 0;
[82]	302	}
	303
[88]	304	for (uint32_t i=0; i<_param->_nb_context; ++i)
	305	{
	306	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
	307	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
	308	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
	309	}
[78]	310
	311	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
	312	{
	313	LABEL("Iteration %d",iteration);
[88]	314
	315	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
	316	in_PREDICT_VAL [i]->write(0);
	317	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
	318	in_DECOD_VAL [i]->write(0);
	319	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
	320	in_BRANCH_COMPLETE_VAL [i]->write(0);
	321	for (uint32_t i=0; i<_param->_nb_context; ++i)
	322	in_BRANCH_EVENT_ACK [i]->write(0);
	323	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
	324	in_UPDATE_ACK [i]->write(0);
[95]	325	for (uint32_t i=0; i<_param->_nb_context; ++i)
[97]	326	in_EVENT_VAL [i]->write(0);
	327
[88]	328	//---------------------------------------------------------------------
	329	//---------------------------------------------------------------------
	330	// COMMON CASE
	331	//---------------------------------------------------------------------
	332	//---------------------------------------------------------------------
[94]	333	if (test1)
	334	{
[81]	335	uint32_t context = rand() % _param->_nb_context;
[78]	336
[81]	337	{
[88]	338	LABEL("PREDICT - fill the queue");
[81]	339	uint32_t port = rand() % _param->_nb_inst_predict;
[88]	340
	341	LABEL(" * context : %d",context);
	342	LABEL(" * port : %d",port);
[81]	343
[88]	344	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
[81]	345	{
[88]	346	request_t request;
	347	request.context = context;
	348	request.address_src = 0xdeadbeef+i;
	349	request.address_dest = 0x21071981+i;
	350	request.address_good = request.address_dest;
	351	request.condition = BRANCH_CONDITION_FLAG_SET;
	352	request.take = 1;
	353	request.take_good = 1;
	354	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
[98]	355	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
[88]	356	request.is_accurate = true;
	357	request.miss_ifetch = false;
	358	request.miss_decod = false;
	359	request.miss_commit = false;
	360	request.history = i;
	361	request.ras_address = 0xdeaddead+i;
	362	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
	363	request.ufpt_ptr = ufpt_top [context];
	364	// request.upt_ptr;
	365
	366	bool have_transaction = false;
[81]	367	do
	368	{
	369	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
[88]	370	in_PREDICT_CONTEXT_ID [port]->write(request.context );
	371	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
	372	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	373	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
	374	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
	375	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
	376	in_PREDICT_DIR_HISTORY [port]->write(request.history );
	377	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
	378	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
[81]	379
[88]	380	if (_param->_have_port_depth)
[101]	381	{
[88]	382	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	383	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	384	}
[88]	385	SC_START(0); // fct melay
[81]	386
[88]	387	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
	388	port,
	389	in_PREDICT_VAL [port]->read(),
	390	out_PREDICT_ACK [port]->read(),
	391	in_PREDICT_BTB_IS_ACCURATE [port]->read());
[81]	392
	393	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
	394	{
	395	LABEL("PREDICT [%d] - Transaction accepted",port);
[88]	396	have_transaction = true;
	397
	398	if (_param->_have_port_depth)
	399	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
	400
	401	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
[81]	402	}
	403
[88]	404	SC_START(1); // transition
[81]	405
[88]	406	} while (not have_transaction);
[82]	407
[88]	408	ufpt.push_back(request);
	409
	410	in_PREDICT_VAL [port]->write(0);
	411
	412	if (_param->_have_port_depth)
[101]	413	{
[88]	414	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	415	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	416	}
[81]	417	}
	418	}
	419
[88]	420	{
	421	LABEL("DECOD");
[81]	422	uint32_t port = rand() % _param->_nb_inst_decod;
[88]	423
	424	LABEL(" * context : %d",context);
	425	LABEL(" * port : %d",port);
	426
	427	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
[81]	428	{
[88]	429	request_t request = ufpt.front();
	430
	431	bool have_transaction = false;
[81]	432	do
	433	{
	434	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
[88]	435	in_DECOD_CONTEXT_ID [port]->write(request.context );
	436	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
	437	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	438	in_DECOD_BTB_CONDITION [port]->write(request.condition );
	439	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
	440	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
	441	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
	442	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
	443	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
	444	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
	445	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
	446
	447	SC_START(0); // fct melay
[81]	448
[88]	449	LABEL("DECOD [%d] %d - %d",
	450	port,
	451	in_PREDICT_VAL [port]->read(),
	452	out_PREDICT_ACK [port]->read());
[81]	453
	454	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
	455	{
[88]	456	LABEL("DECOD [%d] - Transaction accepted",port);
	457	have_transaction = true;
	458
	459	request.upt_ptr = upt_top [context];
	460	upt.push_back(request);
	461	ufpt.pop_front();
	462
	463	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
[81]	464	}
[88]	465
	466	SC_START(1); // transition
	467
	468	} while (not have_transaction);
	469
[81]	470	in_DECOD_VAL [port]->write(0);
	471
[88]	472	if (_param->_have_port_depth)
[101]	473	{
[88]	474	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	475	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	476	}
[88]	477	}
	478	}
	479
	480	{
	481	LABEL("BRANCH_COMPLETE - hit ifetch");
[81]	482
[88]	483	uint32_t port = rand() % _param->_nb_inst_branch_complete;
[81]	484
[88]	485	LABEL(" * port : %d",port);
	486
	487	std::list<request_t>::iterator it_upt = upt.begin();
	488
	489	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	490	for (uint32_t i=0; i<upt.size(); i++)
[81]	491	{
[88]	492	bool have_transaction = false;
	493
[81]	494	do
	495	{
[88]	496	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
	497	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
	498	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
	499	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
[98]	500	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
[88]	501
	502	if (_param->_have_port_depth)
[101]	503	{
[88]	504	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	505	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	506	}
[81]	507
	508	SC_START(0);
	509
	510	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
	511
	512	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
	513	{
	514	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
[88]	515	have_transaction = true;
[81]	516
[88]	517	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
	518	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
	519	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
	520	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
	521
	522	it_upt ++;
[81]	523	}
	524
	525	SC_START(1);
[88]	526	} while (not have_transaction);
[81]	527
[88]	528	in_BRANCH_COMPLETE_VAL [port]->write(0);
[81]	529
[88]	530	if (_param->_have_port_depth)
[101]	531	{
[88]	532	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	533	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	534	}
[81]	535	}
	536	}
[88]	537
	538	{
	539	LABEL("UPDATE - hit ifetch");
[81]	540
[88]	541	uint32_t port = 0;
[81]	542
[88]	543	LABEL(" * port : %d",port);
	544	std::list<request_t>::iterator it_upt = upt.begin();
[81]	545
[88]	546	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	547	for (uint32_t i=0; i<upt.size(); i++)
[82]	548	{
[94]	549	bool have_transaction = false;
[81]	550
[94]	551	do
	552	{
	553	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	554
	555	// if (_param->_have_port_depth)
[101]	556	// {
[94]	557	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	558	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	559	// }
[94]	560
	561	SC_START(0);
	562
	563	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	564
	565	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	566	{
	567	LABEL("UPDATE [%d] - Transaction accepted",port);
	568	have_transaction = true;
	569
	570	if (_param->_have_port_context_id)
	571	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
	572	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
	573	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
	574	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
	575	if (update_btb(it_upt->condition))
	576	{
	577	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
	578	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	579	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
	580	}
	581	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
	582	if (update_dir(it_upt->condition))
	583	if (_param->_have_port_history)
	584	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
	585	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
	586	if (update_ras(it_upt->condition))
	587	{
	588	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	589	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
	590	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
	591	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
	592	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
	593	}
	594	++ it_upt;
	595	}
	596
	597	SC_START(1);
	598	} while (not have_transaction);
	599
	600	in_UPDATE_ACK [port]->write(0);
	601	// if (_param->_have_port_depth)
	602	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	603	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	604	}
	605	upt.clear();
	606	}
	607
	608	// Wait Garbage Collector
	609	{
	610	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
	611	// upt_top [context] = (upt_top [context]);
	612
	613	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
	614	(upt_top [context] != out_DEPTH_MAX [context]->read()))
	615	SC_START(1);
	616
	617	}
	618	}
	619
	620	//---------------------------------------------------------------------
	621	//---------------------------------------------------------------------
	622	// DECOD MISS : no RAS in ifetch
	623	//---------------------------------------------------------------------
	624	//---------------------------------------------------------------------
	625	if (test2)
	626	{
	627	uint32_t context = rand() % _param->_nb_context;
	628
	629	{
	630	LABEL("PREDICT - fill the queue");
	631	uint32_t port = rand() % _param->_nb_inst_predict;
	632
	633	LABEL(" * context : %d",context);
	634	LABEL(" * port : %d",port);
	635
	636	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	637	{
	638	request_t request;
	639	request.context = context;
	640	request.address_src = 0xdeadbeef+i;
	641	request.address_dest = 0x21071981+i;
	642	request.address_good = request.address_dest;
	643	request.condition = BRANCH_CONDITION_FLAG_SET;
	644	request.take = 1;
	645	request.take_good = 1;
	646	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
[98]	647	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
[94]	648	request.is_accurate = true;
	649	request.miss_ifetch = false;
	650	request.miss_decod = false;
	651	request.miss_commit = false;
	652	request.history = i;
	653	request.ras_address = 0xdeaddead+i;
	654	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
	655	request.ufpt_ptr = ufpt_top [context];
	656	// request.upt_ptr;
	657
[88]	658	bool have_transaction = false;
[94]	659	do
	660	{
	661	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
	662	in_PREDICT_CONTEXT_ID [port]->write(request.context );
	663	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
	664	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	665	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
	666	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
	667	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
	668	in_PREDICT_DIR_HISTORY [port]->write(request.history );
	669	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
	670	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
	671
	672	if (_param->_have_port_depth)
[101]	673	{
[94]	674	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	675	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	676	}
[94]	677	SC_START(0); // fct melay
	678
	679	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
	680	port,
	681	in_PREDICT_VAL [port]->read(),
	682	out_PREDICT_ACK [port]->read(),
	683	in_PREDICT_BTB_IS_ACCURATE [port]->read());
	684
	685	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
	686	{
	687	LABEL("PREDICT [%d] - Transaction accepted",port);
	688	have_transaction = true;
[81]	689
[94]	690	if (_param->_have_port_depth)
	691	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
	692
	693	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
	694	}
	695
	696	SC_START(1); // transition
	697
	698	} while (not have_transaction);
	699
	700	// ufpt.push_back(request);
	701
	702	in_PREDICT_VAL [port]->write(0);
	703
	704	if (_param->_have_port_depth)
[101]	705	{
[94]	706	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	707	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	708	}
[94]	709	}
	710	}
	711
	712	{
	713	LABEL("DECOD - Miss");
	714	uint32_t port = rand() % _param->_nb_inst_decod;
	715
	716	LABEL(" * context : %d",context);
	717	LABEL(" * port : %d",port);
	718
	719	request_t request;
	720	request.context = context;
	721	request.address_src = 0x14011959;
	722	request.address_dest = 0x25071959; // after = not take
	723	request.address_good = request.address_dest;
	724	request.condition = BRANCH_CONDITION_FLAG_SET;
	725	request.take = 0;
	726	request.take_good = 0;
	727	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
[98]	728	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
[94]	729	request.is_accurate = true;
	730	request.miss_ifetch = false;
	731	request.miss_decod = true ;
	732	request.miss_commit = false;
	733	request.history = 1;
	734	request.ras_address = 0xbabababa;
	735	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
	736	request.ufpt_ptr = ufpt_top [context];
[98]	737	request.upt_ptr = upt_top [context];
[94]	738
	739	event = request;
	740
	741	// for (uint32_t i=0; i<upt.size(); i++)
	742	// just one
	743	{
	744	bool have_transaction = false;
[81]	745	do
	746	{
[94]	747	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
	748	in_DECOD_CONTEXT_ID [port]->write(request.context );
	749	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
	750	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	751	in_DECOD_BTB_CONDITION [port]->write(request.condition );
	752	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
	753	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
	754	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
	755	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
	756	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
	757	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
	758	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
[82]	759
[94]	760	SC_START(0); // fct melay
	761
	762	LABEL("DECOD [%d] %d - %d",
	763	port,
	764	in_PREDICT_VAL [port]->read(),
	765	out_PREDICT_ACK [port]->read());
	766
	767	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
	768	{
	769	LABEL("DECOD [%d] - Transaction accepted",port);
	770	have_transaction = true;
	771
	772	request.upt_ptr = upt_top [context];
	773	upt.push_back(request);
	774	// ufpt.pop_front();
	775
	776	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
	777	}
	778
	779	SC_START(1); // transition
	780
	781	} while (not have_transaction);
	782
	783	in_DECOD_VAL [port]->write(0);
	784
	785	if (_param->_have_port_depth)
[101]	786	{
[94]	787	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	788	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	789	}
[94]	790	}
	791	}
	792
	793	{
	794	LABEL("BRANCH_COMPLETE - hit ifetch");
	795
	796	uint32_t port = rand() % _param->_nb_inst_branch_complete;
	797
	798	LABEL(" * port : %d",port);
	799
	800	std::list<request_t>::iterator it_upt = upt.begin();
	801
	802	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	803	// for (uint32_t i=0; i<upt.size(); i++)
	804	// just one
	805	{
	806	bool have_transaction = false;
	807
	808	do
	809	{
	810	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
	811	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
	812	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
	813	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
[98]	814	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
[94]	815
	816	if (_param->_have_port_depth)
[101]	817	{
[94]	818	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	819	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	820	}
[94]	821	SC_START(0);
	822
	823	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
	824
	825	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
	826	{
	827	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
	828	have_transaction = true;
	829
	830	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
	831	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
	832	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
	833	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
	834
	835	it_upt ++;
	836	}
	837
	838	SC_START(1);
	839	} while (not have_transaction);
	840
	841	in_BRANCH_COMPLETE_VAL [port]->write(0);
	842
	843	if (_param->_have_port_depth)
[101]	844	{
[94]	845	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	846	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	847	}
[94]	848	}
	849	}
	850
	851	{
	852	LABEL("UPDATE - hit ifetch");
	853
	854	uint32_t port = 0;
	855
	856	LABEL(" * port : %d",port);
	857	std::list<request_t>::iterator it_upt = upt.begin();
	858
	859	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	860	// for (uint32_t i=0; i<upt.size(); i++)
	861	// just one
	862	{
	863	bool have_transaction = false;
	864
	865	do
	866	{
[88]	867	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	868
	869	// if (_param->_have_port_depth)
	870	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	871	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[81]	872
	873	SC_START(0);
[94]	874
[88]	875	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
[81]	876
[88]	877	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
[81]	878	{
[88]	879	LABEL("UPDATE [%d] - Transaction accepted",port);
	880	have_transaction = true;
[81]	881
[88]	882	if (_param->_have_port_context_id)
[94]	883	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
	884	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
	885	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
	886	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
[88]	887	if (update_btb(it_upt->condition))
	888	{
[94]	889	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
	890	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	891	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
[88]	892	}
[94]	893	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
	894
[88]	895	if (update_dir(it_upt->condition))
	896	if (_param->_have_port_history)
[94]	897	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
	898	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
[88]	899	if (update_ras(it_upt->condition))
	900	{
[94]	901	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	902	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
	903	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
	904	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
	905	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
[88]	906	}
	907	++ it_upt;
[82]	908	}
[88]	909
[81]	910	SC_START(1);
[88]	911	} while (not have_transaction);
[81]	912
[88]	913	in_UPDATE_ACK [port]->write(0);
	914	// if (_param->_have_port_depth)
	915	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	916	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[81]	917	}
[88]	918	upt.clear();
[81]	919	}
	920
[94]	921	{
	922	LABEL("BRANCH_EVENT - have miss decod");
	923
	924	uint32_t port = context;
	925
	926	{
	927	bool have_transaction = false;
	928
	929	do
	930	{
	931	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
	932
	933	SC_START(0);
	934
	935	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
	936
	937	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
	938	{
	939	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
	940	have_transaction = true;
[98]	941
	942	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
[94]	943	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
	944	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
	945	if (event.take)
	946	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
	947
	948	event.address_src = 0;
	949	event.take = 0;
	950	event.address_dest = 0;
	951	}
	952
	953	SC_START(1);
	954	} while (not have_transaction);
	955
	956	in_BRANCH_EVENT_ACK [port]->write(0);
	957	}
	958	}
[95]	959
	960	{
	961	LABEL("EVENT_STATE");
	962
	963	SC_START(1);
[97]	964	in_EVENT_VAL [context]->write(1);
[105]	965	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
[94]	966
[95]	967	SC_START(1);
[97]	968	in_EVENT_VAL [context]->write(0);
[95]	969	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
	970	}
[94]	971
[88]	972	// Wait Garbage Collector
	973	{
[94]	974	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
[88]	975	// upt_top [context] = (upt_top [context]);
	976
	977	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
	978	(upt_top [context] != out_DEPTH_MAX [context]->read()))
	979	SC_START(1);
	980
	981	}
[94]	982	}
	983
	984	//---------------------------------------------------------------------
	985	//---------------------------------------------------------------------
	986	// DECOD MISS : with RAS in ifetch
	987	//---------------------------------------------------------------------
	988	//---------------------------------------------------------------------
	989	if (test3)
	990	{
	991	uint32_t context = rand() % _param->_nb_context;
	992	uint32_t have_ras = false;
	993	{
	994	LABEL("PREDICT - fill the queue");
	995	uint32_t port = rand() % _param->_nb_inst_predict;
	996
	997	LABEL(" * context : %d",context);
	998	LABEL(" * port : %d",port);
	999
	1000	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1001	{
	1002	request_t request;
	1003	request.context = context;
	1004	request.address_src = 0xdeadbeef+i;
	1005	request.address_dest = 0x21071981+i;
	1006	request.address_good = request.address_dest;
	1007	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
	1008
	1009	have_ras \|= (update_ras(request.condition));
	1010
	1011	request.take = 1;
	1012	request.take_good = 1;
	1013	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
[98]	1014	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
[94]	1015	request.is_accurate = true;
	1016	request.miss_ifetch = false;
	1017	request.miss_decod = true ;
	1018	request.miss_commit = false;
	1019	request.history = i;
	1020	request.ras_address = 0x12344321+i;
	1021	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
	1022	request.ufpt_ptr = ufpt_top [context];
	1023	// request.upt_ptr;
	1024
	1025	bool have_transaction = false;
	1026	do
	1027	{
	1028	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
	1029	in_PREDICT_CONTEXT_ID [port]->write(request.context );
	1030	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
	1031	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	1032	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
	1033	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
	1034	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
	1035	in_PREDICT_DIR_HISTORY [port]->write(request.history );
	1036	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
	1037	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
	1038
	1039	if (_param->_have_port_depth)
[101]	1040	{
[94]	1041	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1042	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1043	}
[94]	1044	SC_START(0); // fct melay
	1045
	1046	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
	1047	port,
	1048	in_PREDICT_VAL [port]->read(),
	1049	out_PREDICT_ACK [port]->read(),
	1050	in_PREDICT_BTB_IS_ACCURATE [port]->read());
	1051
	1052	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
	1053	{
	1054	LABEL("PREDICT [%d] - Transaction accepted",port);
	1055	have_transaction = true;
	1056
	1057	if (_param->_have_port_depth)
	1058	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
	1059
	1060	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
	1061	}
	1062
	1063	SC_START(1); // transition
	1064
	1065	} while (not have_transaction);
	1066
	1067	ufpt.push_back(request); // to update
	1068
	1069	in_PREDICT_VAL [port]->write(0);
	1070
	1071	if (_param->_have_port_depth)
[101]	1072	{
[94]	1073	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1074	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1075	}
[94]	1076	}
	1077	}
	1078
	1079	{
	1080	LABEL("DECOD - Miss");
	1081	uint32_t port = rand() % _param->_nb_inst_decod;
	1082
	1083	LABEL(" * context : %d",context);
	1084	LABEL(" * port : %d",port);
	1085
	1086	request_t request;
	1087	request.context = context;
	1088	request.address_src = 0x14011959;
	1089	request.address_dest = 0x25071959; // after = not take
	1090	request.address_good = request.address_dest;
	1091	request.condition = BRANCH_CONDITION_FLAG_SET;
	1092	request.take = 0;
	1093	request.take_good = 0;
	1094	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
[98]	1095	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
[94]	1096	request.is_accurate = true;
	1097	request.miss_ifetch = false;
	1098	request.miss_decod = true ;
	1099	request.miss_commit = false;
	1100	request.history = 1;
	1101	request.ras_address = 0xbabababa;
	1102	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
	1103	request.ufpt_ptr = ufpt_top [context];
[98]	1104	request.upt_ptr = upt_top [context];
[94]	1105
	1106	event = request;
	1107
	1108	// for (uint32_t i=0; i<upt.size(); i++)
	1109	// just one
	1110	{
	1111	bool have_transaction = false;
	1112	do
	1113	{
	1114	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
	1115	in_DECOD_CONTEXT_ID [port]->write(request.context );
	1116	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
	1117	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	1118	in_DECOD_BTB_CONDITION [port]->write(request.condition );
	1119	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
	1120	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
	1121	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
	1122	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
	1123	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
	1124	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
	1125	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
	1126
	1127	SC_START(0); // fct melay
	1128
	1129	LABEL("DECOD [%d] %d - %d",
	1130	port,
	1131	in_PREDICT_VAL [port]->read(),
	1132	out_PREDICT_ACK [port]->read());
	1133
	1134	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
	1135	{
	1136	LABEL("DECOD [%d] - Transaction accepted",port);
	1137	have_transaction = true;
	1138
	1139	request.upt_ptr = upt_top [context];
	1140	upt.push_back(request);
	1141	// ufpt.pop_front();
	1142
	1143	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
	1144	}
	1145
	1146	SC_START(1); // transition
	1147
	1148	} while (not have_transaction);
	1149
	1150	in_DECOD_VAL [port]->write(0);
	1151
	1152	if (_param->_have_port_depth)
[101]	1153	{
[94]	1154	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1155	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1156	}
[94]	1157	}
	1158	}
	1159
	1160	{
	1161	LABEL("BRANCH_COMPLETE - hit ifetch");
	1162
	1163	uint32_t port = rand() % _param->_nb_inst_branch_complete;
	1164
	1165	LABEL(" * port : %d",port);
	1166
	1167	std::list<request_t>::iterator it_upt = upt.begin();
	1168
	1169	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1170	// for (uint32_t i=0; i<upt.size(); i++)
	1171	// just one
	1172	{
	1173	bool have_transaction = false;
	1174
	1175	do
	1176	{
	1177	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
	1178	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
	1179	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
	1180	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
[98]	1181	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
[94]	1182
	1183	if (_param->_have_port_depth)
[101]	1184	{
[94]	1185	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1186	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1187	}
[94]	1188	SC_START(0);
	1189
	1190	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
	1191
	1192	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
	1193	{
	1194	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
	1195	have_transaction = true;
	1196
	1197	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
	1198	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
	1199	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
	1200	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
	1201
	1202	it_upt ++;
	1203	}
	1204
	1205	SC_START(1);
	1206	} while (not have_transaction);
	1207
	1208	in_BRANCH_COMPLETE_VAL [port]->write(0);
	1209
	1210	if (_param->_have_port_depth)
[101]	1211	{
[94]	1212	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1213	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1214	}
[94]	1215	}
	1216	}
	1217
	1218	if (have_ras)
	1219	{
	1220	LABEL("UPDATE - Update UPFT");
	1221
	1222	uint32_t port = 0;
	1223
	1224	LABEL(" * port : %d",port);
	1225	std::list<request_t>::iterator it_ufpt = ufpt.end();
	1226	-- it_ufpt;
	1227
	1228	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1229	{
	1230	bool have_transaction = false;
	1231
	1232	do
	1233	{
	1234	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	1235
	1236	// if (_param->_have_port_depth)
	1237	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
	1238	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
	1239
	1240	SC_START(0);
	1241
	1242	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	1243
	1244	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	1245	{
	1246	LABEL("UPDATE [%d] - Transaction accepted",port);
	1247	have_transaction = true;
	1248
	1249	if (_param->_have_port_context_id)
	1250	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
	1251	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
	1252	it_ufpt->miss_decod or
	1253	it_ufpt->miss_commit ));
	1254	// if (update_btb(it_ufpt->condition) or
	1255	// update_dir(it_ufpt->condition))
	1256	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
	1257	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
	1258	// if (update_btb(it_ufpt->condition))
	1259	// {
	1260	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
	1261	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
	1262	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
	1263	// }
	1264	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
	1265
	1266	// if (update_dir(it_ufpt->condition))
	1267	// if (_param->_have_port_history)
	1268	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
	1269	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
	1270	if (update_ras(it_ufpt->condition))
	1271	{
	1272	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	1273	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
	1274	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
	1275	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
	1276
	1277	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
	1278	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
	1279	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
	1280	}
	1281	}
	1282
	1283	SC_START(1);
	1284	} while (not have_transaction);
	1285
	1286	-- it_ufpt;
	1287
	1288
	1289	in_UPDATE_ACK [port]->write(0);
	1290	// if (_param->_have_port_depth)
	1291	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
	1292	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
	1293	}
	1294	}
	1295	ufpt.clear();
	1296
	1297	{
	1298	LABEL("UPDATE - hit ifetch");
	1299
	1300	uint32_t port = 0;
	1301
	1302	LABEL(" * port : %d",port);
	1303	std::list<request_t>::iterator it_upt = upt.begin();
	1304
	1305	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1306	// for (uint32_t i=0; i<upt.size(); i++)
	1307	// just one
	1308	{
	1309	bool have_transaction = false;
	1310
	1311	do
	1312	{
	1313	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	1314
	1315	// if (_param->_have_port_depth)
	1316	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1317	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	1318
	1319	SC_START(0);
	1320
	1321	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	1322
	1323	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	1324	{
	1325	LABEL("UPDATE [%d] - Transaction accepted",port);
	1326	have_transaction = true;
	1327
	1328	if (_param->_have_port_context_id)
	1329	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
	1330	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
	1331	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
	1332	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
	1333	if (update_btb(it_upt->condition))
	1334	{
	1335	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
	1336	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	1337	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
	1338	}
	1339	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
	1340
	1341	if (update_dir(it_upt->condition))
	1342	if (_param->_have_port_history)
	1343	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
	1344	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
	1345	if (update_ras(it_upt->condition))
	1346	{
	1347	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	1348	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
	1349	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
	1350	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
	1351	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
	1352	}
	1353	++ it_upt;
	1354	}
	1355
	1356	SC_START(1);
	1357	} while (not have_transaction);
	1358
	1359	in_UPDATE_ACK [port]->write(0);
	1360	// if (_param->_have_port_depth)
	1361	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1362	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	1363	}
	1364	}
	1365	upt.clear();
	1366
	1367	{
	1368	LABEL("BRANCH_EVENT - have miss decod");
	1369
	1370	uint32_t port = context;
	1371
	1372	{
	1373	bool have_transaction = false;
	1374
	1375	do
	1376	{
	1377	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
	1378
	1379	SC_START(0);
	1380
	1381	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
	1382
	1383	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
	1384	{
	1385	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
	1386	have_transaction = true;
	1387
[98]	1388	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
[94]	1389	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
	1390	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
	1391	if (event.take)
	1392	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
	1393
	1394	event.address_src = 0;
	1395	event.take = 0;
	1396	event.address_dest = 0;
	1397	}
	1398
	1399	SC_START(1);
	1400	} while (not have_transaction);
	1401
	1402	in_BRANCH_EVENT_ACK [port]->write(0);
	1403	}
	1404	}
	1405
[95]	1406	{
	1407	LABEL("EVENT_STATE");
	1408
	1409	SC_START(1);
[97]	1410	in_EVENT_VAL [context]->write(1);
[105]	1411	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
[95]	1412
	1413	SC_START(1);
[97]	1414	in_EVENT_VAL [context]->write(0);
[95]	1415	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
	1416	}
	1417
[94]	1418	// Wait Garbage Collector
	1419	{
	1420	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
	1421	// upt_top [context] = (upt_top [context]);
	1422
	1423	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
	1424	(upt_top [context] != out_DEPTH_MAX [context]->read()))
	1425	SC_START(1);
	1426	}
[81]	1427	}
[94]	1428
	1429	//---------------------------------------------------------------------
	1430	//---------------------------------------------------------------------
	1431	// COMMIT MISS : with RAS in UPFT and UPT
	1432	//---------------------------------------------------------------------
	1433	//---------------------------------------------------------------------
	1434	if (test4)
	1435	{
	1436	uint32_t context = rand() % _param->_nb_context;
	1437	uint32_t have_ufpt_ras = false;
	1438	uint32_t have_upt_ras = false;
	1439	{
	1440	LABEL("PREDICT - fill the queue");
	1441	uint32_t port = rand() % _param->_nb_inst_predict;
	1442
	1443	LABEL(" * context : %d",context);
	1444	LABEL(" * port : %d",port);
	1445
	1446	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1447	{
	1448	request_t request;
	1449	request.context = context;
	1450	request.address_src = rand();
	1451	request.address_dest = rand();
	1452
	1453	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
[81]	1454
[94]	1455	request.take = 1;
	1456	request.take_good = 1;
	1457	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
[98]	1458	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
[95]	1459	request.is_accurate = true ;
[94]	1460	request.miss_ifetch = false;
	1461	request.miss_decod = false;
	1462	request.miss_commit = false;
	1463	request.history = i;
	1464	request.ras_address = rand();
	1465	request.ras_index = rand()%_param->_size_ras_index[context];
	1466	request.ufpt_ptr = ufpt_top [context];
	1467	// request.upt_ptr;
	1468
	1469	bool have_transaction = false;
	1470	do
	1471	{
	1472	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
	1473	in_PREDICT_CONTEXT_ID [port]->write(request.context );
	1474	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
	1475	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	1476	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
	1477	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
	1478	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
	1479	in_PREDICT_DIR_HISTORY [port]->write(request.history );
	1480	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
	1481	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
	1482
	1483	if (_param->_have_port_depth)
[101]	1484	{
[94]	1485	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1486	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1487	}
[94]	1488	SC_START(0); // fct melay
	1489
	1490	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
	1491	port,
	1492	in_PREDICT_VAL [port]->read(),
	1493	out_PREDICT_ACK [port]->read(),
	1494	in_PREDICT_BTB_IS_ACCURATE [port]->read());
	1495
	1496	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
	1497	{
	1498	LABEL("PREDICT [%d] - Transaction accepted",port);
	1499	have_transaction = true;
	1500
	1501	if (_param->_have_port_depth)
	1502	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
	1503
	1504	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
	1505	}
	1506
	1507	SC_START(1); // transition
	1508
	1509	} while (not have_transaction);
	1510
	1511	ufpt.push_back(request); // to update
	1512
	1513	in_PREDICT_VAL [port]->write(0);
	1514
	1515	if (_param->_have_port_depth)
[101]	1516	{
	1517	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
[94]	1518	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1519	}
[94]	1520	}
	1521	}
	1522
	1523	{
	1524	LABEL("DECOD");
	1525	uint32_t port = rand() % _param->_nb_inst_decod;
	1526
	1527	LABEL(" * context : %d",context);
	1528	LABEL(" * port : %d",port);
	1529
	1530	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1531	{
	1532	request_t request = ufpt.front();
	1533
	1534	bool have_transaction = false;
	1535	do
	1536	{
	1537	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
	1538	in_DECOD_CONTEXT_ID [port]->write(request.context );
	1539	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
	1540	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	1541	in_DECOD_BTB_CONDITION [port]->write(request.condition );
	1542	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
	1543	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
	1544	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
	1545	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
	1546	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
	1547	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
	1548	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
	1549
	1550	have_upt_ras \|= (update_ras(request.condition));
	1551
	1552	SC_START(0); // fct melay
	1553
	1554	LABEL("DECOD [%d] %d - %d",
	1555	port,
[95]	1556	in_DECOD_VAL [port]->read(),
	1557	out_DECOD_ACK [port]->read());
[94]	1558
	1559	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
	1560	{
	1561	LABEL("DECOD [%d] - Transaction accepted",port);
	1562	have_transaction = true;
	1563
	1564	request.upt_ptr = upt_top [context];
	1565	upt.push_back(request);
	1566	ufpt.pop_front();
	1567
	1568	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
	1569	}
	1570
	1571	SC_START(1); // transition
	1572
	1573	} while (not have_transaction);
	1574
	1575	in_DECOD_VAL [port]->write(0);
	1576
	1577	if (_param->_have_port_depth)
[101]	1578	{
	1579	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
[94]	1580	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1581	}
[94]	1582	}
	1583	}
	1584
	1585	{
	1586	LABEL("PREDICT - fill the queue");
	1587	uint32_t port = rand() % _param->_nb_inst_predict;
	1588
	1589	LABEL(" * context : %d",context);
	1590	LABEL(" * port : %d",port);
	1591
	1592	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1593	{
	1594	request_t request;
	1595	request.context = context;
	1596	request.address_src = rand();
	1597	request.address_dest = rand();
	1598	request.address_good = request.address_dest;
	1599	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
	1600
	1601	have_ufpt_ras \|= (update_ras(request.condition));
	1602
	1603	request.take = 1;
	1604	request.take_good = 1;
	1605	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
[98]	1606	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
[95]	1607	request.is_accurate = true ;
[94]	1608	request.miss_ifetch = false;
	1609	request.miss_decod = false;
	1610	request.miss_commit = true;
	1611	request.history = i;
	1612	request.ras_address = rand();
	1613	request.ras_index = rand()%_param->_size_ras_index[context];
	1614	request.ufpt_ptr = ufpt_top [context];
	1615	// request.upt_ptr;
	1616
	1617	bool have_transaction = false;
	1618	do
	1619	{
	1620	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
	1621	in_PREDICT_CONTEXT_ID [port]->write(request.context );
	1622	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
	1623	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	1624	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
	1625	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
	1626	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
	1627	in_PREDICT_DIR_HISTORY [port]->write(request.history );
	1628	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
	1629	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
	1630
	1631	if (_param->_have_port_depth)
[101]	1632	{
[94]	1633	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1634	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1635	}
[94]	1636	SC_START(0); // fct melay
	1637
	1638	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
	1639	port,
	1640	in_PREDICT_VAL [port]->read(),
	1641	out_PREDICT_ACK [port]->read(),
	1642	in_PREDICT_BTB_IS_ACCURATE [port]->read());
	1643
	1644	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
	1645	{
	1646	LABEL("PREDICT [%d] - Transaction accepted",port);
	1647	have_transaction = true;
	1648
	1649	if (_param->_have_port_depth)
	1650	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
	1651
	1652	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
	1653	}
	1654
	1655	SC_START(1); // transition
	1656
	1657	} while (not have_transaction);
	1658
	1659	ufpt.push_back(request); // to update
	1660
	1661	in_PREDICT_VAL [port]->write(0);
	1662
	1663	if (_param->_have_port_depth)
[101]	1664	{
	1665	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
[94]	1666	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1667	}
[94]	1668	}
	1669	}
	1670
	1671	std::list<request_t>::iterator it_event;
	1672	{
[95]	1673	LABEL("BRANCH_COMPLETE - Miss ifetch");
[94]	1674
	1675	uint32_t port = rand() % _param->_nb_inst_branch_complete;
	1676
	1677	LABEL(" * port : %d",port);
	1678
	1679	// middle
	1680	it_event = upt.begin();
	1681	for (uint32_t i=0; i < (upt.size()>>1); ++i)
	1682	it_event ++;
	1683
	1684	for (std::list<request_t>::iterator it_upt = it_event;
	1685	it_upt != upt.end();
	1686	++it_upt)
	1687	it_upt->miss_commit = true;
	1688
	1689	if (update_ras(it_event->condition))
[95]	1690	{
	1691	it_event->address_good = ~(it_event->address_dest);
	1692	}
[94]	1693	else
	1694	{
	1695	it_event->address_good = it_event->address_dest;
	1696	it_event->flag = not it_event->flag;
[98]	1697	it_event->no_sequence = not it_event->no_sequence;
[94]	1698	it_event->take_good = not it_event->take_good;
	1699	}
	1700
	1701	event = *it_event;
	1702
	1703
	1704	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1705	// for (uint32_t i=0; i<upt.size(); i++)
	1706	// just one
	1707	{
	1708	bool have_transaction = false;
	1709
	1710	do
	1711	{
	1712	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
	1713	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
	1714	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
	1715	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
[98]	1716	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
[94]	1717
	1718	if (_param->_have_port_depth)
[101]	1719	{
[94]	1720	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1721	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1722	}
	1723
[94]	1724	SC_START(0);
	1725
	1726	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
	1727
	1728	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
	1729	{
	1730	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
[98]	1731	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
	1732	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
	1733	LABEL(" * CONDITION : %d" ,it_event->condition );
	1734	LABEL(" * ADDRESS : %.8x",it_event->address_good);
	1735	LABEL(" * FLAG : %d" ,it_event->flag );
	1736	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
[94]	1737
	1738	have_transaction = true;
	1739
	1740	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
	1741	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
	1742	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
	1743	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
	1744
[95]	1745	upt_top_event [it_event->context] = upt_top [it_event->context];
	1746	upt_top [it_event->context] = it_event->upt_ptr;
[94]	1747	}
	1748
	1749	SC_START(1);
	1750	} while (not have_transaction);
	1751
	1752	in_BRANCH_COMPLETE_VAL [port]->write(0);
	1753
	1754	if (_param->_have_port_depth)
[101]	1755	{
[94]	1756	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1757	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1758	}
[94]	1759	}
	1760	}
[95]	1761
	1762	{
	1763	LABEL("BRANCH_COMPLETE - Hit ifetch");
	1764
	1765	uint32_t port = rand() % _param->_nb_inst_branch_complete;
	1766
	1767	LABEL(" * port : %d",port);
	1768
	1769	std::list<request_t>::iterator it_upt = upt.begin();
	1770
	1771	while (it_upt != it_event)
	1772	{
	1773	bool have_transaction = false;
	1774
	1775	do
	1776	{
	1777	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
	1778	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
	1779	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
	1780	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
[98]	1781	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
[95]	1782
	1783	if (_param->_have_port_depth)
[101]	1784	{
[95]	1785	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1786	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1787	}
[95]	1788	SC_START(0);
	1789
	1790	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
	1791
	1792	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
	1793	{
	1794	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
[98]	1795	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
	1796	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
	1797	LABEL(" * CONDITION : %d" ,it_upt->condition );
	1798	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
	1799	LABEL(" * FLAG : %d" ,it_upt->flag );
	1800	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
[95]	1801
	1802	have_transaction = true;
	1803
	1804	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
	1805	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
	1806	it_upt->take_good = it_upt->take;
	1807	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
	1808	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	1809
	1810	it_upt++;
	1811	}
	1812
	1813	SC_START(1);
	1814	} while (not have_transaction);
	1815
	1816	in_BRANCH_COMPLETE_VAL [port]->write(0);
	1817
	1818	if (_param->_have_port_depth)
[101]	1819	{
[95]	1820	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1821	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
[101]	1822	}
[95]	1823	}
	1824	}
[94]	1825
	1826	if (have_ufpt_ras)
	1827	{
	1828	LABEL("UPDATE - Update UPFT");
	1829
	1830	uint32_t port = 0;
	1831
	1832	LABEL(" * port : %d",port);
	1833	std::list<request_t>::iterator it_ufpt = ufpt.end();
	1834	-- it_ufpt;
	1835
	1836	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	1837	{
	1838	bool have_transaction = false;
	1839
	1840	do
	1841	{
	1842	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	1843
	1844	// if (_param->_have_port_depth)
	1845	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
	1846	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
	1847
	1848	SC_START(0);
	1849
	1850	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	1851
	1852	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	1853	{
	1854	LABEL("UPDATE [%d] - Transaction accepted",port);
	1855	have_transaction = true;
	1856
	1857	if (_param->_have_port_context_id)
	1858	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
	1859	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
	1860	it_ufpt->miss_decod or
	1861	it_ufpt->miss_commit ));
	1862	// if (update_btb(it_ufpt->condition) or
	1863	// update_dir(it_ufpt->condition))
	1864	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
	1865	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
	1866	// if (update_btb(it_ufpt->condition))
	1867	// {
	1868	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
	1869	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
	1870	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
	1871	// }
	1872	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
	1873
	1874	// if (update_dir(it_ufpt->condition))
	1875	// if (_param->_have_port_history)
	1876	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
	1877	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
	1878	if (update_ras(it_ufpt->condition))
	1879	{
	1880	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	1881	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
	1882	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
	1883	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
	1884	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
	1885	}
	1886	}
	1887
	1888	SC_START(1);
	1889	} while (not have_transaction);
	1890
	1891	-- it_ufpt;
	1892
	1893
	1894	in_UPDATE_ACK [port]->write(0);
	1895	// if (_param->_have_port_depth)
	1896	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
	1897	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
	1898	}
	1899	}
	1900	ufpt.clear();
	1901
	1902	{
[95]	1903	LABEL("UPDATE - upt (after event)");
[94]	1904
	1905	uint32_t port = 0;
	1906
	1907	LABEL(" * port : %d",port);
	1908	std::list<request_t>::iterator it_upt = upt.end();
	1909
	1910	// for (uint32_t i=0; i<upt.size(); i++)
[95]	1911	do
[94]	1912	{
[95]	1913	--it_upt;
	1914
[94]	1915	bool have_transaction = false;
	1916
[95]	1917	if (need_update(it_upt->condition))
[94]	1918	do
	1919	{
	1920	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	1921
	1922	// if (_param->_have_port_depth)
	1923	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1924	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	1925
	1926	SC_START(0);
	1927
	1928	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	1929
	1930	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	1931	{
	1932	LABEL("UPDATE [%d] - Transaction accepted",port);
[95]	1933	LABEL(" * address_src : %.8x",it_upt->address_src);
	1934	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
	1935
[94]	1936	have_transaction = true;
	1937
[95]	1938	bool btb_val = ((it_upt == it_event) and
	1939	(update_btb(it_upt->condition)));
	1940	bool dir_val = ((it_upt == it_event) and
	1941	update_dir(it_upt->condition) and
	1942	not (it_upt->miss_ifetch or it_upt->miss_decod));
	1943	bool ras_val = update_ras(it_upt->condition);
	1944
[94]	1945	if (_param->_have_port_context_id)
	1946	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
	1947	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
[95]	1948	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
	1949
	1950	if (btb_val)
[94]	1951	{
	1952	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
	1953	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	1954	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
	1955	}
[95]	1956	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
[94]	1957
[95]	1958	if (dir_val)
	1959	{
	1960	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
[94]	1961	if (_param->_have_port_history)
	1962	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
[95]	1963	}
	1964	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
	1965
	1966	if (ras_val)
[94]	1967	{
	1968	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	1969	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
	1970	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
	1971	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
	1972	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
	1973	}
	1974
[95]	1975	// -- it_upt;
[94]	1976	}
	1977
	1978	SC_START(1);
	1979	} while (not have_transaction);
	1980
	1981	upt.pop_back();
	1982	in_UPDATE_ACK [port]->write(0);
	1983	// if (_param->_have_port_depth)
	1984	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	1985	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	1986	}
[95]	1987	while (it_upt != it_event);
	1988
[94]	1989	}
[95]	1990
[94]	1991	{
	1992	LABEL("BRANCH_EVENT - have miss decod");
	1993
	1994	uint32_t port = context;
	1995
	1996	{
	1997	bool have_transaction = false;
	1998
	1999	do
	2000	{
	2001	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
	2002
	2003	SC_START(0);
	2004
	2005	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
	2006
	2007	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
	2008	{
	2009	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
	2010	have_transaction = true;
	2011
	2012	LABEL(" * event.address_src : %.8x,",event.address_src );
	2013	LABEL(" * event.address_good : %.8x,",event.address_good);
	2014	LABEL(" * event.take : %.8x,",event.take );
	2015
[98]	2016	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
[94]	2017	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
	2018	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
	2019	if (event.take_good)
	2020	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
	2021
	2022	event.address_src = 0;
	2023	event.take = 0;
	2024	event.address_dest = 0;
	2025	}
	2026
	2027	SC_START(1);
	2028	} while (not have_transaction);
	2029
	2030	in_BRANCH_EVENT_ACK [port]->write(0);
	2031	}
	2032	}
[95]	2033
[94]	2034	{
[95]	2035	LABEL("EVENT_STATE");
[94]	2036
[95]	2037	SC_START(1);
[97]	2038	in_EVENT_VAL [context]->write(1);
[105]	2039	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
[95]	2040
	2041	SC_START(1);
[97]	2042	in_EVENT_VAL [context]->write(0);
[95]	2043	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
	2044	}
	2045
	2046	{
	2047	LABEL("UPDATE - upt (before event)");
	2048
[94]	2049	uint32_t port = 0;
	2050
	2051	LABEL(" * port : %d",port);
[95]	2052	LABEL(" * size : %d",upt.size());
[94]	2053	std::list<request_t>::iterator it_upt = upt.begin();
	2054
	2055	for (uint32_t i=0; i<upt.size(); i++)
	2056	{
	2057	bool have_transaction = false;
	2058
	2059	do
	2060	{
	2061	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	2062
	2063	// if (_param->_have_port_depth)
	2064	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2065	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2066
	2067	SC_START(0);
	2068
	2069	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	2070
	2071	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	2072	{
	2073	LABEL("UPDATE [%d] - Transaction accepted",port);
	2074	have_transaction = true;
	2075
	2076	if (_param->_have_port_context_id)
	2077	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
	2078	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
	2079	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
	2080	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
	2081	if (update_btb(it_upt->condition))
	2082	{
	2083	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
	2084	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	2085	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
	2086	}
	2087	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
	2088
	2089	if (update_dir(it_upt->condition))
	2090	if (_param->_have_port_history)
	2091	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
	2092	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
	2093	if (update_ras(it_upt->condition))
	2094	{
	2095	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	2096	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
	2097	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
	2098	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
	2099	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
	2100	}
	2101
[95]	2102	++ it_upt;
[94]	2103	}
	2104
	2105	SC_START(1);
	2106	} while (not have_transaction);
	2107
	2108	in_UPDATE_ACK [port]->write(0);
	2109	// if (_param->_have_port_depth)
	2110	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2111	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2112	}
	2113	}
[95]	2114	upt.clear();
[94]	2115
	2116	// Wait Garbage Collector
	2117	{
[95]	2118	LABEL("GARBAGE COLLECTOR");
	2119	LABEL(" * upt bottom : %d",upt_bottom [context]);
	2120	LABEL(" * upt top : %d",upt_top [context]);
[94]	2121
[95]	2122	upt_top [context] = (upt_top_event [context]);
	2123	upt_bottom [context] = (upt_top [context]);
	2124
[94]	2125	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
	2126	(upt_top [context] != out_DEPTH_MAX [context]->read()))
[95]	2127	{
	2128	SC_START(1);
	2129	}
[94]	2130
	2131	}
	2132	}
[105]	2133
	2134	//---------------------------------------------------------------------
	2135	//---------------------------------------------------------------------
	2136	// COMMIT MISS : with RAS in UPFT and UPT
	2137	//---------------------------------------------------------------------
	2138	//---------------------------------------------------------------------
	2139	if (test5)
	2140	{
	2141	uint32_t context = rand() % _param->_nb_context;
	2142	uint32_t have_ufpt_ras = false;
	2143	uint32_t have_upt_ras = false;
	2144
	2145	{
	2146	LABEL("PREDICT - fill the queue");
	2147	uint32_t port = rand() % _param->_nb_inst_predict;
	2148
	2149	LABEL(" * context : %d",context);
	2150	LABEL(" * port : %d",port);
	2151
	2152	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	2153	{
	2154	request_t request;
	2155	request.context = context;
	2156	request.address_src = rand();
	2157	request.address_dest = rand();
	2158
	2159	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
	2160
	2161	request.take = 1;
	2162	request.take_good = 1;
	2163	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
	2164	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
	2165	request.is_accurate = true ;
	2166	request.miss_ifetch = false;
	2167	request.miss_decod = false;
	2168	request.miss_commit = false;
	2169	request.history = i;
	2170	request.ras_address = rand();
	2171	request.ras_index = rand()%_param->_size_ras_index[context];
	2172	request.ufpt_ptr = ufpt_top [context];
	2173	// request.upt_ptr;
	2174
	2175	bool have_transaction = false;
	2176	do
	2177	{
	2178	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
	2179	in_PREDICT_CONTEXT_ID [port]->write(request.context );
	2180	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
	2181	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	2182	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
	2183	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
	2184	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
	2185	in_PREDICT_DIR_HISTORY [port]->write(request.history );
	2186	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
	2187	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
	2188
	2189	if (_param->_have_port_depth)
	2190	{
	2191	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2192	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2193	}
	2194	SC_START(0); // fct melay
	2195
	2196	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
	2197	port,
	2198	in_PREDICT_VAL [port]->read(),
	2199	out_PREDICT_ACK [port]->read(),
	2200	in_PREDICT_BTB_IS_ACCURATE [port]->read());
	2201
	2202	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
	2203	{
	2204	LABEL("PREDICT [%d] - Transaction accepted",port);
	2205	have_transaction = true;
	2206
	2207	if (_param->_have_port_depth)
	2208	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
	2209
	2210	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
	2211	}
	2212
	2213	SC_START(1); // transition
	2214
	2215	} while (not have_transaction);
	2216
	2217	ufpt.push_back(request); // to update
	2218
	2219	in_PREDICT_VAL [port]->write(0);
	2220
	2221	if (_param->_have_port_depth)
	2222	{
	2223	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2224	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2225	}
	2226	}
	2227	}
	2228
	2229	{
	2230	LABEL("DECOD");
	2231	uint32_t port = rand() % _param->_nb_inst_decod;
	2232
	2233	LABEL(" * context : %d",context);
	2234	LABEL(" * port : %d",port);
	2235
	2236	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	2237	{
	2238	request_t request = ufpt.front();
	2239
	2240	bool have_transaction = false;
	2241	do
	2242	{
	2243	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
	2244	in_DECOD_CONTEXT_ID [port]->write(request.context );
	2245	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
	2246	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	2247	in_DECOD_BTB_CONDITION [port]->write(request.condition );
	2248	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
	2249	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
	2250	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
	2251	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
	2252	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
	2253	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
	2254	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
	2255
	2256	have_upt_ras \|= (update_ras(request.condition));
	2257
	2258	SC_START(0); // fct melay
	2259
	2260	LABEL("DECOD [%d] %d - %d",
	2261	port,
	2262	in_DECOD_VAL [port]->read(),
	2263	out_DECOD_ACK [port]->read());
	2264
	2265	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
	2266	{
	2267	LABEL("DECOD [%d] - Transaction accepted",port);
	2268	have_transaction = true;
	2269
	2270	request.upt_ptr = upt_top [context];
	2271	upt.push_back(request);
	2272	ufpt.pop_front();
	2273
	2274	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
	2275	}
	2276
	2277	SC_START(1); // transition
	2278
	2279	} while (not have_transaction);
	2280
	2281	in_DECOD_VAL [port]->write(0);
	2282
	2283	if (_param->_have_port_depth)
	2284	{
	2285	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2286	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2287	}
	2288	}
	2289	}
	2290
	2291	{
	2292	LABEL("PREDICT - fill the queue");
	2293	uint32_t port = rand() % _param->_nb_inst_predict;
	2294
	2295	LABEL(" * context : %d",context);
	2296	LABEL(" * port : %d",port);
	2297
	2298	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	2299	{
	2300	request_t request;
	2301	request.context = context;
	2302	request.address_src = rand();
	2303	request.address_dest = rand();
	2304	request.address_good = request.address_dest;
	2305	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
	2306
	2307	have_ufpt_ras \|= (update_ras(request.condition));
	2308
	2309	request.take = 1;
	2310	request.take_good = 1;
	2311	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
	2312	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
	2313	request.is_accurate = true ;
	2314	request.miss_ifetch = false;
	2315	request.miss_decod = false;
	2316	request.miss_commit = true;
	2317	request.history = i;
	2318	request.ras_address = rand();
	2319	request.ras_index = rand()%_param->_size_ras_index[context];
	2320	request.ufpt_ptr = ufpt_top [context];
	2321	// request.upt_ptr;
	2322
	2323	bool have_transaction = false;
	2324	do
	2325	{
	2326	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
	2327	in_PREDICT_CONTEXT_ID [port]->write(request.context );
	2328	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
	2329	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
	2330	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
	2331	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
	2332	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
	2333	in_PREDICT_DIR_HISTORY [port]->write(request.history );
	2334	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
	2335	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
	2336
	2337	if (_param->_have_port_depth)
	2338	{
	2339	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2340	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2341	}
	2342	SC_START(0); // fct melay
	2343
	2344	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
	2345	port,
	2346	in_PREDICT_VAL [port]->read(),
	2347	out_PREDICT_ACK [port]->read(),
	2348	in_PREDICT_BTB_IS_ACCURATE [port]->read());
	2349
	2350	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
	2351	{
	2352	LABEL("PREDICT [%d] - Transaction accepted",port);
	2353	have_transaction = true;
	2354
	2355	if (_param->_have_port_depth)
	2356	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
	2357
	2358	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
	2359	}
	2360
	2361	SC_START(1); // transition
	2362
	2363	} while (not have_transaction);
	2364
	2365	ufpt.push_back(request); // to update
	2366
	2367	in_PREDICT_VAL [port]->write(0);
	2368
	2369	if (_param->_have_port_depth)
	2370	{
	2371	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2372	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2373	}
	2374	}
	2375	}
	2376
	2377	uint32_t nb_branch_before_event = 0;
	2378	{
	2379	// middle
	2380	std::list<request_t>::iterator it_event = upt.begin();
	2381	for (uint32_t i=0; i < (upt.size()>>1); ++i)
	2382	{
	2383	nb_branch_before_event ++;
	2384	it_event ++;
	2385	}
	2386	for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it)
	2387	it->miss_commit = true;
	2388
	2389	bool have_transaction = false;
	2390
	2391	do
	2392	{
	2393	PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event);
	2394	PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION);
	2395	PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr);
	2396
	2397	SC_START(0);
	2398
	2399	if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context]))
	2400	{
	2401	LABEL("EVENT [%d] - Transaction accepted",context);
	2402
	2403	have_transaction = true;
	2404	}
	2405
	2406	SC_START(1);
	2407	}
	2408	while (not have_transaction);
	2409	PORT_WRITE(in_EVENT_VAL [context],0);
	2410
	2411	upt_top_event [it_event->context] = upt_top [it_event->context];
	2412	upt_top [it_event->context] = it_event->upt_ptr;
	2413	}
	2414
	2415	{
	2416	LABEL("BRANCH_COMPLETE - Hit ifetch");
	2417
	2418	uint32_t port = rand() % _param->_nb_inst_branch_complete;
	2419
	2420	LABEL(" * port : %d",port);
	2421
	2422	std::list<request_t>::iterator it_upt = upt.begin();
	2423
	2424	for (uint32_t i=0; i<nb_branch_before_event; ++i)
	2425	{
	2426	bool have_transaction = false;
	2427
	2428	do
	2429	{
	2430	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
	2431	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
	2432	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
	2433	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
	2434	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
	2435
	2436	if (_param->_have_port_depth)
	2437	{
	2438	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2439	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2440	}
	2441	SC_START(0);
	2442
	2443	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
	2444
	2445	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
	2446	{
	2447	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
	2448	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
	2449	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
	2450	LABEL(" * CONDITION : %d" ,it_upt->condition );
	2451	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
	2452	LABEL(" * FLAG : %d" ,it_upt->flag );
	2453	LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence );
	2454
	2455	have_transaction = true;
	2456
	2457	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
	2458	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
	2459	it_upt->take_good = it_upt->take;
	2460	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
	2461	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	2462
	2463	it_upt++;
	2464	}
	2465
	2466	SC_START(1);
	2467
	2468	} while (not have_transaction);
	2469
	2470	in_BRANCH_COMPLETE_VAL [port]->write(0);
	2471
	2472	if (_param->_have_port_depth)
	2473	{
	2474	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2475	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2476	}
	2477	}
	2478	}
	2479
	2480	if (have_ufpt_ras)
	2481	{
	2482	LABEL("UPDATE - Update UPFT");
	2483
	2484	uint32_t port = 0;
	2485
	2486	LABEL(" * port : %d",port);
	2487	std::list<request_t>::iterator it_ufpt = ufpt.end();
	2488	-- it_ufpt;
	2489
	2490	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
	2491	{
	2492	bool have_transaction = false;
	2493
	2494	do
	2495	{
	2496	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	2497
	2498	// if (_param->_have_port_depth)
	2499	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
	2500	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
	2501
	2502	SC_START(0);
	2503
	2504	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	2505
	2506	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	2507	{
	2508	LABEL("UPDATE [%d] - Transaction accepted",port);
	2509	have_transaction = true;
	2510
	2511	if (_param->_have_port_context_id)
	2512	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
	2513	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
	2514	it_ufpt->miss_decod or
	2515	it_ufpt->miss_commit ));
	2516	// if (update_btb(it_ufpt->condition) or
	2517	// update_dir(it_ufpt->condition))
	2518	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
	2519	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
	2520	// if (update_btb(it_ufpt->condition))
	2521	// {
	2522	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
	2523	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
	2524	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
	2525	// }
	2526	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
	2527
	2528	// if (update_dir(it_ufpt->condition))
	2529	// if (_param->_have_port_history)
	2530	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
	2531	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
	2532	if (update_ras(it_ufpt->condition))
	2533	{
	2534	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	2535	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
	2536	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
	2537	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
	2538	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
	2539	}
	2540	}
	2541
	2542	SC_START(1);
	2543	} while (not have_transaction);
	2544
	2545	-- it_ufpt;
	2546
	2547
	2548	in_UPDATE_ACK [port]->write(0);
	2549	// if (_param->_have_port_depth)
	2550	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
	2551	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
	2552	}
	2553	}
	2554	ufpt.clear();
	2555
	2556	{
	2557	LABEL("UPDATE - upt (after event)");
	2558
	2559	uint32_t port = 0;
	2560
	2561	LABEL(" * port : %d",port);
	2562
	2563	std::list<request_t>::iterator it_upt = upt.end();
	2564
	2565	// for (uint32_t i=0; i<upt.size(); i++)
	2566
	2567	uint32_t size = upt.size();
	2568
	2569	LABEL(" * size : %d",size);
	2570	LABEL(" * nb_branch_before_event : %d",nb_branch_before_event);
	2571
	2572	for (uint32_t i=nb_branch_before_event; i<size; ++i)
	2573	{
	2574	--it_upt;
	2575
	2576	bool have_transaction = false;
	2577
	2578	if (need_update(it_upt->condition))
	2579	do
	2580	{
	2581	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	2582
	2583	// if (_param->_have_port_depth)
	2584	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2585	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2586
	2587	SC_START(0);
	2588
	2589	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	2590
	2591	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	2592	{
	2593	LABEL("UPDATE [%d] - Transaction accepted",port);
	2594	LABEL(" * address_src : %.8x",it_upt->address_src);
	2595	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
	2596
	2597	have_transaction = true;
	2598
	2599	bool btb_val = ((update_btb(it_upt->condition)));
	2600	bool dir_val = (update_dir(it_upt->condition) and
	2601	not (it_upt->miss_ifetch or it_upt->miss_decod));
	2602	bool ras_val = update_ras(it_upt->condition);
	2603
	2604	if (_param->_have_port_context_id)
	2605	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
	2606	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
	2607	// TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
	2608
	2609	// if (btb_val)
	2610	// {
	2611	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
	2612	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	2613	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
	2614	// }
	2615	// TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
	2616
	2617	// if (dir_val)
	2618	// {
	2619	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
	2620	// if (_param->_have_port_history)
	2621	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
	2622	// }
	2623	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
	2624
	2625	if (ras_val)
	2626	{
	2627	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	2628	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
	2629	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
	2630	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
	2631	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
	2632	}
	2633	// -- it_upt;
	2634	}
	2635
	2636	SC_START(1);
	2637	} while (not have_transaction);
	2638
	2639	upt.pop_back();
	2640	in_UPDATE_ACK [port]->write(0);
	2641	// if (_param->_have_port_depth)
	2642	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2643	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2644	}
	2645	}
	2646
	2647	/*
	2648	{
	2649	LABEL("BRANCH_EVENT - have miss decod");
	2650
	2651	uint32_t port = context;
	2652
	2653	{
	2654	bool have_transaction = false;
	2655
	2656	do
	2657	{
	2658	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
	2659
	2660	SC_START(0);
	2661
	2662	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
	2663
	2664	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
	2665	{
	2666	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
	2667	have_transaction = true;
	2668
	2669	LABEL(" * event.address_src : %.8x,",event.address_src );
	2670	LABEL(" * event.address_good : %.8x,",event.address_good);
	2671	LABEL(" * event.take : %.8x,",event.take );
	2672
	2673	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
	2674	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
	2675	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
	2676	if (event.take_good)
	2677	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
	2678
	2679	event.address_src = 0;
	2680	event.take = 0;
	2681	event.address_dest = 0;
	2682	}
	2683
	2684	SC_START(1);
	2685	} while (not have_transaction);
	2686
	2687	in_BRANCH_EVENT_ACK [port]->write(0);
	2688	}
	2689	}
	2690
	2691	{
	2692	LABEL("EVENT_STATE");
	2693
	2694	SC_START(1);
	2695	in_EVENT_VAL [context]->write(1);
	2696	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
	2697
	2698	SC_START(1);
	2699	in_EVENT_VAL [context]->write(0);
	2700	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
	2701	}
	2702	*/
	2703
	2704	{
	2705	LABEL("UPDATE - upt (before event)");
	2706
	2707	uint32_t port = 0;
	2708
	2709	LABEL(" * port : %d",port);
	2710	LABEL(" * size : %d",upt.size());
	2711	std::list<request_t>::iterator it_upt = upt.begin();
	2712
	2713	for (uint32_t i=0; i<upt.size(); i++)
	2714	{
	2715	bool have_transaction = false;
	2716
	2717	do
	2718	{
	2719	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
	2720
	2721	// if (_param->_have_port_depth)
	2722	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2723	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2724
	2725	SC_START(0);
	2726
	2727	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
	2728
	2729	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
	2730	{
	2731	LABEL("UPDATE [%d] - Transaction accepted",port);
	2732	have_transaction = true;
	2733
	2734	if (_param->_have_port_context_id)
	2735	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
	2736	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
	2737	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
	2738	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
	2739	if (update_btb(it_upt->condition))
	2740	{
	2741	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
	2742	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
	2743	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
	2744	}
	2745	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
	2746
	2747	if (update_dir(it_upt->condition))
	2748	if (_param->_have_port_history)
	2749	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
	2750	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
	2751	if (update_ras(it_upt->condition))
	2752	{
	2753	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
	2754	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
	2755	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
	2756	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
	2757	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
	2758	}
	2759
	2760	++ it_upt;
	2761	}
	2762
	2763	SC_START(1);
	2764	} while (not have_transaction);
	2765
	2766	in_UPDATE_ACK [port]->write(0);
	2767	// if (_param->_have_port_depth)
	2768	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
	2769	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
	2770	}
	2771	}
	2772
	2773	upt.clear();
	2774
	2775	// Wait Garbage Collector
	2776	{
	2777	LABEL("GARBAGE COLLECTOR");
	2778	LABEL(" * upt bottom : %d",upt_bottom [context]);
	2779	LABEL(" * upt top : %d",upt_top [context]);
	2780
	2781	upt_top [context] = (upt_top_event [context]);
	2782	upt_bottom [context] = (upt_top [context]);
	2783
	2784	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
	2785	(upt_top [context] != out_DEPTH_MAX [context]->read()))
	2786	{
	2787	SC_START(1);
	2788	}
	2789	}
	2790	}
[94]	2791
[88]	2792	}// ITERATION
[81]	2793
[78]	2794	/********************************************************
	2795	* Simulation - End
	2796	********************************************************/
	2797
	2798	TEST_OK ("End of Simulation");
	2799	delete _time;
	2800
	2801	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
	2802
	2803	delete in_CLOCK;
	2804	delete in_NRESET;
[81]	2805
	2806	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	2807	delete [] in_PREDICT_VAL ;
	2808	delete [] out_PREDICT_ACK ;
	2809	delete [] in_PREDICT_CONTEXT_ID ;
	2810	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
	2811	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
	2812	delete [] in_PREDICT_BTB_CONDITION ;
	2813	delete [] in_PREDICT_BTB_LAST_TAKE ;
	2814	delete [] in_PREDICT_BTB_IS_ACCURATE ;
	2815	delete [] in_PREDICT_DIR_HISTORY ;
	2816	delete [] in_PREDICT_RAS_ADDRESS ;
	2817	delete [] in_PREDICT_RAS_INDEX ;
[88]	2818	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
[81]	2819
	2820	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	2821	delete [] in_DECOD_VAL ;
	2822	delete [] out_DECOD_ACK ;
	2823	delete [] in_DECOD_CONTEXT_ID ;
	2824	delete [] in_DECOD_BTB_ADDRESS_SRC ;
	2825	delete [] in_DECOD_BTB_ADDRESS_DEST ;
	2826	delete [] in_DECOD_BTB_CONDITION ;
	2827	delete [] in_DECOD_BTB_LAST_TAKE ;
	2828	delete [] in_DECOD_RAS_ADDRESS ;
	2829	delete [] in_DECOD_RAS_INDEX ;
[82]	2830	delete [] in_DECOD_MISS_IFETCH ;
	2831	delete [] in_DECOD_MISS_DECOD ;
[81]	2832	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
	2833	//delete [] out_DECOD_DEPTH ;
[88]	2834	delete [] in_DECOD_IS_ACCURATE ;
[81]	2835
	2836	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	2837	delete [] in_BRANCH_COMPLETE_VAL ;
	2838	delete [] out_BRANCH_COMPLETE_ACK ;
	2839	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
	2840	delete [] in_BRANCH_COMPLETE_DEPTH ;
	2841	delete [] in_BRANCH_COMPLETE_ADDRESS ;
[98]	2842	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
[81]	2843	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
	2844	delete [] out_BRANCH_COMPLETE_TAKE ;
	2845	delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
	2846	delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
[82]	2847
	2848	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	2849	delete [] out_BRANCH_EVENT_VAL ;
	2850	delete [] in_BRANCH_EVENT_ACK ;
[98]	2851	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
	2852	delete [] out_BRANCH_EVENT_DEPTH ;
[95]	2853	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
[82]	2854	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
[94]	2855	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
[82]	2856	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
[81]	2857
	2858	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	2859	delete [] out_UPDATE_VAL ;
	2860	delete [] in_UPDATE_ACK ;
	2861	delete [] out_UPDATE_CONTEXT_ID ;
	2862	delete [] out_UPDATE_MISS_PREDICTION ;
	2863	delete [] out_UPDATE_DIRECTION_GOOD ;
	2864	delete [] out_UPDATE_BTB_VAL ;
	2865	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
	2866	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
	2867	delete [] out_UPDATE_BTB_CONDITION ;
	2868	delete [] out_UPDATE_DIR_VAL ;
	2869	delete [] out_UPDATE_DIR_HISTORY ;
	2870	delete [] out_UPDATE_RAS_VAL ;
[94]	2871	delete [] out_UPDATE_RAS_FLUSH ;
[82]	2872	delete [] out_UPDATE_RAS_PUSH ;
[81]	2873	delete [] out_UPDATE_RAS_ADDRESS ;
	2874	delete [] out_UPDATE_RAS_INDEX ;
	2875	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
	2876
[97]	2877	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
	2878	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
[95]	2879	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
	2880	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
	2881
[81]	2882	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[101]	2883	delete [] out_DEPTH_VAL;
[88]	2884	delete [] out_DEPTH_CURRENT;
	2885	delete [] out_DEPTH_MIN;
	2886	delete [] out_DEPTH_MAX;
[101]	2887	delete [] out_DEPTH_FULL;
[81]	2888
[78]	2889	#endif
	2890
	2891	delete _Update_Prediction_Table;
	2892	#ifdef STATISTICS
	2893	delete _parameters_statistics;
	2894	#endif
	2895	}

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