[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_transition.cpp 145 2010-10-13 18:15:51Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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[110] | 10 | #include "Behavioural/include/Simulation.h" |
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[88] | 11 | |
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| 12 | namespace morpheo { |
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| 13 | namespace behavioural { |
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| 14 | namespace core { |
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| 15 | namespace multi_ooo_engine { |
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| 16 | namespace ooo_engine { |
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| 17 | namespace commit_unit { |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::transition" |
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| 21 | void Commit_unit::transition (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[100] | 28 | // Clear all bank |
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[115] | 29 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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[88] | 30 | { |
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[115] | 31 | while(not _rob[i].empty()) |
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| 32 | { |
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| 33 | delete _rob[i].front(); |
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| 34 | _rob[i].pop_front(); |
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| 35 | } |
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[88] | 36 | reg_BANK_PTR [i] = 0; |
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| 37 | } |
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| 38 | |
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[100] | 39 | // Reset pointer |
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[88] | 40 | reg_NUM_BANK_HEAD = 0; |
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| 41 | reg_NUM_BANK_TAIL = 0; |
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[122] | 42 | reg_NUM_PTR_TAIL = 0; |
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[88] | 43 | |
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[100] | 44 | // Reset counter |
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[88] | 45 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 46 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 47 | { |
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[109] | 48 | _nb_cycle_idle [i][j] = 0; |
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| 49 | |
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[122] | 50 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 51 | // reg_EVENT_FLUSH [i][j] = false; |
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[123] | 52 | // reg_EVENT_STOP [i][j] = false; |
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[139] | 53 | // reg_EVENT_NUM_BANK [i][j] = 0; // not necessary |
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| 54 | // reg_EVENT_NUM_PTR [i][j] = 0; // not necessary |
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| 55 | // reg_EVENT_CAN_RESTART [i][j] = 0; // not necessary |
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[128] | 56 | reg_EVENT_PACKET [i][j] = 0; // not necessary |
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[139] | 57 | reg_EVENT_DEPTH [i][j] = 0; // not necessary |
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[124] | 58 | reg_EVENT_NB_INST [i][j] = 0; |
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[122] | 59 | reg_EVENT_LAST [i][j] = false; |
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[128] | 60 | reg_EVENT_LAST_NUM_BANK [i][j] = 0; // not necessary |
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| 61 | reg_EVENT_LAST_NUM_PTR [i][j] = 0; // not necessary |
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[100] | 62 | |
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[123] | 63 | reg_EVENT_NEXT_STOP [i][j] = false; |
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[128] | 64 | reg_EVENT_NEXT_PACKET [i][j] = 0; // not necessary |
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[123] | 65 | |
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[104] | 66 | // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; |
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| 67 | reg_PC_CURRENT [i][j] = (0x100 )>>2; |
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| 68 | reg_PC_CURRENT_IS_DS [i][j] = 0; |
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| 69 | reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; |
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[105] | 70 | reg_PC_NEXT [i][j] = (0x100+4)>>2; |
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[145] | 71 | |
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| 72 | reg_NB_INST_COMMIT_ALL [i][j] = 0; |
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| 73 | reg_NB_INST_COMMIT_MEM [i][j] = 0; |
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| 74 | |
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| 75 | if (_param->_front_end_rat_scheme[i] == RAT_DEPTH_SAVE) |
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| 76 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 77 | reg_NB_INST_DEPTH [i][j][k] = 0; |
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[88] | 78 | } |
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| 79 | |
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[139] | 80 | // Resert RAT_UPDATE_TABLE |
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| 81 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 82 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 83 | { |
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| 84 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
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| 85 | rat_gpr_update_table [i][j][k] = false; // not necessary |
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| 86 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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| 87 | rat_spr_update_table [i][j][k] = false; // not necessary |
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| 88 | } |
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| 89 | |
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[100] | 90 | // Reset priority algorithm |
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[88] | 91 | _priority_insert->reset(); |
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| 92 | } |
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| 93 | else |
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| 94 | { |
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[141] | 95 | #ifdef STATISTICS |
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| 96 | uint32_t stat_nb_inst_insert [_param->_nb_rename_unit]; |
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| 97 | uint32_t stat_nb_inst_retire [_param->_nb_rename_unit]; |
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| 98 | uint32_t stat_nb_inst_commit [_param->_nb_rename_unit]; |
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| 99 | |
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| 100 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 101 | for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) |
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| 102 | { |
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| 103 | stat_nb_inst_insert [i] = 0; |
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| 104 | stat_nb_inst_retire [i] = 0; |
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| 105 | stat_nb_inst_commit [i] = 0; |
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| 106 | } |
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| 107 | #endif |
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| 108 | |
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[109] | 109 | // Increase number idle cycle |
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| 110 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 111 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 112 | _nb_cycle_idle [i][j] ++; |
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| 113 | |
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[100] | 114 | // Compute next priority |
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[88] | 115 | _priority_insert->transition(); |
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| 116 | |
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| 117 | // =================================================================== |
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[100] | 118 | // =====[ GARBAGE COLLECTOR ]========================================= |
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| 119 | // =================================================================== |
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| 120 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 121 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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[122] | 122 | { |
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| 123 | // Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty) |
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| 124 | // * no previous can_restart (trap for one) |
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| 125 | // * and decod_queue is empty |
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| 126 | // * and have an event or have a futur event |
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[123] | 127 | // if (not reg_EVENT_CAN_RESTART [i][j] and |
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| 128 | // (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and |
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| 129 | // (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT))) |
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| 130 | // reg_EVENT_CAN_RESTART [i][j] = true; |
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[122] | 131 | |
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| 132 | // Test event state |
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| 133 | switch (reg_EVENT_STATE [i][j]) |
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[104] | 134 | { |
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[122] | 135 | case COMMIT_EVENT_STATE_EVENT : |
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| 136 | { |
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| 137 | // Have an event, test if all composant have ack |
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| 138 | if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) |
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| 139 | { |
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| 140 | // A minor optimisation : test if wait_decod is previously empty. |
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[123] | 141 | // if (not reg_EVENT_CAN_RESTART [i][j]) |
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| 142 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD; |
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| 143 | // else |
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[122] | 144 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; |
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[139] | 145 | |
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| 146 | // Reset update_table |
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| 147 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
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| 148 | rat_gpr_update_table [i][j][k] = false; |
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| 149 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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| 150 | rat_spr_update_table [i][j][k] = false; |
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[122] | 151 | } |
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| 152 | |
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| 153 | break; |
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| 154 | } |
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[123] | 155 | // case COMMIT_EVENT_STATE_WAIT_DECOD : |
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| 156 | // { |
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| 157 | // // Wait flush of decod_queue. |
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| 158 | // // Test if can restart now |
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| 159 | // if (reg_EVENT_CAN_RESTART [i][j]) |
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| 160 | // { |
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| 161 | // //reg_EVENT_FLUSH [i][j] = false; |
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[122] | 162 | |
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[123] | 163 | // // A minor optimisation : test if the last element is already retire |
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| 164 | // if (not reg_EVENT_LAST [i][j]) |
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| 165 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; |
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| 166 | // else |
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| 167 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END; |
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| 168 | // } |
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| 169 | // break; |
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| 170 | // } |
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[124] | 171 | |
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| 172 | // case COMMIT_EVENT_STATE_WAIT_END : |
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| 173 | // { |
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| 174 | // // Wait the flush of Re Order Buffer. |
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| 175 | // // Test if the last element is retire |
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| 176 | // if (reg_EVENT_LAST [i][j]) |
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| 177 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ; |
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| 178 | |
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| 179 | // break; |
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| 180 | // } |
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| 181 | // case COMMIT_EVENT_STATE_END : |
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| 182 | // { |
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| 183 | // // Just one cycle |
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| 184 | |
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| 185 | // // flush of re order buffer is finish |
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| 186 | // reg_EVENT_LAST [i][j] = false; |
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| 187 | |
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| 188 | // if (not reg_EVENT_NEXT_STOP [i][j]) |
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| 189 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 190 | // else |
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| 191 | // { |
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| 192 | // reg_EVENT_NEXT_STOP [i][j] = false; |
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| 193 | // reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j]; |
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| 194 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
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| 195 | // // reg_EVENT_STOP [i][j] = true; |
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| 196 | // reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
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| 197 | // reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL; |
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| 198 | // } |
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| 199 | |
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| 200 | // break; |
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| 201 | // } |
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| 202 | |
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| 203 | |
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[122] | 204 | case COMMIT_EVENT_STATE_WAIT_END : |
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| 205 | { |
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| 206 | // Wait the flush of Re Order Buffer. |
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| 207 | // Test if the last element is retire |
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| 208 | if (reg_EVENT_LAST [i][j]) |
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[124] | 209 | { |
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| 210 | // flush of re order buffer is finish |
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| 211 | reg_EVENT_LAST [i][j] = false; |
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| 212 | |
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| 213 | if (not reg_EVENT_NEXT_STOP [i][j]) |
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| 214 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 215 | else |
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| 216 | { |
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[139] | 217 | uint32_t next_packet = reg_EVENT_NEXT_PACKET [i][j]; |
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| 218 | |
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[124] | 219 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
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[123] | 220 | |
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[124] | 221 | reg_EVENT_NEXT_STOP [i][j] = false; |
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[139] | 222 | reg_EVENT_PACKET [i][j] = next_packet; |
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| 223 | // reg_EVENT_DEPTH [i][j] = _rob[next_packet].depth; |
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[124] | 224 | reg_EVENT_NB_INST [i][j] = reg_NB_INST_COMMIT_ALL [i][j]; |
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| 225 | //reg_EVENT_STOP [i][j] = true; |
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| 226 | reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
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| 227 | reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL; |
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| 228 | } |
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[123] | 229 | } |
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[122] | 230 | break; |
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| 231 | } |
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[124] | 232 | |
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[122] | 233 | //case COMMIT_EVENT_STATE_NO_EVENT : |
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[123] | 234 | //case COMMIT_EVENT_STATE_NOT_YET_EVENT : |
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[122] | 235 | default : break; |
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[104] | 236 | } |
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[122] | 237 | } |
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[100] | 238 | |
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| 239 | // =================================================================== |
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[88] | 240 | // =====[ INSERT ]==================================================== |
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| 241 | // =================================================================== |
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[122] | 242 | { |
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[124] | 243 | // for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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| 244 | // for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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| 245 | // log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL [%d][%d] : %d",i,j,PORT_READ(in_INSERT_VAL [i][j])); |
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| 246 | |
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[122] | 247 | // variable to count instruction insert |
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| 248 | uint32_t nb_insert = 0; |
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[124] | 249 | |
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[122] | 250 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 251 | { |
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| 252 | // compute first bank number |
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| 253 | uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; |
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| 254 | |
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| 255 | if (internal_BANK_INSERT_VAL [num_bank]) |
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| 256 | { |
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| 257 | // get rename unit source and instruction. |
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| 258 | uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank]; |
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| 259 | uint32_t y = internal_BANK_INSERT_NUM_INST [num_bank]; |
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| 260 | |
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| 261 | // Test if an instruction is valid |
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| 262 | // (all in_order insert combinatory is in rename_unit ) |
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| 263 | if (PORT_READ(in_INSERT_VAL [x][y])) |
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| 264 | { |
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| 265 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); |
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| 266 | |
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| 267 | // get information |
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| 268 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; |
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| 269 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; |
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| 270 | Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); |
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| 271 | Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); |
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| 272 | bool is_store = is_operation_memory_store(operation); |
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| 273 | |
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| 274 | Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); |
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| 275 | Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); |
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| 276 | |
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| 277 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 278 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
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| 279 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
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| 280 | log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); |
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| 281 | log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); |
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| 282 | |
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| 283 | // Create new entry and write information |
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| 284 | entry_t * entry = new entry_t; |
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| 285 | uint32_t ptr = reg_BANK_PTR [num_bank]; |
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[88] | 286 | |
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[145] | 287 | // entry->restore = false; |
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[122] | 288 | entry->ptr = ptr; |
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| 289 | entry->front_end_id = front_end_id; |
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| 290 | entry->context_id = context_id ; |
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| 291 | entry->rename_unit_id = x; |
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| 292 | entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; |
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[137] | 293 | #ifdef STATISTICS |
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| 294 | entry->instruction = PORT_READ(in_INSERT_INSTRUCTION [x][y]); |
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| 295 | #endif |
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[122] | 296 | entry->type = type; |
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| 297 | entry->operation = operation; |
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| 298 | entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); |
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| 299 | // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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| 300 | entry->exception = exception; |
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| 301 | entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); |
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| 302 | entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute); |
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| 303 | entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute); |
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| 304 | entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); |
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| 305 | entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; |
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| 306 | #ifdef DEBUG |
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| 307 | entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); |
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| 308 | entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); |
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| 309 | entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); |
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[137] | 310 | #endif |
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[122] | 311 | entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); |
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[137] | 312 | #ifdef DEBUG |
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[122] | 313 | entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); |
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| 314 | entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); |
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| 315 | entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); |
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| 316 | entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); |
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| 317 | entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); |
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| 318 | #endif |
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| 319 | entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); |
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| 320 | entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); |
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| 321 | entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); |
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| 322 | entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); |
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| 323 | entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); |
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| 324 | entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); |
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| 325 | entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); |
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| 326 | entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); |
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[128] | 327 | |
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| 328 | entry->flags = 0; // not necessary |
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[122] | 329 | entry->no_sequence = type == TYPE_BRANCH; |
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[124] | 330 | // entry->speculative = true; |
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[122] | 331 | #ifdef DEBUG |
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| 332 | entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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| 333 | #endif |
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| 334 | entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); |
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| 335 | #ifdef DEBUG |
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| 336 | entry->cycle_rob_in = simulation_cycle(); |
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| 337 | entry->cycle_commit = simulation_cycle(); |
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| 338 | #endif |
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| 339 | |
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| 340 | // Test if exception : |
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| 341 | // * yes : no execute instruction, wait ROB Head |
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| 342 | // * no : test if no_execute (== instruction is flushed) |
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| 343 | // else test type |
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| 344 | // * BRANCH : l.j -> branch is ended |
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| 345 | // other -> wait the execution end of branchment |
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| 346 | // * MEMORY : store -> wait store is at head of ROB |
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| 347 | // other -> wait end of instruction |
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| 348 | // * OTHER |
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| 349 | |
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| 350 | { |
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| 351 | if (exception == EXCEPTION_NONE) |
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| 352 | { |
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| 353 | // no_execute : l.j, l.nop, l.rfe |
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| 354 | |
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| 355 | log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); |
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| 356 | |
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| 357 | switch (type) |
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| 358 | { |
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| 359 | case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} |
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[145] | 360 | case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;} |
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[122] | 361 | default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} |
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| 362 | } |
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| 363 | } |
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| 364 | else |
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| 365 | { |
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| 366 | // Have an exception : wait head of ROB |
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| 367 | // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap |
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| 368 | |
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| 369 | entry->state = ROB_END_EXCEPTION_WAIT_HEAD; |
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| 370 | } |
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| 371 | } |
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[100] | 372 | |
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[122] | 373 | #ifdef STATISTICS |
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| 374 | if (usage_is_set(_usage,USE_STATISTICS)) |
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[141] | 375 | stat_nb_inst_insert [x] ++; |
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[121] | 376 | #endif |
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[122] | 377 | |
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| 378 | // Push entry in rob |
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| 379 | _rob[num_bank].push_back(entry); |
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| 380 | |
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| 381 | // Update counter and pointer |
---|
| 382 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; |
---|
| 383 | if (type == TYPE_MEMORY) |
---|
| 384 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; |
---|
[88] | 385 | |
---|
[145] | 386 | if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE) |
---|
| 387 | reg_NB_INST_DEPTH [front_end_id][context_id][entry->depth] ++; |
---|
| 388 | |
---|
[122] | 389 | // flush = present event or future event. |
---|
| 390 | // * present event = don't can restart |
---|
[88] | 391 | |
---|
[122] | 392 | // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
---|
[88] | 393 | |
---|
[122] | 394 | // bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
| 395 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or |
---|
| 396 | // (reg_EVENT_STOP [front_end_id][context_id])); |
---|
| 397 | |
---|
| 398 | // New instruction from decod_queue. Flush if : |
---|
| 399 | // * future event (instruction don't need execute because they are a previous event (miss load/branch or exception)) |
---|
| 400 | // * or present_event |
---|
| 401 | // * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured. |
---|
[123] | 402 | // bool flush = ((// present event |
---|
| 403 | // ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
| 404 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) |
---|
| 405 | // ) or |
---|
| 406 | // futur event |
---|
| 407 | // reg_EVENT_STOP [front_end_id][context_id]) |
---|
| 408 | // // can't restart |
---|
| 409 | // and not reg_EVENT_CAN_RESTART[front_end_id][context_id] |
---|
| 410 | // ); |
---|
[100] | 411 | |
---|
[123] | 412 | // if (flush) |
---|
| 413 | // { |
---|
| 414 | // // A new invalid instruction is push in rob -> new last instruction |
---|
| 415 | // reg_EVENT_LAST [front_end_id][context_id] = false; |
---|
| 416 | // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank; |
---|
| 417 | // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr; |
---|
| 418 | // } |
---|
[122] | 419 | |
---|
| 420 | // Update pointer |
---|
| 421 | reg_NUM_PTR_TAIL = ptr; |
---|
| 422 | reg_BANK_PTR [num_bank] = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank; |
---|
| 423 | nb_insert ++; |
---|
[108] | 424 | } |
---|
[122] | 425 | } |
---|
| 426 | } |
---|
| 427 | // Update pointer |
---|
| 428 | reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank; |
---|
| 429 | } |
---|
[88] | 430 | |
---|
| 431 | // =================================================================== |
---|
| 432 | // =====[ COMMIT ]==================================================== |
---|
| 433 | // =================================================================== |
---|
| 434 | |
---|
| 435 | #ifdef STATISTICS |
---|
| 436 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 437 | (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; |
---|
| 438 | #endif |
---|
| 439 | |
---|
[122] | 440 | // For each commit instruction ... |
---|
[88] | 441 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 442 | for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) |
---|
[122] | 443 | // ... test if an instruction have finish this execution |
---|
[88] | 444 | if (internal_BANK_COMMIT_VAL [i][j]) |
---|
| 445 | { |
---|
[122] | 446 | // An instruction is executed -> Change state of this instruction |
---|
[100] | 447 | |
---|
[122] | 448 | // Get information |
---|
[88] | 449 | uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; |
---|
| 450 | |
---|
[122] | 451 | // Test if instruction is valid and is enable |
---|
| 452 | // (can be disable if this instruction is reexecute) |
---|
[88] | 453 | if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) |
---|
| 454 | { |
---|
| 455 | log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); |
---|
[141] | 456 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); |
---|
[88] | 457 | |
---|
[141] | 458 | // find the good entry !!! |
---|
| 459 | entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; |
---|
| 460 | |
---|
[88] | 461 | #ifdef STATISTICS |
---|
| 462 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
[141] | 463 | stat_nb_inst_commit [entry->rename_unit_id] ++; |
---|
[88] | 464 | #endif |
---|
| 465 | |
---|
[124] | 466 | log_printf(TRACE,Commit_unit,FUNCTION," * ptr : %d",entry->ptr); |
---|
[100] | 467 | |
---|
| 468 | //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); |
---|
[122] | 469 | Ttype_t type = entry->type; |
---|
| 470 | Tcontrol_t no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); |
---|
[136] | 471 | // Tcontrol_t cancel = PORT_READ(in_COMMIT_CANCEL [x]); |
---|
[122] | 472 | |
---|
| 473 | #if 0 |
---|
| 474 | if ((type == TYPE_MEMORY) and no_sequence) |
---|
| 475 | continue; |
---|
| 476 | #endif |
---|
| 477 | |
---|
[100] | 478 | Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); |
---|
[88] | 479 | |
---|
[100] | 480 | rob_state_t state = entry->state; |
---|
| 481 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 482 | Tcontext_t context_id = entry->context_id; |
---|
[88] | 483 | |
---|
[100] | 484 | // change state : test exception_use |
---|
[88] | 485 | |
---|
[100] | 486 | bool have_exception = false; |
---|
| 487 | bool have_miss_speculation = false; |
---|
| 488 | |
---|
[122] | 489 | // Test if have an exception ... |
---|
[88] | 490 | if (exception != EXCEPTION_NONE) |
---|
[100] | 491 | { |
---|
[122] | 492 | // Test if the instruction is a load and is a miss speculation |
---|
| 493 | // (load is commit, but they have an dependence with a previous store -> need restart pipeline) |
---|
| 494 | |
---|
[100] | 495 | have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
[88] | 496 | |
---|
[122] | 497 | // * Test if the exception generated can be trap by this exception |
---|
[100] | 498 | switch (entry->exception_use) |
---|
| 499 | { |
---|
| 500 | // Have overflow exception if bit overflow enable is set. |
---|
| 501 | case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} |
---|
| 502 | case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
---|
| 503 | (exception == EXCEPTION_DATA_TLB ) or |
---|
| 504 | (exception == EXCEPTION_DATA_PAGE) or |
---|
| 505 | (exception == EXCEPTION_ALIGNMENT)); break;}; |
---|
| 506 | case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
---|
| 507 | (exception == EXCEPTION_DATA_TLB ) or |
---|
| 508 | (exception == EXCEPTION_DATA_PAGE)); break;}; |
---|
| 509 | case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; |
---|
| 510 | case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; |
---|
| 511 | case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; |
---|
| 512 | case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; |
---|
| 513 | case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; |
---|
| 514 | case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; |
---|
| 515 | case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; |
---|
| 516 | // Case already manage (decod stage -> in insert in ROB) |
---|
| 517 | case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 518 | case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 519 | case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 520 | case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 521 | default : |
---|
| 522 | { |
---|
| 523 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); |
---|
| 524 | break; |
---|
| 525 | } |
---|
| 526 | } |
---|
| 527 | } |
---|
[124] | 528 | |
---|
| 529 | log_printf(TRACE,Commit_unit,FUNCTION," * have_exception : %d",have_exception ); |
---|
| 530 | log_printf(TRACE,Commit_unit,FUNCTION," * have_miss_speculation : %d",have_miss_speculation); |
---|
| 531 | |
---|
[100] | 532 | |
---|
[122] | 533 | // Next state depends of previous state |
---|
[100] | 534 | switch (state) |
---|
| 535 | { |
---|
[122] | 536 | // Branch : if no exception, the branchement can be completed |
---|
| 537 | case ROB_BRANCH_WAIT_END : |
---|
| 538 | { |
---|
| 539 | if (not have_exception) |
---|
| 540 | state = ROB_BRANCH_COMPLETE; |
---|
| 541 | else |
---|
| 542 | state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 543 | break; |
---|
| 544 | } |
---|
| 545 | // Previous event -> set state as execute |
---|
| 546 | case ROB_STORE_KO_WAIT_END : |
---|
| 547 | case ROB_EVENT_WAIT_END : |
---|
| 548 | { |
---|
| 549 | state = ROB_END_KO_SPECULATIVE; |
---|
| 550 | break; |
---|
| 551 | } |
---|
| 552 | // No previous event - Load and other instruction |
---|
| 553 | case ROB_STORE_OK_WAIT_END : |
---|
| 554 | case ROB_OTHER_WAIT_END : |
---|
| 555 | { |
---|
| 556 | if (not have_exception) |
---|
| 557 | { |
---|
| 558 | if (not have_miss_speculation) |
---|
| 559 | state = ROB_END_OK_SPECULATIVE; |
---|
| 560 | else |
---|
| 561 | state = ROB_END_LOAD_MISS_SPECULATIVE; |
---|
| 562 | } |
---|
| 563 | else |
---|
| 564 | state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 565 | break; |
---|
| 566 | } |
---|
| 567 | case ROB_STORE_WAIT_END_OK : |
---|
| 568 | { |
---|
| 569 | if (not have_exception) |
---|
| 570 | state = ROB_STORE_OK; |
---|
| 571 | else |
---|
| 572 | state = ROB_STORE_EVENT; |
---|
| 573 | break; |
---|
| 574 | } |
---|
| 575 | case ROB_STORE_WAIT_END_KO : |
---|
| 576 | { |
---|
| 577 | // if (not have_exception) |
---|
| 578 | state = ROB_STORE_KO; |
---|
| 579 | // else |
---|
| 580 | // state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 581 | break; |
---|
| 582 | } |
---|
| 583 | |
---|
| 584 | |
---|
[100] | 585 | default : |
---|
| 586 | { |
---|
[115] | 587 | throw ERRORMORPHEO(FUNCTION,toString(_("Commit [%d] : Bank [%d][%d], invalid state value (%s).\n"),x,i,j,toString(state).c_str())); |
---|
[100] | 588 | break; |
---|
| 589 | } |
---|
| 590 | } |
---|
[88] | 591 | |
---|
[122] | 592 | // Commit an instruction ... |
---|
[123] | 593 | // Test if have an event (miss_speculation or exception) |
---|
[112] | 594 | |
---|
[123] | 595 | if (have_exception or have_miss_speculation) |
---|
[122] | 596 | { |
---|
[123] | 597 | // Two case : |
---|
| 598 | // if no previous manage event -> generate an event |
---|
| 599 | // if previous manage event -> next generate an event |
---|
| 600 | |
---|
| 601 | // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
---|
| 602 | bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
| 603 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or |
---|
[124] | 604 | (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)// or |
---|
| 605 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_END) |
---|
[123] | 606 | ); |
---|
| 607 | |
---|
[122] | 608 | uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i); |
---|
[123] | 609 | uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); |
---|
[124] | 610 | |
---|
| 611 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
| 612 | log_printf(TRACE,Commit_unit,FUNCTION," * packet : %d",packet); |
---|
[123] | 613 | |
---|
| 614 | if (not flush) |
---|
[122] | 615 | { |
---|
[123] | 616 | bool can = true; |
---|
| 617 | // test have a previous event detected (event_stop = 1) |
---|
| 618 | // if yes, test if the actual event if "before (in order)" that the previous event |
---|
| 619 | if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) |
---|
| 620 | { |
---|
| 621 | // Compare packet_id (by construction instruction is insert in order by increase packet_id) |
---|
| 622 | |
---|
| 623 | uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id]; |
---|
| 624 | uint32_t _new = packet; |
---|
| 625 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 626 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 627 | if (_new < _old) reg_EVENT_PACKET [front_end_id][context_id] = packet; |
---|
| 628 | else can = false; |
---|
| 629 | } |
---|
| 630 | else |
---|
| 631 | reg_EVENT_PACKET [front_end_id][context_id] = packet; |
---|
| 632 | |
---|
| 633 | if (can) |
---|
| 634 | { |
---|
| 635 | // have an error, stop issue instruction |
---|
| 636 | reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
---|
[124] | 637 | |
---|
[139] | 638 | // reg_EVENT_DEPTH [front_end_id][context_id] = _rob[packet].depth; |
---|
[124] | 639 | reg_EVENT_NB_INST [front_end_id][context_id] = reg_NB_INST_COMMIT_ALL [front_end_id][context_id]; |
---|
| 640 | |
---|
| 641 | //reg_EVENT_STOP [front_end_id][context_id] = true; |
---|
[123] | 642 | |
---|
| 643 | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 644 | reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; |
---|
| 645 | } |
---|
[122] | 646 | } |
---|
| 647 | else |
---|
[123] | 648 | { |
---|
| 649 | bool find = true; |
---|
[122] | 650 | |
---|
[124] | 651 | log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_STOP : %d",reg_EVENT_NEXT_STOP [front_end_id][context_id]); |
---|
| 652 | log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_PACKET : %d",reg_EVENT_NEXT_PACKET[front_end_id][context_id]); |
---|
| 653 | |
---|
[123] | 654 | // already manage an event. |
---|
| 655 | if (reg_EVENT_NEXT_STOP [front_end_id][context_id]) |
---|
| 656 | { |
---|
| 657 | // after last ? |
---|
| 658 | uint32_t _old = reg_EVENT_NEXT_PACKET [front_end_id][context_id]; |
---|
| 659 | uint32_t _new = packet; |
---|
[124] | 660 | |
---|
| 661 | log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top ); |
---|
| 662 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old ); |
---|
| 663 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new ); |
---|
| 664 | |
---|
[123] | 665 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 666 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 667 | if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; |
---|
[124] | 668 | else find = false; |
---|
| 669 | |
---|
| 670 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old ); |
---|
| 671 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new ); |
---|
[123] | 672 | } |
---|
| 673 | else |
---|
| 674 | { |
---|
| 675 | // after last ? |
---|
| 676 | uint32_t _old = ((reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id]); |
---|
| 677 | uint32_t _new = packet; |
---|
[124] | 678 | |
---|
| 679 | log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top ); |
---|
| 680 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old ); |
---|
| 681 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new ); |
---|
| 682 | |
---|
[123] | 683 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 684 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 685 | if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; |
---|
[124] | 686 | else find = false; |
---|
| 687 | |
---|
| 688 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old ); |
---|
| 689 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new ); |
---|
[123] | 690 | } |
---|
| 691 | |
---|
[124] | 692 | log_printf(TRACE,Commit_unit,FUNCTION," * find : %d",find); |
---|
| 693 | |
---|
[123] | 694 | if (find) |
---|
| 695 | reg_EVENT_NEXT_STOP [front_end_id][context_id] = true; // in all case : need stop |
---|
| 696 | } |
---|
[122] | 697 | } |
---|
[123] | 698 | |
---|
[122] | 699 | // Update Re Order Buffer |
---|
[105] | 700 | entry->state = state; |
---|
| 701 | entry->exception = exception; |
---|
| 702 | entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); |
---|
[122] | 703 | entry->no_sequence = no_sequence; |
---|
[105] | 704 | // jalr, jr : address_dest is in register |
---|
[122] | 705 | if (( type == TYPE_BRANCH) and |
---|
[105] | 706 | (entry->operation == OPERATION_BRANCH_L_JALR) and |
---|
| 707 | (entry->read_rb)) |
---|
| 708 | entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]); |
---|
[111] | 709 | |
---|
| 710 | #ifdef DEBUG |
---|
[122] | 711 | entry->load_data = PORT_READ(in_COMMIT_ADDRESS [x]); |
---|
| 712 | entry->cycle_commit = simulation_cycle(); |
---|
[111] | 713 | #endif |
---|
[88] | 714 | } |
---|
| 715 | } |
---|
| 716 | |
---|
| 717 | // =================================================================== |
---|
| 718 | // =====[ RETIRE ]==================================================== |
---|
| 719 | // =================================================================== |
---|
| 720 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[110] | 721 | { |
---|
[122] | 722 | // Compute bank number |
---|
[110] | 723 | uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; |
---|
| 724 | |
---|
[122] | 725 | // Test if have an request |
---|
[110] | 726 | if (internal_BANK_RETIRE_VAL [num_bank]) |
---|
| 727 | { |
---|
[122] | 728 | // Take num instruction |
---|
[110] | 729 | uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank]; |
---|
[144] | 730 | #ifdef DEBUG |
---|
[110] | 731 | uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank]; |
---|
[144] | 732 | #endif |
---|
[110] | 733 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); |
---|
[112] | 734 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank ); |
---|
[110] | 735 | |
---|
[88] | 736 | #ifdef DEBUG_TEST |
---|
[110] | 737 | if (not PORT_READ(in_RETIRE_ACK [x][y])) |
---|
| 738 | throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); |
---|
[88] | 739 | #endif |
---|
| 740 | |
---|
[122] | 741 | #ifdef STATISTICS |
---|
[139] | 742 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
[141] | 743 | stat_nb_inst_retire [x] ++; |
---|
[111] | 744 | #endif |
---|
[110] | 745 | |
---|
[122] | 746 | // Read information |
---|
| 747 | entry_t * entry = _rob [num_bank].front(); |
---|
[105] | 748 | |
---|
[122] | 749 | entry->state_old = entry->state; |
---|
| 750 | entry->state = ROB_END; |
---|
[139] | 751 | |
---|
| 752 | |
---|
| 753 | // Update RAT_UPDATE_TABLE |
---|
| 754 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 755 | Tcontext_t context_id = entry->context_id ; |
---|
| 756 | |
---|
| 757 | if (entry->write_rd and internal_BANK_RETIRE_RESTORE_RD_PHY_OLD [num_bank]) |
---|
| 758 | rat_gpr_update_table [front_end_id][context_id][entry->num_reg_rd_log] = true; |
---|
| 759 | if (entry->write_re and internal_BANK_RETIRE_RESTORE_RE_PHY_OLD [num_bank]) |
---|
| 760 | rat_spr_update_table [front_end_id][context_id][entry->num_reg_re_log] = true; |
---|
[110] | 761 | } |
---|
| 762 | } |
---|
[109] | 763 | |
---|
[122] | 764 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[88] | 765 | { |
---|
[122] | 766 | // Compute bank number |
---|
| 767 | bool can_continue = false; |
---|
| 768 | uint32_t num_bank = reg_NUM_BANK_HEAD; |
---|
| 769 | |
---|
| 770 | if (not _rob [num_bank].empty ()) |
---|
| 771 | { |
---|
| 772 | entry_t * entry = _rob [num_bank].front(); |
---|
| 773 | |
---|
| 774 | if (entry->state == ROB_END) |
---|
| 775 | { |
---|
| 776 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ROB [%d]",num_bank); |
---|
| 777 | |
---|
| 778 | can_continue = true; |
---|
[101] | 779 | |
---|
[142] | 780 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 781 | Tcontext_t context_id = entry->context_id ; |
---|
| 782 | uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id]; |
---|
| 783 | rob_state_t state = entry->state_old; |
---|
| 784 | Ttype_t type = entry->type ; |
---|
| 785 | Toperation_t operation = entry->operation ; |
---|
| 786 | bool retire_ok = false; |
---|
| 787 | uint32_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
[122] | 788 | |
---|
| 789 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); |
---|
| 790 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); |
---|
| 791 | log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",packet_id ); |
---|
| 792 | log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); |
---|
| 793 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
---|
| 794 | log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); |
---|
| 795 | |
---|
| 796 | // Test if the instruction is valid |
---|
| 797 | // (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction) |
---|
| 798 | // (LOAD_MISS = instruction load is valid, but have make an invalid result) |
---|
| 799 | if ((state == ROB_END_OK ) or |
---|
| 800 | // (state == ROB_END_KO ) or |
---|
| 801 | (state == ROB_END_BRANCH_MISS) or |
---|
| 802 | (state == ROB_END_LOAD_MISS )// or |
---|
| 803 | // (state == ROB_END_MISS ) or |
---|
| 804 | // (state == ROB_END_EXCEPTION ) |
---|
| 805 | ) |
---|
| 806 | { |
---|
| 807 | log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok"); |
---|
| 808 | |
---|
| 809 | retire_ok = true; |
---|
| 810 | |
---|
| 811 | // Update PC information |
---|
| 812 | // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; |
---|
| 813 | reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; |
---|
| 814 | reg_PC_CURRENT_IS_DS [front_end_id][context_id] = type == TYPE_BRANCH; |
---|
| 815 | reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; |
---|
| 816 | reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); |
---|
| 817 | } |
---|
| 818 | |
---|
| 819 | // Test if have an event |
---|
| 820 | if ((state == ROB_END_BRANCH_MISS) or |
---|
| 821 | (state == ROB_END_LOAD_MISS)) |
---|
| 822 | { |
---|
| 823 | reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT; |
---|
[139] | 824 | reg_EVENT_TYPE [front_end_id][context_id] = rob_state_to_event_type(state); |
---|
[123] | 825 | // reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue |
---|
[122] | 826 | reg_EVENT_LAST [front_end_id][context_id] = false; |
---|
| 827 | // it the head ! |
---|
| 828 | reg_EVENT_PACKET [front_end_id][context_id] = packet_id; |
---|
[139] | 829 | reg_EVENT_DEPTH [front_end_id][context_id] = entry->depth; |
---|
| 830 | |
---|
[123] | 831 | // // If event is an load_miss, many instruction can be inserted. |
---|
| 832 | // // -> new last instruction |
---|
| 833 | // if (state == ROB_END_LOAD_MISS) |
---|
| 834 | // { |
---|
| 835 | // // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false; |
---|
[122] | 836 | |
---|
[123] | 837 | // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 838 | // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; |
---|
| 839 | // } |
---|
[122] | 840 | } |
---|
| 841 | |
---|
| 842 | // Test if this instruction is the last instruction of an event |
---|
| 843 | // * need event |
---|
| 844 | // * packet id = last packet id |
---|
[124] | 845 | // for (uint32_t x=0; x<_param->_nb_front_end; x++) |
---|
| 846 | // for (uint32_t y=0; y<_param->_nb_context [x]; y++) |
---|
| 847 | // if (((reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NO_EVENT ) and |
---|
| 848 | // (reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and |
---|
| 849 | // (reg_EVENT_LAST_NUM_BANK [x][y] == num_bank ) and |
---|
| 850 | // (reg_EVENT_LAST_NUM_PTR [x][y] == entry->ptr )) |
---|
| 851 | // reg_EVENT_LAST [x][y] = true; |
---|
| 852 | |
---|
| 853 | |
---|
| 854 | if (reg_EVENT_NB_INST [front_end_id][context_id] > 0) |
---|
| 855 | { |
---|
| 856 | reg_EVENT_NB_INST [front_end_id][context_id] --; |
---|
| 857 | if (reg_EVENT_NB_INST [front_end_id][context_id] == 0) |
---|
| 858 | reg_EVENT_LAST [front_end_id][context_id] = true; |
---|
| 859 | } |
---|
| 860 | |
---|
[122] | 861 | // Update nb_inst |
---|
| 862 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; |
---|
| 863 | if (type == TYPE_MEMORY) |
---|
| 864 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; |
---|
[145] | 865 | if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE) |
---|
| 866 | reg_NB_INST_DEPTH [front_end_id][context_id][entry->depth] --; |
---|
[122] | 867 | // Update pointer |
---|
| 868 | reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank; |
---|
| 869 | |
---|
| 870 | // Reset watch dog timer because have transaction on retire interface |
---|
| 871 | _nb_cycle_idle [front_end_id][context_id] = 0; |
---|
| 872 | |
---|
| 873 | // Increase stop condition |
---|
| 874 | if (retire_ok) |
---|
| 875 | _simulation_nb_instruction_commited [num_thread] ++; |
---|
[88] | 876 | |
---|
[122] | 877 | #ifdef STATISTICS |
---|
| 878 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 879 | { |
---|
| 880 | if (retire_ok) |
---|
| 881 | { |
---|
[137] | 882 | uint32_t instruction = entry->instruction; |
---|
| 883 | |
---|
| 884 | (*_stat_nb_inst_retire_ok [num_thread] ) ++; |
---|
| 885 | (*_stat_nb_inst_instruction [instruction]) ++; |
---|
| 886 | (*_stat_nb_inst_type [type] ) ++; |
---|
[142] | 887 | |
---|
| 888 | //uint32_t index = (_stat_last_inst [num_thread] << SIZE_INSTRUCTION) | instruction; |
---|
| 889 | uint32_t index = ((_stat_last_inst_type [num_thread] << (SIZE_TYPE+2*SIZE_OPERATION)) | |
---|
| 890 | (_stat_last_inst_operation [num_thread] << (SIZE_TYPE+ SIZE_OPERATION)) | |
---|
| 891 | ( type << ( SIZE_OPERATION)) | |
---|
| 892 | ( operation )); |
---|
| 893 | |
---|
| 894 | _stat_inst_fusion [num_thread][index] ++; |
---|
| 895 | |
---|
| 896 | //_stat_last_inst [num_thread] = instruction; |
---|
| 897 | _stat_last_inst_type [num_thread] = type ; |
---|
| 898 | _stat_last_inst_operation [num_thread] = operation ; |
---|
[122] | 899 | } |
---|
| 900 | else |
---|
| 901 | (*_stat_nb_inst_retire_ko [num_thread]) ++; |
---|
| 902 | } |
---|
| 903 | #endif |
---|
[88] | 904 | |
---|
[122] | 905 | #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) |
---|
[134] | 906 | if (log_file_generate) |
---|
| 907 | { |
---|
| 908 | // log file |
---|
| 909 | instruction_log_file [num_thread] |
---|
| 910 | << "[" << simulation_cycle() << "] " |
---|
| 911 | << std::hex |
---|
| 912 | << (entry->address<<2) << " (" << (entry->address) << ") " |
---|
| 913 | << std::dec |
---|
| 914 | << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] " |
---|
| 915 | << "{" << ((retire_ok)?"OK":"KO") << "} "; |
---|
| 916 | |
---|
[142] | 917 | if ((type == TYPE_MEMORY) and is_operation_memory_load(operation)) |
---|
[134] | 918 | instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec; |
---|
| 919 | |
---|
| 920 | instruction_log_file [num_thread] << std::endl; |
---|
| 921 | } |
---|
[122] | 922 | #endif |
---|
[123] | 923 | |
---|
| 924 | // Remove entry |
---|
| 925 | delete entry; |
---|
| 926 | _rob [num_bank].pop_front(); |
---|
[122] | 927 | } |
---|
[88] | 928 | } |
---|
[122] | 929 | |
---|
| 930 | if (not can_continue) |
---|
| 931 | break; // stop scan |
---|
[88] | 932 | } |
---|
| 933 | |
---|
| 934 | // =================================================================== |
---|
[122] | 935 | // =====[ REEXECUTE ]================================================= |
---|
| 936 | // =================================================================== |
---|
| 937 | // Test if have an reexecute instruction (an store in head of rob) |
---|
| 938 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) |
---|
| 939 | if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i])) |
---|
| 940 | { |
---|
| 941 | log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [%d]",i); |
---|
| 942 | |
---|
| 943 | uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i]; |
---|
| 944 | |
---|
| 945 | entry_t * entry = _rob [num_bank].front(); |
---|
| 946 | rob_state_t state = entry->state; |
---|
| 947 | |
---|
| 948 | // Change state |
---|
| 949 | switch (state) |
---|
| 950 | { |
---|
| 951 | case ROB_STORE_OK : {state = ROB_STORE_OK_WAIT_END; break; } |
---|
| 952 | case ROB_STORE_KO : {state = ROB_STORE_KO_WAIT_END; break; } |
---|
| 953 | case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; } |
---|
| 954 | default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} |
---|
| 955 | } |
---|
| 956 | |
---|
| 957 | entry->state = state; |
---|
| 958 | } |
---|
| 959 | |
---|
| 960 | // =================================================================== |
---|
[88] | 961 | // =====[ BRANCH_COMPLETE ]=========================================== |
---|
| 962 | // =================================================================== |
---|
| 963 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
---|
[122] | 964 | // Test if the prediction_unit have accept the branch complete transaction |
---|
[88] | 965 | if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) |
---|
| 966 | { |
---|
[101] | 967 | log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
---|
| 968 | |
---|
[122] | 969 | // Read information |
---|
[88] | 970 | uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; |
---|
| 971 | |
---|
| 972 | entry_t * entry = _rob [num_bank].front(); |
---|
| 973 | |
---|
| 974 | #ifdef DEBUG_TEST |
---|
| 975 | rob_state_t state = entry->state; |
---|
| 976 | if (state != ROB_BRANCH_COMPLETE) |
---|
| 977 | throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); |
---|
| 978 | #endif |
---|
[112] | 979 | Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]); |
---|
[122] | 980 | |
---|
| 981 | log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",miss); |
---|
[112] | 982 | |
---|
| 983 | entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; |
---|
[88] | 984 | |
---|
[122] | 985 | // bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id]; |
---|
[112] | 986 | |
---|
[122] | 987 | // Branch_complete can be execute if |
---|
| 988 | // * no present event |
---|
| 989 | // * futur event and most not speculative that the event |
---|
| 990 | |
---|
| 991 | // Also, test if in this cycle, they have not an most recently event !!! |
---|
| 992 | if (miss) |
---|
| 993 | { |
---|
[123] | 994 | bool can = true; |
---|
[122] | 995 | uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
| 996 | |
---|
| 997 | // test if this packet is before previous event |
---|
[123] | 998 | if (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) |
---|
[122] | 999 | { |
---|
| 1000 | uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); |
---|
| 1001 | uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id]; |
---|
| 1002 | uint32_t _new = packet; |
---|
| 1003 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 1004 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 1005 | if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; |
---|
[123] | 1006 | else can = false; |
---|
[122] | 1007 | } |
---|
| 1008 | else |
---|
| 1009 | reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; |
---|
| 1010 | |
---|
[123] | 1011 | if (can) |
---|
| 1012 | { |
---|
| 1013 | // In all case, stop instruction flow |
---|
| 1014 | reg_EVENT_STATE [entry->front_end_id][entry->context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
---|
[139] | 1015 | // reg_EVENT_DEPTH [entry->front_end_id][entry->context_id] = _rob[packet]._depth; |
---|
[124] | 1016 | reg_EVENT_NB_INST [entry->front_end_id][entry->context_id] = reg_NB_INST_COMMIT_ALL [entry->front_end_id][entry->context_id]; |
---|
[123] | 1017 | // reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; |
---|
[122] | 1018 | |
---|
[123] | 1019 | // reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; |
---|
[122] | 1020 | |
---|
[123] | 1021 | reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 1022 | reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; |
---|
| 1023 | } |
---|
[122] | 1024 | } |
---|
[88] | 1025 | } |
---|
| 1026 | |
---|
| 1027 | // =================================================================== |
---|
[100] | 1028 | // =====[ UPDATE ]==================================================== |
---|
| 1029 | // =================================================================== |
---|
[122] | 1030 | // Update when exception or load_miss |
---|
[105] | 1031 | if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) |
---|
| 1032 | { |
---|
| 1033 | log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); |
---|
[100] | 1034 | |
---|
[122] | 1035 | // Change state |
---|
[105] | 1036 | entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); |
---|
| 1037 | |
---|
| 1038 | switch (entry->state) |
---|
| 1039 | { |
---|
| 1040 | // case ROB_END_EXCEPTION_UPDATE : |
---|
| 1041 | // { |
---|
| 1042 | // entry->state = ROB_END_KO; |
---|
| 1043 | // throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); |
---|
| 1044 | // break; |
---|
| 1045 | // } |
---|
| 1046 | case ROB_END_LOAD_MISS_UPDATE : |
---|
| 1047 | { |
---|
| 1048 | log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); |
---|
| 1049 | |
---|
| 1050 | entry->state = ROB_END_LOAD_MISS; |
---|
| 1051 | break; |
---|
| 1052 | } |
---|
| 1053 | default : |
---|
| 1054 | { |
---|
| 1055 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n")); |
---|
| 1056 | break; |
---|
| 1057 | } |
---|
| 1058 | } |
---|
| 1059 | } |
---|
| 1060 | |
---|
[100] | 1061 | // =================================================================== |
---|
[88] | 1062 | // =====[ EVENT ]===================================================== |
---|
| 1063 | // =================================================================== |
---|
[108] | 1064 | // for (uint32_t i=0; i < _param->_nb_front_end; ++i) |
---|
| 1065 | // for (uint32_t j=0; j < _param->_nb_context[i]; ++j) |
---|
| 1066 | // if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j]) |
---|
| 1067 | // { |
---|
| 1068 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j); |
---|
[88] | 1069 | |
---|
[108] | 1070 | // reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]); |
---|
| 1071 | // reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ?? |
---|
| 1072 | // reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); |
---|
| 1073 | // reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]); |
---|
| 1074 | // // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]); |
---|
| 1075 | // } |
---|
| 1076 | |
---|
[88] | 1077 | // =================================================================== |
---|
| 1078 | // =====[ DEPTH - HEAD ]============================================== |
---|
| 1079 | // =================================================================== |
---|
| 1080 | |
---|
[122] | 1081 | { |
---|
[124] | 1082 | bool can_continue [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1083 | uint32_t event_nb_inst [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1084 | bool is_speculative [_param->_nb_front_end][_param->_max_nb_context]; |
---|
[122] | 1085 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1086 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
[124] | 1087 | { |
---|
| 1088 | event_nb_inst [i][j] = 0; |
---|
| 1089 | is_speculative[i][j] = false; |
---|
| 1090 | can_continue [i][j] = (((reg_EVENT_NB_INST [i][j] == 0) or |
---|
| 1091 | ( event_nb_inst [i][j] < reg_EVENT_NB_INST [i][j])) and |
---|
| 1092 | not reg_EVENT_LAST [i][j]); |
---|
| 1093 | } |
---|
[122] | 1094 | |
---|
| 1095 | // Read all instruction of all top bank |
---|
| 1096 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 1097 | { |
---|
| 1098 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
[88] | 1099 | |
---|
[122] | 1100 | // Test if have an instruction |
---|
| 1101 | if (not _rob[num_bank].empty()) |
---|
| 1102 | { |
---|
| 1103 | // Scan all instruction in windows and test if instruction is speculative |
---|
| 1104 | entry_t * entry = _rob [num_bank].front(); |
---|
[124] | 1105 | |
---|
| 1106 | uint32_t num_packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
[122] | 1107 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 1108 | Tcontext_t context_id = entry->context_id ; |
---|
[124] | 1109 | |
---|
| 1110 | log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d] - %d",num_bank,num_packet); |
---|
| 1111 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
---|
| 1112 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
---|
| 1113 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d",reg_EVENT_LAST [front_end_id][context_id]); |
---|
| 1114 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NB_INST : %d",reg_EVENT_NB_INST [front_end_id][context_id]); |
---|
| 1115 | log_printf(TRACE,Commit_unit,FUNCTION," * event_nb_inst : %d", event_nb_inst [front_end_id][context_id]); |
---|
[122] | 1116 | |
---|
| 1117 | // scan while last event instruction is not retire |
---|
[124] | 1118 | if (can_continue [front_end_id][context_id]) |
---|
[122] | 1119 | { |
---|
| 1120 | // Read information |
---|
| 1121 | rob_state_t state = entry->state; |
---|
[137] | 1122 | // Tdepth_t depth = entry->depth; |
---|
[122] | 1123 | |
---|
[137] | 1124 | // Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; |
---|
| 1125 | // Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; |
---|
| 1126 | // Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); |
---|
[122] | 1127 | |
---|
| 1128 | // is a valid instruction ? |
---|
| 1129 | // If DEPTH_CURRENT : |
---|
| 1130 | // equal at DEPTH_MIN -> not speculative |
---|
| 1131 | // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss |
---|
| 1132 | // include ]DEPTH_MIN:DEPTH_MAX] -> speculative |
---|
| 1133 | |
---|
| 1134 | // All case |
---|
| 1135 | // ....... min ...X... max ....... OK |
---|
| 1136 | // ....... min ....... max ...X... KO |
---|
| 1137 | // ...X... min ....... max ....... KO |
---|
| 1138 | // ....... max ....... min ...X... OK |
---|
| 1139 | // ...X... max ....... min ....... OK |
---|
| 1140 | // ....... max ...X... min ....... KO |
---|
| 1141 | |
---|
| 1142 | bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
[123] | 1143 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or |
---|
[122] | 1144 | (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)); |
---|
[124] | 1145 | bool speculative = is_speculative [front_end_id][context_id]; |
---|
| 1146 | |
---|
| 1147 | // bool speculative = entry->speculative and not (depth == depth_min); |
---|
| 1148 | // Tcontrol_t is_valid = ((not speculative or |
---|
| 1149 | // (speculative and (depth_full or // all is valid |
---|
| 1150 | // ((depth_min <= depth_max)? // test if depth is overflow |
---|
| 1151 | // ((depth >= depth_min) and (depth <=depth_max)): |
---|
| 1152 | // ((depth >= depth_min) or (depth <=depth_max)))))) |
---|
| 1153 | // and not flush); // no event |
---|
| 1154 | |
---|
| 1155 | Tcontrol_t is_valid = not flush; |
---|
| 1156 | |
---|
| 1157 | |
---|
[122] | 1158 | //Tcontrol_t is_valid = ((depth == depth_min) and not flush); |
---|
| 1159 | |
---|
| 1160 | |
---|
| 1161 | log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); |
---|
[137] | 1162 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); |
---|
| 1163 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); |
---|
| 1164 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); |
---|
| 1165 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); |
---|
[122] | 1166 | log_printf(TRACE,Commit_unit,FUNCTION," * speculative : %d",speculative); |
---|
| 1167 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
[124] | 1168 | log_printf(TRACE,Commit_unit,FUNCTION," * state (before) : %s",toString(state).c_str()); |
---|
| 1169 | |
---|
| 1170 | // //------------------------------------------------------ |
---|
| 1171 | // // Event ? |
---|
| 1172 | // //------------------------------------------------------ |
---|
| 1173 | |
---|
| 1174 | // if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and |
---|
| 1175 | // (reg_EVENT_PACKET [front_end_id][context_id] == num_packet)) |
---|
| 1176 | // { |
---|
| 1177 | // switch (state) |
---|
| 1178 | // { |
---|
| 1179 | // case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
| 1180 | // case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
| 1181 | // case ROB_END_BRANCH_MISS : |
---|
| 1182 | // case ROB_END_LOAD_MISS : |
---|
| 1183 | // case ROB_END : |
---|
| 1184 | // {break;} |
---|
| 1185 | // default : |
---|
| 1186 | // { |
---|
| 1187 | // throw ERRORMORPHEO(FUNCTION,toString(_("Head [%d] : invalid state (%s)"),num_packet,toString(state).c_str())); |
---|
| 1188 | // break; |
---|
| 1189 | // } |
---|
| 1190 | // } |
---|
| 1191 | // } |
---|
[122] | 1192 | |
---|
| 1193 | //------------------------------------------------------ |
---|
| 1194 | // test if instruction is miss speculative |
---|
| 1195 | //------------------------------------------------------ |
---|
| 1196 | if (not is_valid) |
---|
| 1197 | { |
---|
| 1198 | // Change state |
---|
| 1199 | switch (state) |
---|
| 1200 | { |
---|
[145] | 1201 | case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END ; break;} |
---|
| 1202 | case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} |
---|
[122] | 1203 | case ROB_END_BRANCH_MISS : |
---|
[145] | 1204 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
[124] | 1205 | case ROB_END_LOAD_MISS : |
---|
[122] | 1206 | case ROB_END_LOAD_MISS_UPDATE : |
---|
[145] | 1207 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 1208 | case ROB_STORE_OK : {state = ROB_STORE_KO ; break;} |
---|
[122] | 1209 | case ROB_STORE_WAIT_END_OK : {state = ROB_STORE_WAIT_END_KO; break;} |
---|
| 1210 | case ROB_STORE_OK_WAIT_END : {state = ROB_STORE_KO_WAIT_END; break;} |
---|
[145] | 1211 | case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END ; break;} |
---|
[122] | 1212 | case ROB_END_OK : |
---|
[145] | 1213 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
[122] | 1214 | case ROB_END_KO : |
---|
[145] | 1215 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
[122] | 1216 | case ROB_END_EXCEPTION_UPDATE : |
---|
| 1217 | case ROB_END_EXCEPTION : |
---|
[145] | 1218 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} |
---|
[122] | 1219 | |
---|
| 1220 | // don't change state -> wait |
---|
| 1221 | case ROB_STORE_WAIT_END_KO : {break;} |
---|
| 1222 | case ROB_STORE_KO : {break;} |
---|
| 1223 | case ROB_STORE_KO_WAIT_END : {break;} |
---|
| 1224 | case ROB_STORE_EVENT : {break;} |
---|
| 1225 | case ROB_EVENT_WAIT_END : {break;} |
---|
| 1226 | case ROB_END_MISS : {break;} |
---|
| 1227 | case ROB_END : {break;} |
---|
| 1228 | |
---|
| 1229 | // can't have miss speculation -> invalid state |
---|
| 1230 | default : |
---|
| 1231 | { |
---|
| 1232 | throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); |
---|
| 1233 | break; |
---|
| 1234 | } |
---|
| 1235 | } |
---|
| 1236 | } |
---|
[124] | 1237 | |
---|
| 1238 | //------------------------------------------------------ |
---|
| 1239 | // test if instruction is branch not finish |
---|
| 1240 | //------------------------------------------------------ |
---|
| 1241 | switch (state) |
---|
| 1242 | { |
---|
| 1243 | case ROB_BRANCH_WAIT_END : |
---|
| 1244 | case ROB_BRANCH_COMPLETE : |
---|
| 1245 | { |
---|
| 1246 | is_speculative [front_end_id][context_id] = true; |
---|
| 1247 | break; |
---|
| 1248 | } |
---|
| 1249 | default : break; |
---|
| 1250 | } |
---|
[122] | 1251 | |
---|
| 1252 | //------------------------------------------------------ |
---|
| 1253 | // test if instruction is not speculative |
---|
| 1254 | //------------------------------------------------------ |
---|
[124] | 1255 | // entry->speculative = speculative; |
---|
[122] | 1256 | // if (entry->depth == depth_min) |
---|
| 1257 | // test if instruction is speculative (depth != depth_min) |
---|
| 1258 | if (not speculative) |
---|
| 1259 | { |
---|
| 1260 | switch (state) |
---|
| 1261 | { |
---|
| 1262 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} |
---|
| 1263 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} |
---|
| 1264 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
| 1265 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
| 1266 | default : {break;} // else, no change |
---|
| 1267 | } |
---|
| 1268 | } |
---|
| 1269 | |
---|
| 1270 | //------------------------------------------------------ |
---|
| 1271 | // test if instruction wait head and is the top of rob |
---|
| 1272 | //------------------------------------------------------ |
---|
| 1273 | // TODO : retire OOO |
---|
| 1274 | if (i == 0) |
---|
| 1275 | { |
---|
| 1276 | switch (state) |
---|
| 1277 | { |
---|
| 1278 | // case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} |
---|
| 1279 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} |
---|
| 1280 | default : {break;} // else, no change |
---|
| 1281 | } |
---|
| 1282 | } |
---|
| 1283 | |
---|
| 1284 | // Write new state |
---|
| 1285 | entry->state = state; |
---|
[124] | 1286 | |
---|
| 1287 | log_printf(TRACE,Commit_unit,FUNCTION," * state (after ) : %s",toString(state).c_str()); |
---|
[122] | 1288 | |
---|
[124] | 1289 | // log_printf(TRACE,Commit_unit,FUNCTION," * Stop Scan !!!"); |
---|
[122] | 1290 | |
---|
[124] | 1291 | event_nb_inst [front_end_id][context_id] ++; |
---|
| 1292 | |
---|
| 1293 | // stop if : |
---|
| 1294 | // * begin event |
---|
| 1295 | // * end event |
---|
| 1296 | if (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and |
---|
| 1297 | (reg_EVENT_PACKET[front_end_id][context_id] == num_packet)) or |
---|
| 1298 | ((reg_EVENT_NB_INST [front_end_id][context_id] > 0) and |
---|
| 1299 | ( event_nb_inst [front_end_id][context_id] >= reg_EVENT_NB_INST [front_end_id][context_id]))) |
---|
| 1300 | can_continue [front_end_id][context_id] = false; |
---|
[122] | 1301 | } |
---|
| 1302 | } |
---|
| 1303 | } |
---|
| 1304 | } |
---|
[105] | 1305 | |
---|
| 1306 | |
---|
[101] | 1307 | |
---|
[122] | 1308 | #ifdef STATISTICS |
---|
[124] | 1309 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 1310 | { |
---|
| 1311 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 1312 | *(_stat_bank_nb_inst [i]) += _rob[i].size(); |
---|
| 1313 | |
---|
| 1314 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1315 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1316 | { |
---|
| 1317 | uint32_t num_thread = _param->_translate_num_context_to_num_thread [i][j]; |
---|
| 1318 | |
---|
| 1319 | switch (reg_EVENT_STATE [i][j]) |
---|
| 1320 | { |
---|
| 1321 | case COMMIT_EVENT_STATE_NO_EVENT : (*_stat_nb_cycle_state_no_event [num_thread])++; break; |
---|
| 1322 | case COMMIT_EVENT_STATE_NOT_YET_EVENT : (*_stat_nb_cycle_state_not_yet_event [num_thread])++; break; |
---|
| 1323 | case COMMIT_EVENT_STATE_EVENT : (*_stat_nb_cycle_state_event [num_thread])++; break; |
---|
| 1324 | case COMMIT_EVENT_STATE_WAIT_END : (*_stat_nb_cycle_state_wait_end [num_thread])++; break; |
---|
| 1325 | } |
---|
| 1326 | } |
---|
[141] | 1327 | |
---|
| 1328 | for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) |
---|
| 1329 | { |
---|
| 1330 | (*_stat_nb_inst_insert [i]) += stat_nb_inst_insert [i]; |
---|
| 1331 | (*_stat_nb_inst_retire [i]) += stat_nb_inst_retire [i]; |
---|
| 1332 | (*_stat_nb_inst_commit [i]) += stat_nb_inst_commit [i]; |
---|
| 1333 | } |
---|
[124] | 1334 | } |
---|
[122] | 1335 | #endif |
---|
[88] | 1336 | } |
---|
| 1337 | |
---|
| 1338 | // =================================================================== |
---|
| 1339 | // =====[ OTHER ]===================================================== |
---|
| 1340 | // =================================================================== |
---|
| 1341 | |
---|
[108] | 1342 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) |
---|
| 1343 | { |
---|
| 1344 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); |
---|
| 1345 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); |
---|
| 1346 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); |
---|
[122] | 1347 | log_printf(TRACE,Commit_unit,FUNCTION," * num_ptr_tail : %d",reg_NUM_PTR_TAIL ); |
---|
[108] | 1348 | |
---|
| 1349 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1350 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1351 | { |
---|
[110] | 1352 | log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]); |
---|
[122] | 1353 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str()); |
---|
| 1354 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); |
---|
[123] | 1355 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); |
---|
| 1356 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]); |
---|
| 1357 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]); |
---|
[145] | 1358 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_DEPTH : %d",reg_EVENT_DEPTH [i][j]); |
---|
| 1359 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_TYPE : %s",toString(reg_EVENT_TYPE [i][j]).c_str()); |
---|
[124] | 1360 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]); |
---|
| 1361 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT : stop : %d - packet : %d",reg_EVENT_NEXT_STOP [i][j],reg_EVENT_NEXT_PACKET[i][j]); |
---|
| 1362 | log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : all : %d - mem : %d - event : %d",reg_NB_INST_COMMIT_ALL[i][j], reg_NB_INST_COMMIT_MEM[i][j],reg_EVENT_NB_INST[i][j]); |
---|
| 1363 | log_printf(TRACE,Commit_unit,FUNCTION," * PC : %.8x (%.8x) - %d %d - %.8x (%.8x)",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j],reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); |
---|
[108] | 1364 | } |
---|
| 1365 | |
---|
[122] | 1366 | std::list<entry_t*>::iterator iter [_param->_nb_bank]; |
---|
[108] | 1367 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[104] | 1368 | { |
---|
[108] | 1369 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
[122] | 1370 | // log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); |
---|
[108] | 1371 | |
---|
[122] | 1372 | iter [num_bank] = _rob[num_bank].begin(); |
---|
| 1373 | } |
---|
| 1374 | |
---|
[123] | 1375 | bool all_empty = false; |
---|
| 1376 | uint32_t nb_write_rd = 0; |
---|
| 1377 | uint32_t nb_write_re = 0; |
---|
| 1378 | |
---|
[122] | 1379 | while (not all_empty) |
---|
| 1380 | { |
---|
| 1381 | all_empty = true; |
---|
[108] | 1382 | |
---|
[122] | 1383 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[108] | 1384 | { |
---|
[122] | 1385 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
| 1386 | |
---|
| 1387 | std::list<entry_t*>::iterator it = iter[num_bank]; |
---|
| 1388 | if (it != _rob[num_bank].end()) |
---|
| 1389 | { |
---|
| 1390 | all_empty = false; |
---|
| 1391 | |
---|
[123] | 1392 | nb_write_rd += ((*it)->write_rd)?1:0; |
---|
| 1393 | nb_write_re += ((*it)->write_re)?1:0; |
---|
| 1394 | |
---|
[124] | 1395 | log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", |
---|
[122] | 1396 | num_bank , |
---|
| 1397 | (*it)->ptr , |
---|
| 1398 | (*it)->front_end_id , |
---|
| 1399 | (*it)->context_id , |
---|
| 1400 | (*it)->rename_unit_id , |
---|
| 1401 | (*it)->depth , |
---|
| 1402 | (*it)->type , |
---|
| 1403 | (*it)->operation , |
---|
| 1404 | (*it)->is_delay_slot , |
---|
| 1405 | (*it)->use_store_queue , |
---|
| 1406 | (*it)->store_queue_ptr_write , |
---|
| 1407 | (*it)->use_load_queue , |
---|
| 1408 | (*it)->load_queue_ptr_write , |
---|
| 1409 | toString((*it)->state).c_str() ); |
---|
[124] | 1410 | log_printf(TRACE,Commit_unit,FUNCTION," (%.4d) %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", |
---|
| 1411 | (((*it)->ptr << _param->_shift_num_slot) | num_bank), |
---|
[122] | 1412 | (*it)->read_ra , |
---|
| 1413 | (*it)->num_reg_ra_log , |
---|
| 1414 | (*it)->num_reg_ra_phy , |
---|
| 1415 | (*it)->read_rb , |
---|
| 1416 | (*it)->num_reg_rb_log , |
---|
| 1417 | (*it)->num_reg_rb_phy , |
---|
| 1418 | (*it)->read_rc , |
---|
| 1419 | (*it)->num_reg_rc_log , |
---|
| 1420 | (*it)->num_reg_rc_phy , |
---|
| 1421 | (*it)->write_rd , |
---|
| 1422 | (*it)->num_reg_rd_log , |
---|
| 1423 | (*it)->num_reg_rd_phy_old , |
---|
| 1424 | (*it)->num_reg_rd_phy_new , |
---|
| 1425 | (*it)->write_re , |
---|
| 1426 | (*it)->num_reg_re_log , |
---|
| 1427 | (*it)->num_reg_re_phy_old , |
---|
| 1428 | (*it)->num_reg_re_phy_new ); |
---|
| 1429 | |
---|
[124] | 1430 | log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", |
---|
[122] | 1431 | (*it)->exception_use , |
---|
| 1432 | (*it)->exception , |
---|
| 1433 | (*it)->flags , |
---|
| 1434 | (*it)->no_sequence , |
---|
[128] | 1435 | // (*it)->speculative , |
---|
[122] | 1436 | (*it)->address , |
---|
| 1437 | (*it)->address<<2 , |
---|
| 1438 | (*it)->address_next , |
---|
| 1439 | (*it)->address_next<<2 |
---|
| 1440 | ); |
---|
| 1441 | |
---|
| 1442 | iter [num_bank] ++; |
---|
| 1443 | } |
---|
[108] | 1444 | } |
---|
[104] | 1445 | } |
---|
[123] | 1446 | |
---|
[145] | 1447 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump RAT_Update Table"); |
---|
[139] | 1448 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
---|
| 1449 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
---|
| 1450 | { |
---|
| 1451 | { |
---|
| 1452 | std::string str = ""; |
---|
| 1453 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
---|
| 1454 | str+=toString("%.1d ",rat_gpr_update_table[i][j][k]); |
---|
| 1455 | |
---|
| 1456 | log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str()); |
---|
| 1457 | } |
---|
| 1458 | |
---|
| 1459 | { |
---|
| 1460 | std::string str = ""; |
---|
| 1461 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
---|
| 1462 | str+=toString("%.1d ",rat_spr_update_table[i][j][k]); |
---|
| 1463 | |
---|
| 1464 | log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str()); |
---|
| 1465 | } |
---|
| 1466 | } |
---|
| 1467 | |
---|
[123] | 1468 | log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_rd : %d",nb_write_rd); |
---|
| 1469 | log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_re : %d",nb_write_re); |
---|
[108] | 1470 | } |
---|
[88] | 1471 | #endif |
---|
| 1472 | |
---|
[108] | 1473 | #ifdef DEBUG_TEST |
---|
| 1474 | { |
---|
| 1475 | uint32_t x=reg_NUM_BANK_HEAD; |
---|
| 1476 | if (not _rob[x].empty()) |
---|
| 1477 | { |
---|
| 1478 | entry_t * entry = _rob [x].front(); |
---|
[97] | 1479 | |
---|
[108] | 1480 | if (false |
---|
| 1481 | // or (entry->state == ROB_EMPTY ) |
---|
| 1482 | // or (entry->state == ROB_BRANCH_WAIT_END ) |
---|
| 1483 | // or (entry->state == ROB_BRANCH_COMPLETE ) |
---|
| 1484 | // or (entry->state == ROB_STORE_WAIT_HEAD_OK ) |
---|
| 1485 | // //or (entry->state == ROB_STORE_WAIT_HEAD_KO ) |
---|
| 1486 | // or (entry->state == ROB_STORE_HEAD_OK ) |
---|
| 1487 | // or (entry->state == ROB_STORE_HEAD_KO ) |
---|
| 1488 | // or (entry->state == ROB_OTHER_WAIT_END ) |
---|
[112] | 1489 | // or (entry->state == ROB_EVENT_WAIT_END ) |
---|
[108] | 1490 | // or (entry->state == ROB_END_OK_SPECULATIVE ) |
---|
| 1491 | or (entry->state == ROB_END_OK ) |
---|
| 1492 | // or (entry->state == ROB_END_KO_SPECULATIVE ) |
---|
| 1493 | // or (entry->state == ROB_END_KO ) |
---|
| 1494 | // or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE) |
---|
| 1495 | or (entry->state == ROB_END_BRANCH_MISS ) |
---|
| 1496 | // or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE ) |
---|
| 1497 | // or (entry->state == ROB_END_LOAD_MISS_UPDATE ) |
---|
| 1498 | or (entry->state == ROB_END_LOAD_MISS ) |
---|
| 1499 | // or (entry->state == ROB_END_MISS ) |
---|
| 1500 | // or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD ) |
---|
| 1501 | // or (entry->state == ROB_END_EXCEPTION_UPDATE ) |
---|
| 1502 | // or (entry->state == ROB_END_EXCEPTION ) |
---|
| 1503 | ) |
---|
| 1504 | if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) |
---|
[122] | 1505 | throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"), |
---|
[108] | 1506 | entry->address, |
---|
| 1507 | entry->front_end_id, |
---|
| 1508 | entry->context_id, |
---|
| 1509 | reg_PC_CURRENT[entry->front_end_id][entry->context_id])); |
---|
| 1510 | } |
---|
| 1511 | } |
---|
[124] | 1512 | { |
---|
| 1513 | uint32_t NB_INST [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1514 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1515 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1516 | NB_INST [i][j] = 0; //reg_EVENT_NB_INST [i][j]; |
---|
| 1517 | |
---|
| 1518 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
---|
| 1519 | for (std::list<entry_t*>::iterator it=_rob[i].begin(); |
---|
| 1520 | it!=_rob [i].end(); |
---|
| 1521 | ++it) |
---|
| 1522 | NB_INST [(*it)->front_end_id][(*it)->context_id] ++; |
---|
| 1523 | |
---|
| 1524 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1525 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1526 | if (NB_INST [i][j] != reg_NB_INST_COMMIT_ALL [i][j]) |
---|
| 1527 | throw ERRORMORPHEO(FUNCTION,toString(_("Context [%d][%d] have not the good nb_inst (%d in rob, %d in register).\n"),i,j,NB_INST[i][j], reg_NB_INST_COMMIT_ALL [i][j])); |
---|
| 1528 | } |
---|
[108] | 1529 | #endif |
---|
[88] | 1530 | |
---|
| 1531 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 1532 | end_cycle (); |
---|
| 1533 | #endif |
---|
| 1534 | |
---|
[109] | 1535 | // Stop Condition |
---|
| 1536 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1537 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
[110] | 1538 | if (_nb_cycle_idle [i][j] >= debug_idle_cycle) |
---|
| 1539 | throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j])); |
---|
[109] | 1540 | |
---|
[88] | 1541 | log_end(Commit_unit,FUNCTION); |
---|
| 1542 | }; |
---|
| 1543 | |
---|
| 1544 | }; // end namespace commit_unit |
---|
| 1545 | }; // end namespace ooo_engine |
---|
| 1546 | }; // end namespace multi_ooo_engine |
---|
| 1547 | }; // end namespace core |
---|
| 1548 | |
---|
| 1549 | }; // end namespace behavioural |
---|
| 1550 | }; // end namespace morpheo |
---|
| 1551 | #endif |
---|