[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_transition.cpp 137 2010-02-16 12:35:48Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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[110] | 10 | #include "Behavioural/include/Simulation.h" |
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[88] | 11 | |
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| 12 | namespace morpheo { |
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| 13 | namespace behavioural { |
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| 14 | namespace core { |
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| 15 | namespace multi_ooo_engine { |
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| 16 | namespace ooo_engine { |
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| 17 | namespace commit_unit { |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::transition" |
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| 21 | void Commit_unit::transition (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[100] | 28 | // Clear all bank |
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[115] | 29 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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[88] | 30 | { |
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[115] | 31 | while(not _rob[i].empty()) |
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| 32 | { |
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| 33 | delete _rob[i].front(); |
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| 34 | _rob[i].pop_front(); |
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| 35 | } |
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[88] | 36 | reg_BANK_PTR [i] = 0; |
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| 37 | } |
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| 38 | |
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[100] | 39 | // Reset pointer |
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[88] | 40 | reg_NUM_BANK_HEAD = 0; |
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| 41 | reg_NUM_BANK_TAIL = 0; |
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[122] | 42 | reg_NUM_PTR_TAIL = 0; |
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[88] | 43 | |
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[100] | 44 | // Reset counter |
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[88] | 45 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 46 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 47 | { |
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[109] | 48 | _nb_cycle_idle [i][j] = 0; |
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| 49 | |
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[104] | 50 | reg_NB_INST_COMMIT_ALL [i][j] = 0; |
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| 51 | reg_NB_INST_COMMIT_MEM [i][j] = 0; |
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| 52 | |
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[122] | 53 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 54 | // reg_EVENT_FLUSH [i][j] = false; |
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[123] | 55 | // reg_EVENT_STOP [i][j] = false; |
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[128] | 56 | reg_EVENT_NUM_BANK [i][j] = 0; // not necessary |
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| 57 | reg_EVENT_NUM_PTR [i][j] = 0; // not necessary |
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| 58 | //reg_EVENT_CAN_RESTART [i][j] = 0; // not necessary |
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| 59 | reg_EVENT_PACKET [i][j] = 0; // not necessary |
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[124] | 60 | reg_EVENT_NB_INST [i][j] = 0; |
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[122] | 61 | reg_EVENT_LAST [i][j] = false; |
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[128] | 62 | reg_EVENT_LAST_NUM_BANK [i][j] = 0; // not necessary |
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| 63 | reg_EVENT_LAST_NUM_PTR [i][j] = 0; // not necessary |
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[100] | 64 | |
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[123] | 65 | reg_EVENT_NEXT_STOP [i][j] = false; |
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[128] | 66 | reg_EVENT_NEXT_PACKET [i][j] = 0; // not necessary |
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[123] | 67 | |
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[104] | 68 | // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; |
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| 69 | reg_PC_CURRENT [i][j] = (0x100 )>>2; |
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| 70 | reg_PC_CURRENT_IS_DS [i][j] = 0; |
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| 71 | reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; |
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[105] | 72 | reg_PC_NEXT [i][j] = (0x100+4)>>2; |
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[88] | 73 | } |
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| 74 | |
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[100] | 75 | // Reset priority algorithm |
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[88] | 76 | _priority_insert->reset(); |
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| 77 | } |
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| 78 | else |
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| 79 | { |
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[109] | 80 | // Increase number idle cycle |
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| 81 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 82 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 83 | _nb_cycle_idle [i][j] ++; |
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| 84 | |
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[100] | 85 | // Compute next priority |
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[88] | 86 | _priority_insert->transition(); |
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| 87 | |
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| 88 | // =================================================================== |
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[100] | 89 | // =====[ GARBAGE COLLECTOR ]========================================= |
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| 90 | // =================================================================== |
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| 91 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 92 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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[122] | 93 | { |
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| 94 | // Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty) |
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| 95 | // * no previous can_restart (trap for one) |
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| 96 | // * and decod_queue is empty |
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| 97 | // * and have an event or have a futur event |
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[123] | 98 | // if (not reg_EVENT_CAN_RESTART [i][j] and |
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| 99 | // (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and |
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| 100 | // (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT))) |
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| 101 | // reg_EVENT_CAN_RESTART [i][j] = true; |
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[122] | 102 | |
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| 103 | // Test event state |
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| 104 | switch (reg_EVENT_STATE [i][j]) |
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[104] | 105 | { |
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[122] | 106 | case COMMIT_EVENT_STATE_EVENT : |
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| 107 | { |
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| 108 | // Have an event, test if all composant have ack |
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| 109 | if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) |
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| 110 | { |
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| 111 | // A minor optimisation : test if wait_decod is previously empty. |
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[123] | 112 | // if (not reg_EVENT_CAN_RESTART [i][j]) |
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| 113 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD; |
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| 114 | // else |
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[122] | 115 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; |
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| 116 | } |
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| 117 | |
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| 118 | break; |
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| 119 | } |
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[123] | 120 | // case COMMIT_EVENT_STATE_WAIT_DECOD : |
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| 121 | // { |
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| 122 | // // Wait flush of decod_queue. |
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| 123 | // // Test if can restart now |
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| 124 | // if (reg_EVENT_CAN_RESTART [i][j]) |
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| 125 | // { |
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| 126 | // //reg_EVENT_FLUSH [i][j] = false; |
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[122] | 127 | |
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[123] | 128 | // // A minor optimisation : test if the last element is already retire |
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| 129 | // if (not reg_EVENT_LAST [i][j]) |
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| 130 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; |
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| 131 | // else |
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| 132 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END; |
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| 133 | // } |
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| 134 | // break; |
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| 135 | // } |
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[124] | 136 | |
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| 137 | // case COMMIT_EVENT_STATE_WAIT_END : |
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| 138 | // { |
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| 139 | // // Wait the flush of Re Order Buffer. |
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| 140 | // // Test if the last element is retire |
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| 141 | // if (reg_EVENT_LAST [i][j]) |
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| 142 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ; |
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| 143 | |
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| 144 | // break; |
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| 145 | // } |
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| 146 | // case COMMIT_EVENT_STATE_END : |
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| 147 | // { |
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| 148 | // // Just one cycle |
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| 149 | |
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| 150 | // // flush of re order buffer is finish |
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| 151 | // reg_EVENT_LAST [i][j] = false; |
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| 152 | |
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| 153 | // if (not reg_EVENT_NEXT_STOP [i][j]) |
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| 154 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 155 | // else |
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| 156 | // { |
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| 157 | // reg_EVENT_NEXT_STOP [i][j] = false; |
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| 158 | // reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j]; |
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| 159 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
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| 160 | // // reg_EVENT_STOP [i][j] = true; |
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| 161 | // reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
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| 162 | // reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL; |
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| 163 | // } |
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| 164 | |
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| 165 | // break; |
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| 166 | // } |
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| 167 | |
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| 168 | |
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[122] | 169 | case COMMIT_EVENT_STATE_WAIT_END : |
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| 170 | { |
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| 171 | // Wait the flush of Re Order Buffer. |
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| 172 | // Test if the last element is retire |
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| 173 | if (reg_EVENT_LAST [i][j]) |
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[124] | 174 | { |
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| 175 | // flush of re order buffer is finish |
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| 176 | reg_EVENT_LAST [i][j] = false; |
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| 177 | |
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| 178 | if (not reg_EVENT_NEXT_STOP [i][j]) |
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| 179 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 180 | else |
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| 181 | { |
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| 182 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
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[123] | 183 | |
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[124] | 184 | reg_EVENT_NEXT_STOP [i][j] = false; |
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| 185 | reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j]; |
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| 186 | reg_EVENT_NB_INST [i][j] = reg_NB_INST_COMMIT_ALL [i][j]; |
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| 187 | //reg_EVENT_STOP [i][j] = true; |
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| 188 | reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
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| 189 | reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL; |
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| 190 | } |
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[123] | 191 | } |
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[122] | 192 | break; |
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| 193 | } |
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[124] | 194 | |
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[122] | 195 | //case COMMIT_EVENT_STATE_NO_EVENT : |
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[123] | 196 | //case COMMIT_EVENT_STATE_NOT_YET_EVENT : |
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[122] | 197 | default : break; |
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[104] | 198 | } |
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[122] | 199 | } |
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[100] | 200 | |
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| 201 | // =================================================================== |
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[88] | 202 | // =====[ INSERT ]==================================================== |
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| 203 | // =================================================================== |
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[122] | 204 | { |
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[124] | 205 | // for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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| 206 | // for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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| 207 | // log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL [%d][%d] : %d",i,j,PORT_READ(in_INSERT_VAL [i][j])); |
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| 208 | |
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[122] | 209 | // variable to count instruction insert |
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| 210 | uint32_t nb_insert = 0; |
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[124] | 211 | |
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[122] | 212 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 213 | { |
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| 214 | // compute first bank number |
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| 215 | uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; |
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| 216 | |
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| 217 | if (internal_BANK_INSERT_VAL [num_bank]) |
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| 218 | { |
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| 219 | // get rename unit source and instruction. |
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| 220 | uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank]; |
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| 221 | uint32_t y = internal_BANK_INSERT_NUM_INST [num_bank]; |
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| 222 | |
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| 223 | // Test if an instruction is valid |
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| 224 | // (all in_order insert combinatory is in rename_unit ) |
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| 225 | if (PORT_READ(in_INSERT_VAL [x][y])) |
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| 226 | { |
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| 227 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); |
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| 228 | |
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| 229 | // get information |
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| 230 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; |
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| 231 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; |
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| 232 | Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); |
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| 233 | Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); |
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| 234 | bool is_store = is_operation_memory_store(operation); |
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| 235 | |
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| 236 | Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); |
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| 237 | Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); |
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| 238 | |
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| 239 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 240 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
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| 241 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
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| 242 | log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); |
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| 243 | log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); |
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| 244 | |
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| 245 | // Create new entry and write information |
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| 246 | entry_t * entry = new entry_t; |
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| 247 | uint32_t ptr = reg_BANK_PTR [num_bank]; |
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[88] | 248 | |
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[122] | 249 | entry->ptr = ptr; |
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| 250 | entry->front_end_id = front_end_id; |
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| 251 | entry->context_id = context_id ; |
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| 252 | entry->rename_unit_id = x; |
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| 253 | entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; |
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[137] | 254 | #ifdef STATISTICS |
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| 255 | entry->instruction = PORT_READ(in_INSERT_INSTRUCTION [x][y]); |
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| 256 | #endif |
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[122] | 257 | entry->type = type; |
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| 258 | entry->operation = operation; |
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| 259 | entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); |
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| 260 | // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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| 261 | entry->exception = exception; |
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| 262 | entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); |
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| 263 | entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute); |
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| 264 | entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute); |
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| 265 | entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); |
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| 266 | entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; |
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| 267 | #ifdef DEBUG |
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| 268 | entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); |
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| 269 | entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); |
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| 270 | entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); |
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[137] | 271 | #endif |
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[122] | 272 | entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); |
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[137] | 273 | #ifdef DEBUG |
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[122] | 274 | entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); |
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| 275 | entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); |
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| 276 | entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); |
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| 277 | entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); |
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| 278 | entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); |
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| 279 | #endif |
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| 280 | entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); |
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| 281 | entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); |
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| 282 | entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); |
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| 283 | entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); |
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| 284 | entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); |
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| 285 | entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); |
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| 286 | entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); |
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| 287 | entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); |
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[128] | 288 | |
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| 289 | entry->flags = 0; // not necessary |
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[122] | 290 | entry->no_sequence = type == TYPE_BRANCH; |
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[124] | 291 | // entry->speculative = true; |
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[122] | 292 | #ifdef DEBUG |
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| 293 | entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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| 294 | #endif |
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| 295 | entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); |
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| 296 | #ifdef DEBUG |
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| 297 | entry->cycle_rob_in = simulation_cycle(); |
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| 298 | entry->cycle_commit = simulation_cycle(); |
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| 299 | #endif |
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| 300 | |
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| 301 | // Test if exception : |
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| 302 | // * yes : no execute instruction, wait ROB Head |
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| 303 | // * no : test if no_execute (== instruction is flushed) |
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| 304 | // else test type |
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| 305 | // * BRANCH : l.j -> branch is ended |
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| 306 | // other -> wait the execution end of branchment |
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| 307 | // * MEMORY : store -> wait store is at head of ROB |
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| 308 | // other -> wait end of instruction |
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| 309 | // * OTHER |
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| 310 | |
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| 311 | { |
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| 312 | if (exception == EXCEPTION_NONE) |
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| 313 | { |
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| 314 | // no_execute : l.j, l.nop, l.rfe |
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| 315 | |
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| 316 | log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); |
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| 317 | |
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| 318 | switch (type) |
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| 319 | { |
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| 320 | case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} |
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| 321 | case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;} |
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| 322 | default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} |
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| 323 | } |
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| 324 | } |
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| 325 | else |
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| 326 | { |
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| 327 | // Have an exception : wait head of ROB |
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| 328 | // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap |
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| 329 | |
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| 330 | entry->state = ROB_END_EXCEPTION_WAIT_HEAD; |
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| 331 | } |
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| 332 | } |
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[100] | 333 | |
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[122] | 334 | #ifdef STATISTICS |
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| 335 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 336 | (*_stat_nb_inst_insert [x]) ++; |
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[121] | 337 | #endif |
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[122] | 338 | |
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| 339 | // Push entry in rob |
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| 340 | _rob[num_bank].push_back(entry); |
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| 341 | |
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| 342 | // Update counter and pointer |
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| 343 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; |
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| 344 | if (type == TYPE_MEMORY) |
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| 345 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; |
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| 346 | |
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[88] | 347 | |
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[122] | 348 | // flush = present event or future event. |
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| 349 | // * present event = don't can restart |
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[88] | 350 | |
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[122] | 351 | // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
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[88] | 352 | |
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[122] | 353 | // bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
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| 354 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or |
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| 355 | // (reg_EVENT_STOP [front_end_id][context_id])); |
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| 356 | |
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| 357 | // New instruction from decod_queue. Flush if : |
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| 358 | // * future event (instruction don't need execute because they are a previous event (miss load/branch or exception)) |
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| 359 | // * or present_event |
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| 360 | // * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured. |
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[123] | 361 | // bool flush = ((// present event |
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| 362 | // ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
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| 363 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) |
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| 364 | // ) or |
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| 365 | // futur event |
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| 366 | // reg_EVENT_STOP [front_end_id][context_id]) |
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| 367 | // // can't restart |
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| 368 | // and not reg_EVENT_CAN_RESTART[front_end_id][context_id] |
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| 369 | // ); |
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[100] | 370 | |
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[123] | 371 | // if (flush) |
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| 372 | // { |
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| 373 | // // A new invalid instruction is push in rob -> new last instruction |
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| 374 | // reg_EVENT_LAST [front_end_id][context_id] = false; |
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| 375 | // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank; |
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| 376 | // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr; |
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| 377 | // } |
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[122] | 378 | |
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| 379 | // Update pointer |
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| 380 | reg_NUM_PTR_TAIL = ptr; |
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| 381 | reg_BANK_PTR [num_bank] = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank; |
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| 382 | nb_insert ++; |
---|
[108] | 383 | } |
---|
[122] | 384 | } |
---|
| 385 | } |
---|
| 386 | // Update pointer |
---|
| 387 | reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank; |
---|
| 388 | } |
---|
[88] | 389 | |
---|
| 390 | // =================================================================== |
---|
| 391 | // =====[ COMMIT ]==================================================== |
---|
| 392 | // =================================================================== |
---|
| 393 | |
---|
| 394 | #ifdef STATISTICS |
---|
| 395 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 396 | (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; |
---|
| 397 | #endif |
---|
| 398 | |
---|
[122] | 399 | // For each commit instruction ... |
---|
[88] | 400 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 401 | for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) |
---|
[122] | 402 | // ... test if an instruction have finish this execution |
---|
[88] | 403 | if (internal_BANK_COMMIT_VAL [i][j]) |
---|
| 404 | { |
---|
[122] | 405 | // An instruction is executed -> Change state of this instruction |
---|
[100] | 406 | |
---|
[122] | 407 | // Get information |
---|
[88] | 408 | uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; |
---|
| 409 | |
---|
[122] | 410 | // Test if instruction is valid and is enable |
---|
| 411 | // (can be disable if this instruction is reexecute) |
---|
[88] | 412 | if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) |
---|
| 413 | { |
---|
| 414 | log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); |
---|
| 415 | |
---|
| 416 | #ifdef STATISTICS |
---|
| 417 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 418 | (*_stat_nb_inst_commit) ++; |
---|
| 419 | #endif |
---|
| 420 | |
---|
[124] | 421 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); |
---|
[88] | 422 | |
---|
| 423 | // find the good entry !!! |
---|
[100] | 424 | entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; |
---|
[123] | 425 | |
---|
[124] | 426 | log_printf(TRACE,Commit_unit,FUNCTION," * ptr : %d",entry->ptr); |
---|
[100] | 427 | |
---|
| 428 | //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); |
---|
[122] | 429 | Ttype_t type = entry->type; |
---|
| 430 | Tcontrol_t no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); |
---|
[136] | 431 | // Tcontrol_t cancel = PORT_READ(in_COMMIT_CANCEL [x]); |
---|
[122] | 432 | |
---|
| 433 | #if 0 |
---|
| 434 | if ((type == TYPE_MEMORY) and no_sequence) |
---|
| 435 | continue; |
---|
| 436 | #endif |
---|
| 437 | |
---|
[100] | 438 | Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); |
---|
[88] | 439 | |
---|
[100] | 440 | rob_state_t state = entry->state; |
---|
| 441 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 442 | Tcontext_t context_id = entry->context_id; |
---|
[88] | 443 | |
---|
[100] | 444 | // change state : test exception_use |
---|
[88] | 445 | |
---|
[100] | 446 | bool have_exception = false; |
---|
| 447 | bool have_miss_speculation = false; |
---|
| 448 | |
---|
[122] | 449 | // Test if have an exception ... |
---|
[88] | 450 | if (exception != EXCEPTION_NONE) |
---|
[100] | 451 | { |
---|
[122] | 452 | // Test if the instruction is a load and is a miss speculation |
---|
| 453 | // (load is commit, but they have an dependence with a previous store -> need restart pipeline) |
---|
| 454 | |
---|
[100] | 455 | have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
[88] | 456 | |
---|
[122] | 457 | // * Test if the exception generated can be trap by this exception |
---|
[100] | 458 | switch (entry->exception_use) |
---|
| 459 | { |
---|
| 460 | // Have overflow exception if bit overflow enable is set. |
---|
| 461 | case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} |
---|
| 462 | case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
---|
| 463 | (exception == EXCEPTION_DATA_TLB ) or |
---|
| 464 | (exception == EXCEPTION_DATA_PAGE) or |
---|
| 465 | (exception == EXCEPTION_ALIGNMENT)); break;}; |
---|
| 466 | case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
---|
| 467 | (exception == EXCEPTION_DATA_TLB ) or |
---|
| 468 | (exception == EXCEPTION_DATA_PAGE)); break;}; |
---|
| 469 | case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; |
---|
| 470 | case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; |
---|
| 471 | case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; |
---|
| 472 | case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; |
---|
| 473 | case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; |
---|
| 474 | case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; |
---|
| 475 | case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; |
---|
| 476 | // Case already manage (decod stage -> in insert in ROB) |
---|
| 477 | case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 478 | case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 479 | case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 480 | case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 481 | default : |
---|
| 482 | { |
---|
| 483 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); |
---|
| 484 | break; |
---|
| 485 | } |
---|
| 486 | } |
---|
| 487 | } |
---|
[124] | 488 | |
---|
| 489 | log_printf(TRACE,Commit_unit,FUNCTION," * have_exception : %d",have_exception ); |
---|
| 490 | log_printf(TRACE,Commit_unit,FUNCTION," * have_miss_speculation : %d",have_miss_speculation); |
---|
| 491 | |
---|
[100] | 492 | |
---|
[122] | 493 | // Next state depends of previous state |
---|
[100] | 494 | switch (state) |
---|
| 495 | { |
---|
[122] | 496 | // Branch : if no exception, the branchement can be completed |
---|
| 497 | case ROB_BRANCH_WAIT_END : |
---|
| 498 | { |
---|
| 499 | if (not have_exception) |
---|
| 500 | state = ROB_BRANCH_COMPLETE; |
---|
| 501 | else |
---|
| 502 | state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 503 | break; |
---|
| 504 | } |
---|
| 505 | // Previous event -> set state as execute |
---|
| 506 | case ROB_STORE_KO_WAIT_END : |
---|
| 507 | case ROB_EVENT_WAIT_END : |
---|
| 508 | { |
---|
| 509 | state = ROB_END_KO_SPECULATIVE; |
---|
| 510 | break; |
---|
| 511 | } |
---|
| 512 | // No previous event - Load and other instruction |
---|
| 513 | case ROB_STORE_OK_WAIT_END : |
---|
| 514 | case ROB_OTHER_WAIT_END : |
---|
| 515 | { |
---|
| 516 | if (not have_exception) |
---|
| 517 | { |
---|
| 518 | if (not have_miss_speculation) |
---|
| 519 | state = ROB_END_OK_SPECULATIVE; |
---|
| 520 | else |
---|
| 521 | state = ROB_END_LOAD_MISS_SPECULATIVE; |
---|
| 522 | } |
---|
| 523 | else |
---|
| 524 | state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 525 | break; |
---|
| 526 | } |
---|
| 527 | case ROB_STORE_WAIT_END_OK : |
---|
| 528 | { |
---|
| 529 | if (not have_exception) |
---|
| 530 | state = ROB_STORE_OK; |
---|
| 531 | else |
---|
| 532 | state = ROB_STORE_EVENT; |
---|
| 533 | break; |
---|
| 534 | } |
---|
| 535 | case ROB_STORE_WAIT_END_KO : |
---|
| 536 | { |
---|
| 537 | // if (not have_exception) |
---|
| 538 | state = ROB_STORE_KO; |
---|
| 539 | // else |
---|
| 540 | // state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 541 | break; |
---|
| 542 | } |
---|
| 543 | |
---|
| 544 | |
---|
[100] | 545 | default : |
---|
| 546 | { |
---|
[115] | 547 | throw ERRORMORPHEO(FUNCTION,toString(_("Commit [%d] : Bank [%d][%d], invalid state value (%s).\n"),x,i,j,toString(state).c_str())); |
---|
[100] | 548 | break; |
---|
| 549 | } |
---|
| 550 | } |
---|
[88] | 551 | |
---|
[122] | 552 | // Commit an instruction ... |
---|
[123] | 553 | // Test if have an event (miss_speculation or exception) |
---|
[112] | 554 | |
---|
[123] | 555 | if (have_exception or have_miss_speculation) |
---|
[122] | 556 | { |
---|
[123] | 557 | // Two case : |
---|
| 558 | // if no previous manage event -> generate an event |
---|
| 559 | // if previous manage event -> next generate an event |
---|
| 560 | |
---|
| 561 | // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
---|
| 562 | bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
| 563 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or |
---|
[124] | 564 | (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)// or |
---|
| 565 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_END) |
---|
[123] | 566 | ); |
---|
| 567 | |
---|
[122] | 568 | uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i); |
---|
[123] | 569 | uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); |
---|
[124] | 570 | |
---|
| 571 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
| 572 | log_printf(TRACE,Commit_unit,FUNCTION," * packet : %d",packet); |
---|
[123] | 573 | |
---|
| 574 | if (not flush) |
---|
[122] | 575 | { |
---|
[123] | 576 | bool can = true; |
---|
| 577 | // test have a previous event detected (event_stop = 1) |
---|
| 578 | // if yes, test if the actual event if "before (in order)" that the previous event |
---|
| 579 | if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) |
---|
| 580 | { |
---|
| 581 | // Compare packet_id (by construction instruction is insert in order by increase packet_id) |
---|
| 582 | |
---|
| 583 | uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id]; |
---|
| 584 | uint32_t _new = packet; |
---|
| 585 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 586 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 587 | if (_new < _old) reg_EVENT_PACKET [front_end_id][context_id] = packet; |
---|
| 588 | else can = false; |
---|
| 589 | } |
---|
| 590 | else |
---|
| 591 | reg_EVENT_PACKET [front_end_id][context_id] = packet; |
---|
| 592 | |
---|
| 593 | if (can) |
---|
| 594 | { |
---|
| 595 | // have an error, stop issue instruction |
---|
| 596 | reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
---|
[124] | 597 | |
---|
| 598 | reg_EVENT_NB_INST [front_end_id][context_id] = reg_NB_INST_COMMIT_ALL [front_end_id][context_id]; |
---|
| 599 | |
---|
| 600 | //reg_EVENT_STOP [front_end_id][context_id] = true; |
---|
[123] | 601 | |
---|
| 602 | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 603 | reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; |
---|
| 604 | } |
---|
[122] | 605 | } |
---|
| 606 | else |
---|
[123] | 607 | { |
---|
| 608 | bool find = true; |
---|
[122] | 609 | |
---|
[124] | 610 | log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_STOP : %d",reg_EVENT_NEXT_STOP [front_end_id][context_id]); |
---|
| 611 | log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_PACKET : %d",reg_EVENT_NEXT_PACKET[front_end_id][context_id]); |
---|
| 612 | |
---|
[123] | 613 | // already manage an event. |
---|
| 614 | if (reg_EVENT_NEXT_STOP [front_end_id][context_id]) |
---|
| 615 | { |
---|
| 616 | // after last ? |
---|
| 617 | uint32_t _old = reg_EVENT_NEXT_PACKET [front_end_id][context_id]; |
---|
| 618 | uint32_t _new = packet; |
---|
[124] | 619 | |
---|
| 620 | log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top ); |
---|
| 621 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old ); |
---|
| 622 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new ); |
---|
| 623 | |
---|
[123] | 624 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 625 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 626 | if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; |
---|
[124] | 627 | else find = false; |
---|
| 628 | |
---|
| 629 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old ); |
---|
| 630 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new ); |
---|
[123] | 631 | } |
---|
| 632 | else |
---|
| 633 | { |
---|
| 634 | // after last ? |
---|
| 635 | uint32_t _old = ((reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id]); |
---|
| 636 | uint32_t _new = packet; |
---|
[124] | 637 | |
---|
| 638 | log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top ); |
---|
| 639 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old ); |
---|
| 640 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new ); |
---|
| 641 | |
---|
[123] | 642 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 643 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 644 | if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; |
---|
[124] | 645 | else find = false; |
---|
| 646 | |
---|
| 647 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old ); |
---|
| 648 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new ); |
---|
[123] | 649 | } |
---|
| 650 | |
---|
[124] | 651 | log_printf(TRACE,Commit_unit,FUNCTION," * find : %d",find); |
---|
| 652 | |
---|
[123] | 653 | if (find) |
---|
| 654 | reg_EVENT_NEXT_STOP [front_end_id][context_id] = true; // in all case : need stop |
---|
| 655 | } |
---|
[122] | 656 | } |
---|
[123] | 657 | |
---|
[122] | 658 | // Update Re Order Buffer |
---|
[105] | 659 | entry->state = state; |
---|
| 660 | entry->exception = exception; |
---|
| 661 | entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); |
---|
[122] | 662 | entry->no_sequence = no_sequence; |
---|
[105] | 663 | // jalr, jr : address_dest is in register |
---|
[122] | 664 | if (( type == TYPE_BRANCH) and |
---|
[105] | 665 | (entry->operation == OPERATION_BRANCH_L_JALR) and |
---|
| 666 | (entry->read_rb)) |
---|
| 667 | entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]); |
---|
[111] | 668 | |
---|
| 669 | #ifdef DEBUG |
---|
[122] | 670 | entry->load_data = PORT_READ(in_COMMIT_ADDRESS [x]); |
---|
| 671 | entry->cycle_commit = simulation_cycle(); |
---|
[111] | 672 | #endif |
---|
[88] | 673 | } |
---|
| 674 | } |
---|
| 675 | |
---|
| 676 | // =================================================================== |
---|
| 677 | // =====[ RETIRE ]==================================================== |
---|
| 678 | // =================================================================== |
---|
| 679 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[110] | 680 | { |
---|
[122] | 681 | // Compute bank number |
---|
[110] | 682 | uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; |
---|
| 683 | |
---|
[122] | 684 | // Test if have an request |
---|
[110] | 685 | if (internal_BANK_RETIRE_VAL [num_bank]) |
---|
| 686 | { |
---|
[122] | 687 | // Take num instruction |
---|
[110] | 688 | uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank]; |
---|
| 689 | uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank]; |
---|
| 690 | |
---|
| 691 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); |
---|
[112] | 692 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank ); |
---|
[110] | 693 | |
---|
[88] | 694 | #ifdef DEBUG_TEST |
---|
[110] | 695 | if (not PORT_READ(in_RETIRE_ACK [x][y])) |
---|
| 696 | throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); |
---|
[88] | 697 | #endif |
---|
| 698 | |
---|
| 699 | |
---|
[122] | 700 | #ifdef STATISTICS |
---|
| 701 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 702 | (*_stat_nb_inst_retire [x]) ++; |
---|
[110] | 703 | |
---|
[111] | 704 | #endif |
---|
[110] | 705 | |
---|
[122] | 706 | // Read information |
---|
| 707 | entry_t * entry = _rob [num_bank].front(); |
---|
[105] | 708 | |
---|
[122] | 709 | entry->state_old = entry->state; |
---|
| 710 | entry->state = ROB_END; |
---|
[110] | 711 | } |
---|
| 712 | } |
---|
[109] | 713 | |
---|
[122] | 714 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[88] | 715 | { |
---|
[122] | 716 | // Compute bank number |
---|
| 717 | bool can_continue = false; |
---|
| 718 | uint32_t num_bank = reg_NUM_BANK_HEAD; |
---|
| 719 | |
---|
| 720 | if (not _rob [num_bank].empty ()) |
---|
| 721 | { |
---|
| 722 | entry_t * entry = _rob [num_bank].front(); |
---|
| 723 | |
---|
| 724 | if (entry->state == ROB_END) |
---|
| 725 | { |
---|
| 726 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ROB [%d]",num_bank); |
---|
| 727 | |
---|
| 728 | can_continue = true; |
---|
[101] | 729 | |
---|
[122] | 730 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 731 | Tcontext_t context_id = entry->context_id ; |
---|
| 732 | uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id]; |
---|
| 733 | rob_state_t state = entry->state_old; |
---|
| 734 | Ttype_t type = entry->type ; |
---|
| 735 | bool retire_ok = false; |
---|
| 736 | uint32_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
| 737 | |
---|
| 738 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); |
---|
| 739 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); |
---|
| 740 | log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",packet_id ); |
---|
| 741 | log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); |
---|
| 742 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
---|
| 743 | log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); |
---|
| 744 | |
---|
| 745 | // Test if the instruction is valid |
---|
| 746 | // (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction) |
---|
| 747 | // (LOAD_MISS = instruction load is valid, but have make an invalid result) |
---|
| 748 | if ((state == ROB_END_OK ) or |
---|
| 749 | // (state == ROB_END_KO ) or |
---|
| 750 | (state == ROB_END_BRANCH_MISS) or |
---|
| 751 | (state == ROB_END_LOAD_MISS )// or |
---|
| 752 | // (state == ROB_END_MISS ) or |
---|
| 753 | // (state == ROB_END_EXCEPTION ) |
---|
| 754 | ) |
---|
| 755 | { |
---|
| 756 | log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok"); |
---|
| 757 | |
---|
| 758 | retire_ok = true; |
---|
| 759 | |
---|
| 760 | // Update PC information |
---|
| 761 | // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; |
---|
| 762 | reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; |
---|
| 763 | reg_PC_CURRENT_IS_DS [front_end_id][context_id] = type == TYPE_BRANCH; |
---|
| 764 | reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; |
---|
| 765 | reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); |
---|
| 766 | } |
---|
| 767 | |
---|
| 768 | // Test if have an event |
---|
| 769 | if ((state == ROB_END_BRANCH_MISS) or |
---|
| 770 | (state == ROB_END_LOAD_MISS)) |
---|
| 771 | { |
---|
| 772 | reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT; |
---|
[123] | 773 | // reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue |
---|
[122] | 774 | reg_EVENT_LAST [front_end_id][context_id] = false; |
---|
| 775 | // it the head ! |
---|
| 776 | reg_EVENT_PACKET [front_end_id][context_id] = packet_id; |
---|
| 777 | |
---|
[123] | 778 | // // If event is an load_miss, many instruction can be inserted. |
---|
| 779 | // // -> new last instruction |
---|
| 780 | // if (state == ROB_END_LOAD_MISS) |
---|
| 781 | // { |
---|
| 782 | // // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false; |
---|
[122] | 783 | |
---|
[123] | 784 | // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 785 | // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; |
---|
| 786 | // } |
---|
[122] | 787 | } |
---|
| 788 | |
---|
| 789 | // Test if this instruction is the last instruction of an event |
---|
| 790 | // * need event |
---|
| 791 | // * packet id = last packet id |
---|
[124] | 792 | // for (uint32_t x=0; x<_param->_nb_front_end; x++) |
---|
| 793 | // for (uint32_t y=0; y<_param->_nb_context [x]; y++) |
---|
| 794 | // if (((reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NO_EVENT ) and |
---|
| 795 | // (reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and |
---|
| 796 | // (reg_EVENT_LAST_NUM_BANK [x][y] == num_bank ) and |
---|
| 797 | // (reg_EVENT_LAST_NUM_PTR [x][y] == entry->ptr )) |
---|
| 798 | // reg_EVENT_LAST [x][y] = true; |
---|
| 799 | |
---|
| 800 | |
---|
| 801 | if (reg_EVENT_NB_INST [front_end_id][context_id] > 0) |
---|
| 802 | { |
---|
| 803 | reg_EVENT_NB_INST [front_end_id][context_id] --; |
---|
| 804 | if (reg_EVENT_NB_INST [front_end_id][context_id] == 0) |
---|
| 805 | reg_EVENT_LAST [front_end_id][context_id] = true; |
---|
| 806 | } |
---|
| 807 | |
---|
[122] | 808 | // Update nb_inst |
---|
| 809 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; |
---|
| 810 | if (type == TYPE_MEMORY) |
---|
| 811 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; |
---|
| 812 | |
---|
| 813 | // Update pointer |
---|
| 814 | reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank; |
---|
| 815 | |
---|
| 816 | // Reset watch dog timer because have transaction on retire interface |
---|
| 817 | _nb_cycle_idle [front_end_id][context_id] = 0; |
---|
| 818 | |
---|
| 819 | // Increase stop condition |
---|
| 820 | if (retire_ok) |
---|
| 821 | _simulation_nb_instruction_commited [num_thread] ++; |
---|
[88] | 822 | |
---|
[122] | 823 | #ifdef STATISTICS |
---|
| 824 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 825 | { |
---|
| 826 | if (retire_ok) |
---|
| 827 | { |
---|
[137] | 828 | uint32_t instruction = entry->instruction; |
---|
| 829 | |
---|
| 830 | (*_stat_nb_inst_retire_ok [num_thread] ) ++; |
---|
| 831 | (*_stat_nb_inst_instruction [instruction]) ++; |
---|
| 832 | (*_stat_nb_inst_type [type] ) ++; |
---|
[122] | 833 | } |
---|
| 834 | else |
---|
| 835 | (*_stat_nb_inst_retire_ko [num_thread]) ++; |
---|
| 836 | } |
---|
| 837 | #endif |
---|
[88] | 838 | |
---|
[122] | 839 | #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) |
---|
[134] | 840 | if (log_file_generate) |
---|
| 841 | { |
---|
| 842 | // log file |
---|
| 843 | instruction_log_file [num_thread] |
---|
| 844 | << "[" << simulation_cycle() << "] " |
---|
| 845 | << std::hex |
---|
| 846 | << (entry->address<<2) << " (" << (entry->address) << ") " |
---|
| 847 | << std::dec |
---|
| 848 | << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] " |
---|
| 849 | << "{" << ((retire_ok)?"OK":"KO") << "} "; |
---|
| 850 | |
---|
| 851 | if ((type == TYPE_MEMORY) and is_operation_memory_load(entry->operation)) |
---|
| 852 | instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec; |
---|
| 853 | |
---|
| 854 | instruction_log_file [num_thread] << std::endl; |
---|
| 855 | } |
---|
[122] | 856 | #endif |
---|
[123] | 857 | |
---|
| 858 | // Remove entry |
---|
| 859 | delete entry; |
---|
| 860 | _rob [num_bank].pop_front(); |
---|
[122] | 861 | } |
---|
[88] | 862 | } |
---|
[122] | 863 | |
---|
| 864 | if (not can_continue) |
---|
| 865 | break; // stop scan |
---|
[88] | 866 | } |
---|
| 867 | |
---|
| 868 | // =================================================================== |
---|
[122] | 869 | // =====[ REEXECUTE ]================================================= |
---|
| 870 | // =================================================================== |
---|
| 871 | // Test if have an reexecute instruction (an store in head of rob) |
---|
| 872 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) |
---|
| 873 | if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i])) |
---|
| 874 | { |
---|
| 875 | log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [%d]",i); |
---|
| 876 | |
---|
| 877 | uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i]; |
---|
| 878 | |
---|
| 879 | entry_t * entry = _rob [num_bank].front(); |
---|
| 880 | rob_state_t state = entry->state; |
---|
| 881 | |
---|
| 882 | // Change state |
---|
| 883 | switch (state) |
---|
| 884 | { |
---|
| 885 | case ROB_STORE_OK : {state = ROB_STORE_OK_WAIT_END; break; } |
---|
| 886 | case ROB_STORE_KO : {state = ROB_STORE_KO_WAIT_END; break; } |
---|
| 887 | case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; } |
---|
| 888 | default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} |
---|
| 889 | } |
---|
| 890 | |
---|
| 891 | entry->state = state; |
---|
| 892 | } |
---|
| 893 | |
---|
| 894 | // =================================================================== |
---|
[88] | 895 | // =====[ BRANCH_COMPLETE ]=========================================== |
---|
| 896 | // =================================================================== |
---|
| 897 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
---|
[122] | 898 | // Test if the prediction_unit have accept the branch complete transaction |
---|
[88] | 899 | if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) |
---|
| 900 | { |
---|
[101] | 901 | log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
---|
| 902 | |
---|
[122] | 903 | // Read information |
---|
[88] | 904 | uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; |
---|
| 905 | |
---|
| 906 | entry_t * entry = _rob [num_bank].front(); |
---|
| 907 | |
---|
| 908 | #ifdef DEBUG_TEST |
---|
| 909 | rob_state_t state = entry->state; |
---|
| 910 | if (state != ROB_BRANCH_COMPLETE) |
---|
| 911 | throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); |
---|
| 912 | #endif |
---|
[112] | 913 | Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]); |
---|
[122] | 914 | |
---|
| 915 | log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",miss); |
---|
[112] | 916 | |
---|
| 917 | entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; |
---|
[88] | 918 | |
---|
[122] | 919 | // bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id]; |
---|
[112] | 920 | |
---|
[122] | 921 | // Branch_complete can be execute if |
---|
| 922 | // * no present event |
---|
| 923 | // * futur event and most not speculative that the event |
---|
| 924 | |
---|
| 925 | // Also, test if in this cycle, they have not an most recently event !!! |
---|
| 926 | if (miss) |
---|
| 927 | { |
---|
[123] | 928 | bool can = true; |
---|
[122] | 929 | uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
| 930 | |
---|
| 931 | // test if this packet is before previous event |
---|
[123] | 932 | if (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) |
---|
[122] | 933 | { |
---|
| 934 | uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); |
---|
| 935 | uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id]; |
---|
| 936 | uint32_t _new = packet; |
---|
| 937 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 938 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 939 | if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; |
---|
[123] | 940 | else can = false; |
---|
[122] | 941 | } |
---|
| 942 | else |
---|
| 943 | reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; |
---|
| 944 | |
---|
[123] | 945 | if (can) |
---|
| 946 | { |
---|
| 947 | // In all case, stop instruction flow |
---|
| 948 | reg_EVENT_STATE [entry->front_end_id][entry->context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
---|
[124] | 949 | reg_EVENT_NB_INST [entry->front_end_id][entry->context_id] = reg_NB_INST_COMMIT_ALL [entry->front_end_id][entry->context_id]; |
---|
| 950 | |
---|
[123] | 951 | // reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; |
---|
[122] | 952 | |
---|
[123] | 953 | // reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; |
---|
[122] | 954 | |
---|
[123] | 955 | reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 956 | reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; |
---|
| 957 | } |
---|
[122] | 958 | } |
---|
[88] | 959 | } |
---|
| 960 | |
---|
| 961 | // =================================================================== |
---|
[100] | 962 | // =====[ UPDATE ]==================================================== |
---|
| 963 | // =================================================================== |
---|
[122] | 964 | // Update when exception or load_miss |
---|
[105] | 965 | if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) |
---|
| 966 | { |
---|
| 967 | log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); |
---|
[100] | 968 | |
---|
[122] | 969 | // Change state |
---|
[105] | 970 | entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); |
---|
| 971 | |
---|
| 972 | switch (entry->state) |
---|
| 973 | { |
---|
| 974 | // case ROB_END_EXCEPTION_UPDATE : |
---|
| 975 | // { |
---|
| 976 | // entry->state = ROB_END_KO; |
---|
| 977 | // throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); |
---|
| 978 | // break; |
---|
| 979 | // } |
---|
| 980 | case ROB_END_LOAD_MISS_UPDATE : |
---|
| 981 | { |
---|
| 982 | log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); |
---|
| 983 | |
---|
| 984 | entry->state = ROB_END_LOAD_MISS; |
---|
| 985 | break; |
---|
| 986 | } |
---|
| 987 | default : |
---|
| 988 | { |
---|
| 989 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n")); |
---|
| 990 | break; |
---|
| 991 | } |
---|
| 992 | } |
---|
| 993 | } |
---|
| 994 | |
---|
[100] | 995 | // =================================================================== |
---|
[88] | 996 | // =====[ EVENT ]===================================================== |
---|
| 997 | // =================================================================== |
---|
[108] | 998 | // for (uint32_t i=0; i < _param->_nb_front_end; ++i) |
---|
| 999 | // for (uint32_t j=0; j < _param->_nb_context[i]; ++j) |
---|
| 1000 | // if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j]) |
---|
| 1001 | // { |
---|
| 1002 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j); |
---|
[88] | 1003 | |
---|
[108] | 1004 | // reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]); |
---|
| 1005 | // reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ?? |
---|
| 1006 | // reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); |
---|
| 1007 | // reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]); |
---|
| 1008 | // // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]); |
---|
| 1009 | // } |
---|
| 1010 | |
---|
[88] | 1011 | // =================================================================== |
---|
| 1012 | // =====[ DEPTH - HEAD ]============================================== |
---|
| 1013 | // =================================================================== |
---|
| 1014 | |
---|
[122] | 1015 | { |
---|
[124] | 1016 | bool can_continue [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1017 | uint32_t event_nb_inst [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1018 | bool is_speculative [_param->_nb_front_end][_param->_max_nb_context]; |
---|
[122] | 1019 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1020 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
[124] | 1021 | { |
---|
| 1022 | event_nb_inst [i][j] = 0; |
---|
| 1023 | is_speculative[i][j] = false; |
---|
| 1024 | can_continue [i][j] = (((reg_EVENT_NB_INST [i][j] == 0) or |
---|
| 1025 | ( event_nb_inst [i][j] < reg_EVENT_NB_INST [i][j])) and |
---|
| 1026 | not reg_EVENT_LAST [i][j]); |
---|
| 1027 | } |
---|
[122] | 1028 | |
---|
| 1029 | // Read all instruction of all top bank |
---|
| 1030 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 1031 | { |
---|
| 1032 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
[88] | 1033 | |
---|
[122] | 1034 | // Test if have an instruction |
---|
| 1035 | if (not _rob[num_bank].empty()) |
---|
| 1036 | { |
---|
| 1037 | // Scan all instruction in windows and test if instruction is speculative |
---|
| 1038 | entry_t * entry = _rob [num_bank].front(); |
---|
[124] | 1039 | |
---|
| 1040 | uint32_t num_packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
[122] | 1041 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 1042 | Tcontext_t context_id = entry->context_id ; |
---|
[124] | 1043 | |
---|
| 1044 | log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d] - %d",num_bank,num_packet); |
---|
| 1045 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
---|
| 1046 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
---|
| 1047 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d",reg_EVENT_LAST [front_end_id][context_id]); |
---|
| 1048 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NB_INST : %d",reg_EVENT_NB_INST [front_end_id][context_id]); |
---|
| 1049 | log_printf(TRACE,Commit_unit,FUNCTION," * event_nb_inst : %d", event_nb_inst [front_end_id][context_id]); |
---|
[122] | 1050 | |
---|
| 1051 | // scan while last event instruction is not retire |
---|
[124] | 1052 | if (can_continue [front_end_id][context_id]) |
---|
[122] | 1053 | { |
---|
| 1054 | // Read information |
---|
| 1055 | rob_state_t state = entry->state; |
---|
[137] | 1056 | // Tdepth_t depth = entry->depth; |
---|
[122] | 1057 | |
---|
[137] | 1058 | // Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; |
---|
| 1059 | // Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; |
---|
| 1060 | // Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); |
---|
[122] | 1061 | |
---|
| 1062 | // is a valid instruction ? |
---|
| 1063 | // If DEPTH_CURRENT : |
---|
| 1064 | // equal at DEPTH_MIN -> not speculative |
---|
| 1065 | // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss |
---|
| 1066 | // include ]DEPTH_MIN:DEPTH_MAX] -> speculative |
---|
| 1067 | |
---|
| 1068 | // All case |
---|
| 1069 | // ....... min ...X... max ....... OK |
---|
| 1070 | // ....... min ....... max ...X... KO |
---|
| 1071 | // ...X... min ....... max ....... KO |
---|
| 1072 | // ....... max ....... min ...X... OK |
---|
| 1073 | // ...X... max ....... min ....... OK |
---|
| 1074 | // ....... max ...X... min ....... KO |
---|
| 1075 | |
---|
| 1076 | bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
[123] | 1077 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or |
---|
[122] | 1078 | (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)); |
---|
[124] | 1079 | bool speculative = is_speculative [front_end_id][context_id]; |
---|
| 1080 | |
---|
| 1081 | // bool speculative = entry->speculative and not (depth == depth_min); |
---|
| 1082 | // Tcontrol_t is_valid = ((not speculative or |
---|
| 1083 | // (speculative and (depth_full or // all is valid |
---|
| 1084 | // ((depth_min <= depth_max)? // test if depth is overflow |
---|
| 1085 | // ((depth >= depth_min) and (depth <=depth_max)): |
---|
| 1086 | // ((depth >= depth_min) or (depth <=depth_max)))))) |
---|
| 1087 | // and not flush); // no event |
---|
| 1088 | |
---|
| 1089 | Tcontrol_t is_valid = not flush; |
---|
| 1090 | |
---|
| 1091 | |
---|
[122] | 1092 | //Tcontrol_t is_valid = ((depth == depth_min) and not flush); |
---|
| 1093 | |
---|
| 1094 | |
---|
| 1095 | log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); |
---|
[137] | 1096 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); |
---|
| 1097 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); |
---|
| 1098 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); |
---|
| 1099 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); |
---|
[122] | 1100 | log_printf(TRACE,Commit_unit,FUNCTION," * speculative : %d",speculative); |
---|
| 1101 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
[124] | 1102 | log_printf(TRACE,Commit_unit,FUNCTION," * state (before) : %s",toString(state).c_str()); |
---|
| 1103 | |
---|
| 1104 | // //------------------------------------------------------ |
---|
| 1105 | // // Event ? |
---|
| 1106 | // //------------------------------------------------------ |
---|
| 1107 | |
---|
| 1108 | // if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and |
---|
| 1109 | // (reg_EVENT_PACKET [front_end_id][context_id] == num_packet)) |
---|
| 1110 | // { |
---|
| 1111 | // switch (state) |
---|
| 1112 | // { |
---|
| 1113 | // case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
| 1114 | // case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
| 1115 | // case ROB_END_BRANCH_MISS : |
---|
| 1116 | // case ROB_END_LOAD_MISS : |
---|
| 1117 | // case ROB_END : |
---|
| 1118 | // {break;} |
---|
| 1119 | // default : |
---|
| 1120 | // { |
---|
| 1121 | // throw ERRORMORPHEO(FUNCTION,toString(_("Head [%d] : invalid state (%s)"),num_packet,toString(state).c_str())); |
---|
| 1122 | // break; |
---|
| 1123 | // } |
---|
| 1124 | // } |
---|
| 1125 | // } |
---|
[122] | 1126 | |
---|
| 1127 | //------------------------------------------------------ |
---|
| 1128 | // test if instruction is miss speculative |
---|
| 1129 | //------------------------------------------------------ |
---|
| 1130 | if (not is_valid) |
---|
| 1131 | { |
---|
| 1132 | // Change state |
---|
| 1133 | switch (state) |
---|
| 1134 | { |
---|
| 1135 | case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} |
---|
| 1136 | case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} |
---|
| 1137 | case ROB_END_BRANCH_MISS : |
---|
| 1138 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
[124] | 1139 | case ROB_END_LOAD_MISS : |
---|
[122] | 1140 | case ROB_END_LOAD_MISS_UPDATE : |
---|
| 1141 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 1142 | case ROB_STORE_OK : {state = ROB_STORE_KO ; break;} |
---|
| 1143 | case ROB_STORE_WAIT_END_OK : {state = ROB_STORE_WAIT_END_KO; break;} |
---|
| 1144 | case ROB_STORE_OK_WAIT_END : {state = ROB_STORE_KO_WAIT_END; break;} |
---|
| 1145 | case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} |
---|
| 1146 | case ROB_END_OK : |
---|
| 1147 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 1148 | case ROB_END_KO : |
---|
| 1149 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 1150 | case ROB_END_EXCEPTION_UPDATE : |
---|
| 1151 | case ROB_END_EXCEPTION : |
---|
| 1152 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} |
---|
| 1153 | |
---|
| 1154 | // don't change state -> wait |
---|
| 1155 | case ROB_STORE_WAIT_END_KO : {break;} |
---|
| 1156 | case ROB_STORE_KO : {break;} |
---|
| 1157 | case ROB_STORE_KO_WAIT_END : {break;} |
---|
| 1158 | case ROB_STORE_EVENT : {break;} |
---|
| 1159 | case ROB_EVENT_WAIT_END : {break;} |
---|
| 1160 | case ROB_END_MISS : {break;} |
---|
| 1161 | case ROB_END : {break;} |
---|
| 1162 | |
---|
| 1163 | // can't have miss speculation -> invalid state |
---|
| 1164 | default : |
---|
| 1165 | { |
---|
| 1166 | throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); |
---|
| 1167 | break; |
---|
| 1168 | } |
---|
| 1169 | } |
---|
| 1170 | } |
---|
[124] | 1171 | |
---|
| 1172 | //------------------------------------------------------ |
---|
| 1173 | // test if instruction is branch not finish |
---|
| 1174 | //------------------------------------------------------ |
---|
| 1175 | switch (state) |
---|
| 1176 | { |
---|
| 1177 | case ROB_BRANCH_WAIT_END : |
---|
| 1178 | case ROB_BRANCH_COMPLETE : |
---|
| 1179 | { |
---|
| 1180 | is_speculative [front_end_id][context_id] = true; |
---|
| 1181 | break; |
---|
| 1182 | } |
---|
| 1183 | default : break; |
---|
| 1184 | } |
---|
[122] | 1185 | |
---|
| 1186 | //------------------------------------------------------ |
---|
| 1187 | // test if instruction is not speculative |
---|
| 1188 | //------------------------------------------------------ |
---|
[124] | 1189 | // entry->speculative = speculative; |
---|
[122] | 1190 | // if (entry->depth == depth_min) |
---|
| 1191 | // test if instruction is speculative (depth != depth_min) |
---|
| 1192 | if (not speculative) |
---|
| 1193 | { |
---|
| 1194 | switch (state) |
---|
| 1195 | { |
---|
| 1196 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} |
---|
| 1197 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} |
---|
| 1198 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
| 1199 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
| 1200 | default : {break;} // else, no change |
---|
| 1201 | } |
---|
| 1202 | } |
---|
| 1203 | |
---|
| 1204 | //------------------------------------------------------ |
---|
| 1205 | // test if instruction wait head and is the top of rob |
---|
| 1206 | //------------------------------------------------------ |
---|
| 1207 | // TODO : retire OOO |
---|
| 1208 | if (i == 0) |
---|
| 1209 | { |
---|
| 1210 | switch (state) |
---|
| 1211 | { |
---|
| 1212 | // case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} |
---|
| 1213 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} |
---|
| 1214 | default : {break;} // else, no change |
---|
| 1215 | } |
---|
| 1216 | } |
---|
| 1217 | |
---|
| 1218 | // Write new state |
---|
| 1219 | entry->state = state; |
---|
[124] | 1220 | |
---|
| 1221 | log_printf(TRACE,Commit_unit,FUNCTION," * state (after ) : %s",toString(state).c_str()); |
---|
[122] | 1222 | |
---|
[124] | 1223 | // log_printf(TRACE,Commit_unit,FUNCTION," * Stop Scan !!!"); |
---|
[122] | 1224 | |
---|
[124] | 1225 | event_nb_inst [front_end_id][context_id] ++; |
---|
| 1226 | |
---|
| 1227 | // stop if : |
---|
| 1228 | // * begin event |
---|
| 1229 | // * end event |
---|
| 1230 | if (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and |
---|
| 1231 | (reg_EVENT_PACKET[front_end_id][context_id] == num_packet)) or |
---|
| 1232 | ((reg_EVENT_NB_INST [front_end_id][context_id] > 0) and |
---|
| 1233 | ( event_nb_inst [front_end_id][context_id] >= reg_EVENT_NB_INST [front_end_id][context_id]))) |
---|
| 1234 | can_continue [front_end_id][context_id] = false; |
---|
[122] | 1235 | } |
---|
| 1236 | } |
---|
| 1237 | } |
---|
| 1238 | } |
---|
[105] | 1239 | |
---|
| 1240 | |
---|
[101] | 1241 | |
---|
[122] | 1242 | #ifdef STATISTICS |
---|
[124] | 1243 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 1244 | { |
---|
| 1245 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 1246 | *(_stat_bank_nb_inst [i]) += _rob[i].size(); |
---|
| 1247 | |
---|
| 1248 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1249 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1250 | { |
---|
| 1251 | uint32_t num_thread = _param->_translate_num_context_to_num_thread [i][j]; |
---|
| 1252 | |
---|
| 1253 | switch (reg_EVENT_STATE [i][j]) |
---|
| 1254 | { |
---|
| 1255 | case COMMIT_EVENT_STATE_NO_EVENT : (*_stat_nb_cycle_state_no_event [num_thread])++; break; |
---|
| 1256 | case COMMIT_EVENT_STATE_NOT_YET_EVENT : (*_stat_nb_cycle_state_not_yet_event [num_thread])++; break; |
---|
| 1257 | case COMMIT_EVENT_STATE_EVENT : (*_stat_nb_cycle_state_event [num_thread])++; break; |
---|
| 1258 | case COMMIT_EVENT_STATE_WAIT_END : (*_stat_nb_cycle_state_wait_end [num_thread])++; break; |
---|
| 1259 | } |
---|
| 1260 | } |
---|
| 1261 | } |
---|
[122] | 1262 | #endif |
---|
[88] | 1263 | } |
---|
| 1264 | |
---|
| 1265 | // =================================================================== |
---|
| 1266 | // =====[ OTHER ]===================================================== |
---|
| 1267 | // =================================================================== |
---|
| 1268 | |
---|
[108] | 1269 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) |
---|
| 1270 | { |
---|
| 1271 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); |
---|
| 1272 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); |
---|
| 1273 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); |
---|
[122] | 1274 | log_printf(TRACE,Commit_unit,FUNCTION," * num_ptr_tail : %d",reg_NUM_PTR_TAIL ); |
---|
[108] | 1275 | |
---|
| 1276 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1277 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1278 | { |
---|
[110] | 1279 | log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]); |
---|
[122] | 1280 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str()); |
---|
| 1281 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); |
---|
[123] | 1282 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); |
---|
| 1283 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]); |
---|
| 1284 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]); |
---|
[124] | 1285 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]); |
---|
| 1286 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT : stop : %d - packet : %d",reg_EVENT_NEXT_STOP [i][j],reg_EVENT_NEXT_PACKET[i][j]); |
---|
| 1287 | log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : all : %d - mem : %d - event : %d",reg_NB_INST_COMMIT_ALL[i][j], reg_NB_INST_COMMIT_MEM[i][j],reg_EVENT_NB_INST[i][j]); |
---|
| 1288 | log_printf(TRACE,Commit_unit,FUNCTION," * PC : %.8x (%.8x) - %d %d - %.8x (%.8x)",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j],reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); |
---|
[108] | 1289 | } |
---|
| 1290 | |
---|
[122] | 1291 | std::list<entry_t*>::iterator iter [_param->_nb_bank]; |
---|
[108] | 1292 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[104] | 1293 | { |
---|
[108] | 1294 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
[122] | 1295 | // log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); |
---|
[108] | 1296 | |
---|
[122] | 1297 | iter [num_bank] = _rob[num_bank].begin(); |
---|
| 1298 | } |
---|
| 1299 | |
---|
[123] | 1300 | bool all_empty = false; |
---|
| 1301 | uint32_t nb_write_rd = 0; |
---|
| 1302 | uint32_t nb_write_re = 0; |
---|
| 1303 | |
---|
[122] | 1304 | while (not all_empty) |
---|
| 1305 | { |
---|
| 1306 | all_empty = true; |
---|
[108] | 1307 | |
---|
[122] | 1308 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[108] | 1309 | { |
---|
[122] | 1310 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
| 1311 | |
---|
| 1312 | std::list<entry_t*>::iterator it = iter[num_bank]; |
---|
| 1313 | if (it != _rob[num_bank].end()) |
---|
| 1314 | { |
---|
| 1315 | all_empty = false; |
---|
| 1316 | |
---|
[123] | 1317 | nb_write_rd += ((*it)->write_rd)?1:0; |
---|
| 1318 | nb_write_re += ((*it)->write_re)?1:0; |
---|
| 1319 | |
---|
[124] | 1320 | log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", |
---|
[122] | 1321 | num_bank , |
---|
| 1322 | (*it)->ptr , |
---|
| 1323 | (*it)->front_end_id , |
---|
| 1324 | (*it)->context_id , |
---|
| 1325 | (*it)->rename_unit_id , |
---|
| 1326 | (*it)->depth , |
---|
| 1327 | (*it)->type , |
---|
| 1328 | (*it)->operation , |
---|
| 1329 | (*it)->is_delay_slot , |
---|
| 1330 | (*it)->use_store_queue , |
---|
| 1331 | (*it)->store_queue_ptr_write , |
---|
| 1332 | (*it)->use_load_queue , |
---|
| 1333 | (*it)->load_queue_ptr_write , |
---|
| 1334 | toString((*it)->state).c_str() ); |
---|
[124] | 1335 | log_printf(TRACE,Commit_unit,FUNCTION," (%.4d) %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", |
---|
| 1336 | (((*it)->ptr << _param->_shift_num_slot) | num_bank), |
---|
[122] | 1337 | (*it)->read_ra , |
---|
| 1338 | (*it)->num_reg_ra_log , |
---|
| 1339 | (*it)->num_reg_ra_phy , |
---|
| 1340 | (*it)->read_rb , |
---|
| 1341 | (*it)->num_reg_rb_log , |
---|
| 1342 | (*it)->num_reg_rb_phy , |
---|
| 1343 | (*it)->read_rc , |
---|
| 1344 | (*it)->num_reg_rc_log , |
---|
| 1345 | (*it)->num_reg_rc_phy , |
---|
| 1346 | (*it)->write_rd , |
---|
| 1347 | (*it)->num_reg_rd_log , |
---|
| 1348 | (*it)->num_reg_rd_phy_old , |
---|
| 1349 | (*it)->num_reg_rd_phy_new , |
---|
| 1350 | (*it)->write_re , |
---|
| 1351 | (*it)->num_reg_re_log , |
---|
| 1352 | (*it)->num_reg_re_phy_old , |
---|
| 1353 | (*it)->num_reg_re_phy_new ); |
---|
| 1354 | |
---|
[124] | 1355 | log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", |
---|
[122] | 1356 | (*it)->exception_use , |
---|
| 1357 | (*it)->exception , |
---|
| 1358 | (*it)->flags , |
---|
| 1359 | (*it)->no_sequence , |
---|
[128] | 1360 | // (*it)->speculative , |
---|
[122] | 1361 | (*it)->address , |
---|
| 1362 | (*it)->address<<2 , |
---|
| 1363 | (*it)->address_next , |
---|
| 1364 | (*it)->address_next<<2 |
---|
| 1365 | ); |
---|
| 1366 | |
---|
| 1367 | iter [num_bank] ++; |
---|
| 1368 | } |
---|
[108] | 1369 | } |
---|
[104] | 1370 | } |
---|
[123] | 1371 | |
---|
| 1372 | log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_rd : %d",nb_write_rd); |
---|
| 1373 | log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_re : %d",nb_write_re); |
---|
[108] | 1374 | } |
---|
[88] | 1375 | #endif |
---|
| 1376 | |
---|
[108] | 1377 | #ifdef DEBUG_TEST |
---|
| 1378 | { |
---|
| 1379 | uint32_t x=reg_NUM_BANK_HEAD; |
---|
| 1380 | if (not _rob[x].empty()) |
---|
| 1381 | { |
---|
| 1382 | entry_t * entry = _rob [x].front(); |
---|
[97] | 1383 | |
---|
[108] | 1384 | if (false |
---|
| 1385 | // or (entry->state == ROB_EMPTY ) |
---|
| 1386 | // or (entry->state == ROB_BRANCH_WAIT_END ) |
---|
| 1387 | // or (entry->state == ROB_BRANCH_COMPLETE ) |
---|
| 1388 | // or (entry->state == ROB_STORE_WAIT_HEAD_OK ) |
---|
| 1389 | // //or (entry->state == ROB_STORE_WAIT_HEAD_KO ) |
---|
| 1390 | // or (entry->state == ROB_STORE_HEAD_OK ) |
---|
| 1391 | // or (entry->state == ROB_STORE_HEAD_KO ) |
---|
| 1392 | // or (entry->state == ROB_OTHER_WAIT_END ) |
---|
[112] | 1393 | // or (entry->state == ROB_EVENT_WAIT_END ) |
---|
[108] | 1394 | // or (entry->state == ROB_END_OK_SPECULATIVE ) |
---|
| 1395 | or (entry->state == ROB_END_OK ) |
---|
| 1396 | // or (entry->state == ROB_END_KO_SPECULATIVE ) |
---|
| 1397 | // or (entry->state == ROB_END_KO ) |
---|
| 1398 | // or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE) |
---|
| 1399 | or (entry->state == ROB_END_BRANCH_MISS ) |
---|
| 1400 | // or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE ) |
---|
| 1401 | // or (entry->state == ROB_END_LOAD_MISS_UPDATE ) |
---|
| 1402 | or (entry->state == ROB_END_LOAD_MISS ) |
---|
| 1403 | // or (entry->state == ROB_END_MISS ) |
---|
| 1404 | // or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD ) |
---|
| 1405 | // or (entry->state == ROB_END_EXCEPTION_UPDATE ) |
---|
| 1406 | // or (entry->state == ROB_END_EXCEPTION ) |
---|
| 1407 | ) |
---|
| 1408 | if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) |
---|
[122] | 1409 | throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"), |
---|
[108] | 1410 | entry->address, |
---|
| 1411 | entry->front_end_id, |
---|
| 1412 | entry->context_id, |
---|
| 1413 | reg_PC_CURRENT[entry->front_end_id][entry->context_id])); |
---|
| 1414 | } |
---|
| 1415 | } |
---|
[124] | 1416 | { |
---|
| 1417 | uint32_t NB_INST [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1418 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1419 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1420 | NB_INST [i][j] = 0; //reg_EVENT_NB_INST [i][j]; |
---|
| 1421 | |
---|
| 1422 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
---|
| 1423 | for (std::list<entry_t*>::iterator it=_rob[i].begin(); |
---|
| 1424 | it!=_rob [i].end(); |
---|
| 1425 | ++it) |
---|
| 1426 | NB_INST [(*it)->front_end_id][(*it)->context_id] ++; |
---|
| 1427 | |
---|
| 1428 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1429 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1430 | if (NB_INST [i][j] != reg_NB_INST_COMMIT_ALL [i][j]) |
---|
| 1431 | throw ERRORMORPHEO(FUNCTION,toString(_("Context [%d][%d] have not the good nb_inst (%d in rob, %d in register).\n"),i,j,NB_INST[i][j], reg_NB_INST_COMMIT_ALL [i][j])); |
---|
| 1432 | } |
---|
[108] | 1433 | #endif |
---|
[88] | 1434 | |
---|
| 1435 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 1436 | end_cycle (); |
---|
| 1437 | #endif |
---|
| 1438 | |
---|
[109] | 1439 | // Stop Condition |
---|
| 1440 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1441 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
[110] | 1442 | if (_nb_cycle_idle [i][j] >= debug_idle_cycle) |
---|
| 1443 | throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j])); |
---|
[109] | 1444 | |
---|
[88] | 1445 | log_end(Commit_unit,FUNCTION); |
---|
| 1446 | }; |
---|
| 1447 | |
---|
| 1448 | }; // end namespace commit_unit |
---|
| 1449 | }; // end namespace ooo_engine |
---|
| 1450 | }; // end namespace multi_ooo_engine |
---|
| 1451 | }; // end namespace core |
---|
| 1452 | |
---|
| 1453 | }; // end namespace behavioural |
---|
| 1454 | }; // end namespace morpheo |
---|
| 1455 | #endif |
---|