| [2] | 1 | # |
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| 2 | # $Id: Makefile.Synthesis 103 2009-01-16 16:55:32Z moulu $ |
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| 3 | # |
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| [53] | 4 | # [ Description ] |
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| [2] | 5 | # |
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| 6 | # Makefile |
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| 7 | # |
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| 8 | |
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| [53] | 9 | #-----[ Variables ]---------------------------------------- |
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| [2] | 10 | |
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| 11 | DIR_VHDL = . |
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| 12 | DIR_WORK = work |
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| 13 | |
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| 14 | FPGA_CFG_FILE_LOCAL = mkf.info |
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| 15 | FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural |
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| 16 | FPGA_CFG_FILE_GLOBAL = configure.mkf |
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| 17 | |
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| [19] | 18 | FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 19 | $(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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| 20 | |
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| 21 | FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 22 | $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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| [53] | 23 | #-----[ Rules ]-------------------------------------------- |
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| [62] | 24 | .PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log |
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| [2] | 25 | |
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| 26 | vhdl : execute $(DIR_WORK) |
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| [48] | 27 | @\ |
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| [15] | 28 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \ |
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| [2] | 29 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| [48] | 30 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ |
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| [103] | 31 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \ |
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| 32 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| 33 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ |
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| [48] | 34 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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| [2] | 35 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| [48] | 36 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; |
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| [2] | 37 | |
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| [103] | 38 | |
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| [62] | 39 | sim : vhdl |
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| [48] | 40 | @\ |
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| [15] | 41 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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| [62] | 42 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log}); \ |
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| [48] | 43 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; |
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| [2] | 44 | |
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| [62] | 45 | fpga : sim |
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| [48] | 46 | @\ |
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| 47 | $(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \ |
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| 48 | $(ECHO) "files :::::::: $(FPGA_FILES)"; \ |
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| 49 | for file in $(FPGA_FILES); do \ |
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| [2] | 50 | declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)")); \ |
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| 51 | $(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 52 | $(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 53 | $(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 54 | $(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 55 | $(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| [48] | 56 | done; \ |
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| [96] | 57 | ($(XILINX_ENV); cd $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL)); \ |
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| [48] | 58 | $(MAKE) $(FPGA_LOG_FILES); |
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| [2] | 59 | |
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| 60 | $(DIR_LOG)/%.fpga.log : |
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| [48] | 61 | @\ |
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| 62 | $(ECHO) "Synthetis on FPGA : $*"; \ |
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| 63 | $(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@; |
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| [2] | 64 | |
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| 65 | $(DIR_WORK) : |
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| [48] | 66 | @\ |
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| 67 | $(ECHO) "Create work-space : $@"; \ |
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| 68 | $(MODELTECH_VLIB) $@; |
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| [2] | 69 | |
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| [62] | 70 | $(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log |
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| [48] | 71 | @\ |
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| 72 | $(ECHO) "VHDL's Simulation : $*"; \ |
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| 73 | $(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" &> $@; \ |
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| [42] | 74 | declare -i count=`$(GREP) -ch "Test OK" $@`; \ |
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| 75 | if $(TEST) $$count -ne 0; \ |
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| [2] | 76 | then echo " $* ... OK"; \ |
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| 77 | else echo " $* ... KO"; exit 1; \ |
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| 78 | fi; |
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| 79 | |
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| 80 | $(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl |
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| [48] | 81 | @\ |
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| 82 | $(ECHO) "VHDL's Compilation : $*"; \ |
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| 83 | $(MODELTECH_VCOM) $< &> $@; |
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| [2] | 84 | |
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| 85 | synthesis_clean : |
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| [48] | 86 | @\ |
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| 87 | if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \ |
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| [103] | 88 | $(RM) $(DIR_WORK) transcript Makefile.mkf *.wlf; |
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| [2] | 89 | |
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| [88] | 90 | synthesis_clean_all : synthesis_clean |
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| 91 | |
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| [2] | 92 | synthesis_help : |
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| [48] | 93 | @\ |
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| [53] | 94 | $(ECHO) " -----[ Synthesis ]----------------------------------";\ |
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| [48] | 95 | $(ECHO) "";\ |
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| 96 | $(ECHO) " * vhdl : compile all vhdl's file";\ |
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| [62] | 97 | $(ECHO) " * sim : simulate all testbench's file";\ |
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| [48] | 98 | $(ECHO) " * fpga : synthetis with fpga's tools";\ |
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| 99 | $(ECHO) ""; |
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