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Makefile.Synthesis @ 116

Last change on this file since 116 was 116, checked in by moulu, 15 years ago
1) added a generic multiplier (systemC isn't working with 8bits) 2) added a partial functionnal unit vhdl.
Property svn:keywords set to `Id`
File size: 5.8 KB

Rev	Line
[2]	1	#
	2	# $Id: Makefile.Synthesis 116 2009-04-30 13:51:41Z moulu $
	3	#
[53]	4	# [ Description ]
[2]	5	#
	6	# Makefile
	7	#
	8
[53]	9	#-----[ Variables ]----------------------------------------
[2]	10
	11	DIR_VHDL = .
[113]	12	WORK_NAME = work
	13	DIR_WORK = $(MORPHEO_TMP)/$(WORK_NAME)
[2]	14
	15	FPGA_CFG_FILE_LOCAL = mkf.info
	16	FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural
	17	FPGA_CFG_FILE_GLOBAL = configure.mkf
	18
[19]	19	FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \
	20	$(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg))
	21
	22	FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \
	23	$(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg))
[113]	24
	25
[53]	26	#-----[ Rules ]--------------------------------------------
[62]	27	.PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log
[2]	28
[113]	29	vhdl : $(EXEC_LOG)
[48]	30	@\
[113]	31	$(MAKE) vhdl_package; \
	32	$(MAKE) vhdl_entity; \
	33	$(MAKE) vhdl_testbench
	34
	35	vhdl_package : $(DIR_WORK)
	36	@\
[15]	37	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \
[2]	38	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
[113]	39	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
	40
	41	vhdl_testbench : $(DIR_WORK)
	42	@\
[48]	43	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \
[2]	44	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
[113]	45	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
[2]	46
[113]	47	vhdl_entity : $(DIR_WORK)
	48	@\
	49	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl\|$(GREP_NOT) "(_Pack\.\|_Testbench\.)")); \
	50	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
	51	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \
[103]	52
[113]	53	#list :
	54	# @\
	55	# declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl\|$(GREP_NOT) "(_Pack\.\|_Testbench\.)")); \
	56	# for file1 in $${vhdl_files[*]}; do \
	57	# declare x=$$(basename $${file1} .vhdl); \
	58	# declare -i count_x=$($(ECHO) $${x} \| ${WC} -m); \
	59	# for file2 in $${vhdl_files[*]}; do \
	60	# if $(TEST) "$${file1}" != "$${file2}"; then\
	61	# declare y=$$(basename $${file2} .vhdl); \
	62	# declare -i count_y=$($(ECHO) $${y} \| ${WC} -m); \
	63	# if $(TEST) $${count_x} -gt $${count_y}; then \
	64	# break; \
	65	# fi; \
	66	# $(ECHO) $${x}; \
	67	# fi; \
	68	# done; \
	69	# done;
	70
[62]	71	sim : vhdl
[48]	72	@\
[15]	73	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \
[62]	74	declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log}); \
[113]	75	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
[2]	76
[62]	77	fpga : sim
[48]	78	@\
	79	$(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \
	80	$(ECHO) "files :::::::: $(FPGA_FILES)"; \
	81	for file in $(FPGA_FILES); do \
[2]	82	declare -a files=($$($(LS) $$file*.vhdl\|$(GREP_NOT) "(_Testbench\.)")); \
	83	$(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \
	84	$(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \
	85	$(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \
	86	$(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \
	87	$(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \
[48]	88	done; \
[96]	89	($(XILINX_ENV); cd $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL)); \
[113]	90	$(MAKE) -k $(FPGA_LOG_FILES);
[2]	91
	92	$(DIR_LOG)/%.fpga.log :
[48]	93	@\
	94	$(ECHO) "Synthetis on FPGA : $*"; \
	95	$(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@;
[2]	96
[116]	97	$(DIR_WORK) : $(XILINX_CORELIB)
[48]	98	@\
[113]	99	$(ECHO) "Create work-space : $@"; \
	100	$(MODELTECH_VLIB) $@; \
	101	$(MODELTECH_VMAP) $(XILINX_LIBNAME) $(XILINX_LIBDIR); \
	102	if $(TEST) $${?} -ne 0; then \
	103	$(ECHO) "Xilinx corelib must be compiled to simulation tools"; \
	104	$(ECHO) "Run manualy \"$(XILINX_COMPXLIB)\" with $(XILINX_CORELIB) directory"; \
	105	fi;
[2]	106
[116]	107	$(XILINX_CORELIB) :
	108	@\
	109	$(ECHO) "Create Corelib : $@"; \
	110	$(MODELTECH_ENV); $(XILINX_COMPXLIB)
	111
	112	# $(MODELTECH_ENV); $(XILINX_COMPXLIB) -s mti_se -arch all -lib all -l vhdl -dir $(XILINX_CORELIB) -w -p $(MODELTECH_BIN) -smartmodel_setup
	113
	114
[62]	115	$(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
[48]	116	@\
	117	$(ECHO) "VHDL's Simulation : $*"; \
	118	$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* \|$(UPPERtoLOWER)`" &> $@; \
[42]	119	declare -i count=`$(GREP) -ch "Test OK" $@`; \
	120	if $(TEST) $$count -ne 0; \
[2]	121	then echo " $* ... OK"; \
	122	else echo " $* ... KO"; exit 1; \
	123	fi;
	124
	125	$(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl
[48]	126	@\
	127	$(ECHO) "VHDL's Compilation : $*"; \
[113]	128	$(MODELTECH_VCOM) -work $(DIR_WORK) $< &> $@;
[2]	129
	130	synthesis_clean :
[48]	131	@\
	132	if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \
[113]	133	$(RM) $(DIR_WORK) transcript Makefile.mkf wlf modelsim.ini;
[2]	134
[88]	135	synthesis_clean_all : synthesis_clean
	136
[2]	137	synthesis_help :
[48]	138	@\
[53]	139	$(ECHO) " -----[ Synthesis ]----------------------------------";\
[48]	140	$(ECHO) "";\
	141	$(ECHO) " * vhdl : compile all vhdl's file";\
[62]	142	$(ECHO) " * sim : simulate all testbench's file";\
[48]	143	$(ECHO) " * fpga : synthetis with fpga's tools";\
	144	$(ECHO) "";

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