[2] | 1 | # |
---|
| 2 | # $Id$ |
---|
| 3 | # |
---|
| 4 | # [ Description ] |
---|
| 5 | # |
---|
| 6 | # Makefile |
---|
| 7 | # |
---|
| 8 | |
---|
| 9 | #-----[ Variables ]---------------------------------------- |
---|
| 10 | |
---|
| 11 | DIR_VHDL = . |
---|
| 12 | DIR_WORK = work |
---|
| 13 | |
---|
| 14 | FPGA_CFG_FILE_LOCAL = mkf.info |
---|
| 15 | FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural |
---|
| 16 | FPGA_CFG_FILE_GLOBAL = configure.mkf |
---|
| 17 | |
---|
[19] | 18 | FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
---|
| 19 | $(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
---|
| 20 | |
---|
| 21 | FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
---|
| 22 | $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
---|
[2] | 23 | #-----[ Rules ]-------------------------------------------- |
---|
| 24 | .PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.vhdl_sim.log |
---|
| 25 | |
---|
| 26 | vhdl : execute $(DIR_WORK) |
---|
[48] | 27 | @\ |
---|
[15] | 28 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \ |
---|
[2] | 29 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
---|
[48] | 30 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ |
---|
| 31 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
---|
[2] | 32 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
---|
[48] | 33 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ |
---|
[15] | 34 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \ |
---|
[2] | 35 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
---|
[48] | 36 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; |
---|
[2] | 37 | |
---|
| 38 | vhdl_sim : vhdl |
---|
[48] | 39 | @\ |
---|
[15] | 40 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
---|
[2] | 41 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl_sim.log}); \ |
---|
[48] | 42 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; |
---|
[2] | 43 | |
---|
| 44 | fpga : vhdl_sim |
---|
[48] | 45 | @\ |
---|
| 46 | $(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \ |
---|
| 47 | $(ECHO) "files :::::::: $(FPGA_FILES)"; \ |
---|
| 48 | for file in $(FPGA_FILES); do \ |
---|
[2] | 49 | declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)")); \ |
---|
| 50 | $(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \ |
---|
| 51 | $(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \ |
---|
| 52 | $(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \ |
---|
| 53 | $(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \ |
---|
| 54 | $(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \ |
---|
[48] | 55 | done; \ |
---|
| 56 | ($(XILINX_ENV); $(CD) $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL)); \ |
---|
| 57 | $(MAKE) $(FPGA_LOG_FILES); |
---|
[2] | 58 | |
---|
| 59 | $(DIR_LOG)/%.fpga.log : |
---|
[48] | 60 | @\ |
---|
| 61 | $(ECHO) "Synthetis on FPGA : $*"; \ |
---|
| 62 | $(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@; |
---|
[2] | 63 | |
---|
| 64 | $(DIR_WORK) : |
---|
[48] | 65 | @\ |
---|
| 66 | $(ECHO) "Create work-space : $@"; \ |
---|
| 67 | $(MODELTECH_VLIB) $@; |
---|
[2] | 68 | |
---|
| 69 | $(DIR_LOG)/%.vhdl_sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log |
---|
[48] | 70 | @\ |
---|
| 71 | $(ECHO) "VHDL's Simulation : $*"; \ |
---|
| 72 | $(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" &> $@; \ |
---|
[42] | 73 | declare -i count=`$(GREP) -ch "Test OK" $@`; \ |
---|
| 74 | if $(TEST) $$count -ne 0; \ |
---|
[2] | 75 | then echo " $* ... OK"; \ |
---|
| 76 | else echo " $* ... KO"; exit 1; \ |
---|
| 77 | fi; |
---|
| 78 | |
---|
| 79 | $(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl |
---|
[48] | 80 | @\ |
---|
| 81 | $(ECHO) "VHDL's Compilation : $*"; \ |
---|
| 82 | $(MODELTECH_VCOM) $< &> $@; |
---|
[2] | 83 | |
---|
| 84 | synthesis_clean : |
---|
[48] | 85 | @\ |
---|
| 86 | if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \ |
---|
| 87 | $(RM) $(DIR_WORK) transcript Makefile.mkf; |
---|
[2] | 88 | |
---|
| 89 | synthesis_help : |
---|
[48] | 90 | @\ |
---|
| 91 | $(ECHO) " -----[ Synthesis ]----------------------------------";\ |
---|
| 92 | $(ECHO) "";\ |
---|
| 93 | $(ECHO) " * vhdl : compile all vhdl's file";\ |
---|
| 94 | $(ECHO) " * vhdl_sim : simulate all testbench's file";\ |
---|
| 95 | $(ECHO) " * fpga : synthetis with fpga's tools";\ |
---|
| 96 | $(ECHO) ""; |
---|