| [2] | 1 | # |
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| 2 | # $Id$ |
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| 3 | # |
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| [53] | 4 | # [ Description ] |
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| [2] | 5 | # |
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| 6 | # Makefile |
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| 7 | # |
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| 8 | |
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| [53] | 9 | #-----[ Variables ]---------------------------------------- |
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| [2] | 10 | |
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| 11 | DIR_VHDL = . |
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| 12 | DIR_WORK = work |
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| 13 | |
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| 14 | FPGA_CFG_FILE_LOCAL = mkf.info |
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| 15 | FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural |
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| 16 | FPGA_CFG_FILE_GLOBAL = configure.mkf |
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| 17 | |
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| [19] | 18 | FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 19 | $(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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| 20 | |
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| 21 | FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 22 | $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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| [53] | 23 | #-----[ Rules ]-------------------------------------------- |
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| [62] | 24 | .PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log |
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| [2] | 25 | |
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| 26 | vhdl : execute $(DIR_WORK) |
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| [48] | 27 | @\ |
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| [15] | 28 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \ |
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| [2] | 29 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| [48] | 30 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ |
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| 31 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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| [2] | 32 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| [48] | 33 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ |
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| [15] | 34 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \ |
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| [2] | 35 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| [48] | 36 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; |
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| [2] | 37 | |
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| [62] | 38 | sim : vhdl |
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| [48] | 39 | @\ |
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| [15] | 40 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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| [62] | 41 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log}); \ |
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| [48] | 42 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; |
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| [2] | 43 | |
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| [62] | 44 | fpga : sim |
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| [48] | 45 | @\ |
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| 46 | $(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \ |
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| 47 | $(ECHO) "files :::::::: $(FPGA_FILES)"; \ |
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| 48 | for file in $(FPGA_FILES); do \ |
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| [2] | 49 | declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)")); \ |
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| 50 | $(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 51 | $(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 52 | $(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 53 | $(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 54 | $(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| [48] | 55 | done; \ |
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| [78] | 56 | ($(XILINX_ENV); cd $(FPGA_CFG_FILE_GLOBAL_DIR); $(FPGA_CFG_FILE_GLOBAL)); \ |
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| [48] | 57 | $(MAKE) $(FPGA_LOG_FILES); |
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| [2] | 58 | |
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| 59 | $(DIR_LOG)/%.fpga.log : |
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| [48] | 60 | @\ |
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| 61 | $(ECHO) "Synthetis on FPGA : $*"; \ |
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| 62 | $(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@; |
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| [2] | 63 | |
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| 64 | $(DIR_WORK) : |
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| [48] | 65 | @\ |
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| 66 | $(ECHO) "Create work-space : $@"; \ |
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| 67 | $(MODELTECH_VLIB) $@; |
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| [2] | 68 | |
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| [62] | 69 | $(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log |
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| [48] | 70 | @\ |
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| 71 | $(ECHO) "VHDL's Simulation : $*"; \ |
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| 72 | $(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" &> $@; \ |
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| [42] | 73 | declare -i count=`$(GREP) -ch "Test OK" $@`; \ |
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| 74 | if $(TEST) $$count -ne 0; \ |
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| [2] | 75 | then echo " $* ... OK"; \ |
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| 76 | else echo " $* ... KO"; exit 1; \ |
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| 77 | fi; |
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| 78 | |
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| 79 | $(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl |
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| [48] | 80 | @\ |
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| 81 | $(ECHO) "VHDL's Compilation : $*"; \ |
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| 82 | $(MODELTECH_VCOM) $< &> $@; |
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| [2] | 83 | |
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| 84 | synthesis_clean : |
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| [48] | 85 | @\ |
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| 86 | if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \ |
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| [68] | 87 | $(RM) $(DIR_WORK) transcript Makefile.mkf $(FPGA_CFG_FILE_LOCAL) *.wlf; |
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| [2] | 88 | |
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| 89 | synthesis_help : |
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| [48] | 90 | @\ |
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| [53] | 91 | $(ECHO) " -----[ Synthesis ]----------------------------------";\ |
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| [48] | 92 | $(ECHO) "";\ |
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| 93 | $(ECHO) " * vhdl : compile all vhdl's file";\ |
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| [62] | 94 | $(ECHO) " * sim : simulate all testbench's file";\ |
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| [48] | 95 | $(ECHO) " * fpga : synthetis with fpga's tools";\ |
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| 96 | $(ECHO) ""; |
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