Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit
- Timestamp:
- Jan 15, 2009, 6:19:08 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h
r88 r101 133 133 // Address's Read must be aligned 134 134 135 if ((address & _mask_addr) != 0)136 TEST_KO("<Memory_t::read> Address is not aligned");135 // if ((address & _mask_addr) != 0) 136 // TEST_KO("<Memory_t::read> Address is not aligned"); 137 137 138 138 if (context>_nb_context) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp
r81 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMealy_dcache (void) 25 25 { 26 log_ printf(FUNC,Load_store_unit,FUNCTION,"Begin");27 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");26 log_begin(Load_store_unit,FUNCTION); 27 log_end (Load_store_unit,FUNCTION); 28 28 }; 29 29 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
r88 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMealy_insert (void) 25 25 { 26 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 26 log_begin(Load_store_unit,FUNCTION); 27 log_function(Load_store_unit,FUNCTION,_name.c_str()); 27 28 28 29 // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 52 53 PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]); 53 54 54 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");55 log_end(Load_store_unit,FUNCTION); 55 56 }; 56 57 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp
r81 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMealy_retire (void) 25 25 { 26 log_ printf(FUNC,Load_store_unit,FUNCTION,"Begin");27 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");26 log_begin(Load_store_unit,FUNCTION); 27 log_end (Load_store_unit,FUNCTION); 28 28 }; 29 29 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r97 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMoore (void) 25 25 { 26 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 26 log_begin(Load_store_unit,FUNCTION); 27 log_function(Load_store_unit,FUNCTION,_name.c_str()); 27 28 28 29 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 44 45 // Test store and load queue 45 46 46 log_printf(TRACE,Load_store_unit,FUNCTION," genMoore :Test MEMORY_OUT");47 48 log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue");47 log_printf(TRACE,Load_store_unit,FUNCTION," * Test MEMORY_OUT"); 48 49 log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue"); 49 50 for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++) 50 51 // for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++) … … 71 72 _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed, 72 73 _load_queue [internal_MEMORY_OUT_PTR]._access_size); 73 log_printf(TRACE,Load_store_unit,FUNCTION," * data : %.8x",data_new); 74 log_printf(TRACE,Load_store_unit,FUNCTION," * data (old) : %.8x",data_old); 75 log_printf(TRACE,Load_store_unit,FUNCTION," * data (new) : %.8x",data_new); 74 76 log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata); 75 77 log_printf(TRACE,Load_store_unit,FUNCTION," * shift : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift); … … 91 93 if (not internal_MEMORY_OUT_VAL) 92 94 { 93 log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue");95 log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); 94 96 if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) 95 97 { … … 143 145 Tdcache_data_t dcache_req_wdata ; 144 146 145 log_printf(TRACE,Load_store_unit,FUNCTION," genMoore :Test DCACHE_REQ");147 log_printf(TRACE,Load_store_unit,FUNCTION," * Test DCACHE_REQ"); 146 148 147 149 internal_DCACHE_REQ_VAL = 0; … … 152 154 if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE) 153 155 { 154 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue[%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);156 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ); 155 157 156 158 internal_DCACHE_REQ_VAL = 1; … … 169 171 170 172 dcache_req_packet_id = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write); 171 dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address & _param->_mask_address_msb;173 dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb; 172 174 dcache_req_type = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation); 175 176 // log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address); 177 // log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %.8x",_param->_mask_address_msb); 178 log_printf(TRACE,Load_store_unit,FUNCTION," * dcache_req_address : %.8x",dcache_req_address); 179 173 180 #ifdef SYSTEMC_VHDL_COMPATIBILITY 174 181 dcache_req_wdata = 0; … … 210 217 PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); 211 218 212 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");219 log_end(Load_store_unit,FUNCTION); 213 220 }; 214 221 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r97 r101 260 260 ( internal_MEMORY_IN_ACK == 1)) 261 261 { 262 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_IN [%d]",internal_MEMORY_IN_PORT); 263 262 264 // Test operation : 263 265 //~~~~~~~~~~~~~~~~~ … … 440 442 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 441 443 { 442 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT transaction");444 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction"); 443 445 444 446 switch (internal_MEMORY_OUT_SELECT_QUEUE) … … 498 500 (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) 499 501 { 500 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ ");502 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ[0]"); 501 503 502 504 switch (internal_DCACHE_REQ_SELECT_QUEUE) … … 602 604 ( internal_DCACHE_RSP_ACK == 1)) 603 605 { 604 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP ");606 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP [0]"); 605 607 606 608 // don't use context_id : because there are one queue for all thread … … 610 612 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); 611 613 612 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); 614 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); 615 log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); 616 log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); 613 617 614 618 if (DCACHE_RSP_IS_LOAD(packet_id) == 1) … … 623 627 throw ErrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons.")); 624 628 #endif 625 629 630 _load_queue [packet_id]._rdata = rdata; 626 631 627 632 if (error != DCACHE_ERROR_NONE) … … 639 644 // FIXME : convention : if bus error, the cache return the fautive address ! 640 645 // But, the load's address is aligned ! 641 _load_queue [packet_id]._rdata = rdata; 642 646 643 647 switch (_load_queue [packet_id]._state) 644 648 { … … 695 699 uint32_t j = (*_speculative_access_queue_control)[i]; 696 700 697 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %. 6d, %.2d, %s",701 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s", 698 702 j, 699 703 _speculative_access_queue[j]._context_id , … … 719 723 uint32_t j = i; 720 724 721 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %. 6d, %.2d, %s",725 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s", 722 726 j, 723 727 _load_queue[j]._context_id ,
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